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@@ -0,0 +1,22111 @@
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+/**
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+ ******************************************************************************
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+ * @file stm32f769xx.h
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+ * @author MCD Application Team
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+ * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
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+ *
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+ * This file contains:
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+ * - Data structures and the address mapping for all peripherals
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+ * - Peripheral's registers declarations and bits definition
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+ * - Macros to access peripheral's registers hardware
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+ *
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+ ******************************************************************************
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+ * @attention
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+ *
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+ * Copyright (c) 2016 STMicroelectronics.
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+ * All rights reserved.
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+ *
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+ * This software is licensed under terms that can be found in the LICENSE file
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+ * in the root directory of this software component.
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+ * If no LICENSE file comes with this software, it is provided AS-IS.
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+ *
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+ ******************************************************************************
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+ */
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+
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+/** @addtogroup CMSIS_Device
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+ * @{
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+ */
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+
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+/** @addtogroup stm32f769xx
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+ * @{
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+ */
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+
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+#ifndef __STM32F769xx_H
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+#define __STM32F769xx_H
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+
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+#ifdef __cplusplus
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+ extern "C" {
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+#endif /* __cplusplus */
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+
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+/** @addtogroup Configuration_section_for_CMSIS
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+ * @{
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+ */
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+
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+/**
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+ * @brief STM32F7xx Interrupt Number Definition, according to the selected device
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+ * in @ref Library_configuration_section
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+ */
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+typedef enum
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+{
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+/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
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+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
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+ BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
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+ UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
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+ SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
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+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
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+ PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
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+ SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
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+/****** STM32 specific Interrupt Numbers **********************************************************************/
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+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
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+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
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+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
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+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
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+ RCC_IRQn = 5, /*!< RCC global Interrupt */
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+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
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+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
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+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
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+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
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+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
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+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
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+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
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+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
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+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
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+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
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+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
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+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
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+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
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+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
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+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
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+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
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+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
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+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
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+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
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+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
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+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
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+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
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+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
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+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
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+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
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+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
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+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
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+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
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+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
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+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
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+ FMC_IRQn = 48, /*!< FMC global Interrupt */
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+ SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
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+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
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+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
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+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
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+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
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+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
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+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
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+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
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+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
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+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
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+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
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+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
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+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
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+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
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+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
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+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
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+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
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+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
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+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
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+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
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+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
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+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
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+ USART6_IRQn = 71, /*!< USART6 global interrupt */
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+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
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+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
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+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
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+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
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+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
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+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
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+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
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+ RNG_IRQn = 80, /*!< RNG global interrupt */
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+ FPU_IRQn = 81, /*!< FPU global interrupt */
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+ UART7_IRQn = 82, /*!< UART7 global interrupt */
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+ UART8_IRQn = 83, /*!< UART8 global interrupt */
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+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
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+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
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+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
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+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
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+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */
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+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
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+ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
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+ SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
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+ QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
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+ LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
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+ CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
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+ I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
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+ I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
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+ SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
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+ DSI_IRQn = 98, /*!< DSI global Interrupt */
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+ DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */
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+ DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */
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+ DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */
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+ DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */
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+ SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */
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+ CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */
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+ CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */
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+ CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */
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+ CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */
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+ JPEG_IRQn = 108, /*!< JPEG global Interrupt */
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+ MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */
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+} IRQn_Type;
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+
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+/**
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+ * @}
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+ */
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+
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+/**
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+ * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
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+ */
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+#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
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+#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
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+#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
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+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
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+#define __FPU_PRESENT 1U /*!< FPU present */
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+#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
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+#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
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+#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
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+
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+
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+#include "system_stm32f7xx.h"
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+#include <stdint.h>
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+
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+/** @addtogroup Peripheral_registers_structures
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+ * @{
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+ */
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+
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+/**
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+ * @brief Analog to Digital Converter
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+ */
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+
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+typedef struct
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+{
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+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
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+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
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+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
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+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
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+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
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+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
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+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
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+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
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+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
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+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
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+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
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+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
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+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
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+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
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+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
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+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
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+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
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+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
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+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
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+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
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+} ADC_TypeDef;
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+
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+typedef struct
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+{
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+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
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+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
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+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
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+ AND triple modes, Address offset: ADC1 base address + 0x308 */
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+} ADC_Common_TypeDef;
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+
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+
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+/**
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+ * @brief Controller Area Network TxMailBox
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+ */
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+
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+typedef struct
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+{
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+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
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+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
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+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
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+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
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+} CAN_TxMailBox_TypeDef;
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+
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+/**
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+ * @brief Controller Area Network FIFOMailBox
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+ */
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+
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+typedef struct
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+{
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+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
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+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
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+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
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+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
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+} CAN_FIFOMailBox_TypeDef;
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+
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+/**
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+ * @brief Controller Area Network FilterRegister
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+ */
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+
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+typedef struct
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+{
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+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
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+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
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+} CAN_FilterRegister_TypeDef;
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+
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+/**
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+ * @brief Controller Area Network
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+ */
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+
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+typedef struct
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+{
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+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
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+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
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+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
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+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
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+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
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+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
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+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
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+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
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+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
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+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
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+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
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+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
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+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
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+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
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+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
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+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
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+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
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+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
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+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
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+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
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+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
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+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
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+} CAN_TypeDef;
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+
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+/**
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+ * @brief HDMI-CEC
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+ */
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+
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+typedef struct
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+{
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+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
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+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
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+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
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+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
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+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
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+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
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+}CEC_TypeDef;
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+
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+/**
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+ * @brief CRC calculation unit
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+ */
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+
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+typedef struct
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+{
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+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
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+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
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+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
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+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
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+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
|
|
|
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
|
|
|
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
|
|
|
+} CRC_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Digital to Analog Converter
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
|
|
|
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
|
|
|
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
|
|
|
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
|
|
|
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
|
|
|
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
|
|
|
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
|
|
|
+} DAC_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief DFSDM module registers
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
|
|
|
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
|
|
|
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
|
|
|
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
|
|
|
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
|
|
|
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
|
|
|
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
|
|
|
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
|
|
|
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
|
|
|
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
|
|
|
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
|
|
|
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
|
|
|
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
|
|
|
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
|
|
|
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
|
|
|
+} DFSDM_Filter_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief DFSDM channel configuration registers
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
|
|
|
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
|
|
|
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
|
|
|
+ short circuit detector register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
|
|
|
+} DFSDM_Channel_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Debug MCU
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
|
|
|
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
|
|
|
+}DBGMCU_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief DCMI
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
|
|
|
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
|
|
|
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
|
|
|
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
|
|
|
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
|
|
|
+} DCMI_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief DMA Controller
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
|
|
|
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
|
|
|
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
|
|
|
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
|
|
|
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
|
|
|
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
|
|
|
+} DMA_Stream_TypeDef;
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
|
|
|
+} DMA_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief DMA2D Controller
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
|
|
|
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
|
|
|
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
|
|
|
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
|
|
|
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
|
|
|
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
|
|
|
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
|
|
|
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
|
|
|
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
|
|
|
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
|
|
|
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
|
|
|
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
|
|
|
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
|
|
|
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
|
|
|
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
|
|
|
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
|
|
|
+} DMA2D_TypeDef;
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Ethernet MAC
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t MACCR;
|
|
|
+ __IO uint32_t MACFFR;
|
|
|
+ __IO uint32_t MACHTHR;
|
|
|
+ __IO uint32_t MACHTLR;
|
|
|
+ __IO uint32_t MACMIIAR;
|
|
|
+ __IO uint32_t MACMIIDR;
|
|
|
+ __IO uint32_t MACFCR;
|
|
|
+ __IO uint32_t MACVLANTR; /* 8 */
|
|
|
+ uint32_t RESERVED0[2];
|
|
|
+ __IO uint32_t MACRWUFFR; /* 11 */
|
|
|
+ __IO uint32_t MACPMTCSR;
|
|
|
+ uint32_t RESERVED1;
|
|
|
+ __IO uint32_t MACDBGR;
|
|
|
+ __IO uint32_t MACSR; /* 15 */
|
|
|
+ __IO uint32_t MACIMR;
|
|
|
+ __IO uint32_t MACA0HR;
|
|
|
+ __IO uint32_t MACA0LR;
|
|
|
+ __IO uint32_t MACA1HR;
|
|
|
+ __IO uint32_t MACA1LR;
|
|
|
+ __IO uint32_t MACA2HR;
|
|
|
+ __IO uint32_t MACA2LR;
|
|
|
+ __IO uint32_t MACA3HR;
|
|
|
+ __IO uint32_t MACA3LR; /* 24 */
|
|
|
+ uint32_t RESERVED2[40];
|
|
|
+ __IO uint32_t MMCCR; /* 65 */
|
|
|
+ __IO uint32_t MMCRIR;
|
|
|
+ __IO uint32_t MMCTIR;
|
|
|
+ __IO uint32_t MMCRIMR;
|
|
|
+ __IO uint32_t MMCTIMR; /* 69 */
|
|
|
+ uint32_t RESERVED3[14];
|
|
|
+ __IO uint32_t MMCTGFSCCR; /* 84 */
|
|
|
+ __IO uint32_t MMCTGFMSCCR;
|
|
|
+ uint32_t RESERVED4[5];
|
|
|
+ __IO uint32_t MMCTGFCR;
|
|
|
+ uint32_t RESERVED5[10];
|
|
|
+ __IO uint32_t MMCRFCECR;
|
|
|
+ __IO uint32_t MMCRFAECR;
|
|
|
+ uint32_t RESERVED6[10];
|
|
|
+ __IO uint32_t MMCRGUFCR;
|
|
|
+ uint32_t RESERVED7[334];
|
|
|
+ __IO uint32_t PTPTSCR;
|
|
|
+ __IO uint32_t PTPSSIR;
|
|
|
+ __IO uint32_t PTPTSHR;
|
|
|
+ __IO uint32_t PTPTSLR;
|
|
|
+ __IO uint32_t PTPTSHUR;
|
|
|
+ __IO uint32_t PTPTSLUR;
|
|
|
+ __IO uint32_t PTPTSAR;
|
|
|
+ __IO uint32_t PTPTTHR;
|
|
|
+ __IO uint32_t PTPTTLR;
|
|
|
+ __IO uint32_t RESERVED8;
|
|
|
+ __IO uint32_t PTPTSSR;
|
|
|
+ __IO uint32_t PTPPPSCR;
|
|
|
+ uint32_t RESERVED9[564];
|
|
|
+ __IO uint32_t DMABMR;
|
|
|
+ __IO uint32_t DMATPDR;
|
|
|
+ __IO uint32_t DMARPDR;
|
|
|
+ __IO uint32_t DMARDLAR;
|
|
|
+ __IO uint32_t DMATDLAR;
|
|
|
+ __IO uint32_t DMASR;
|
|
|
+ __IO uint32_t DMAOMR;
|
|
|
+ __IO uint32_t DMAIER;
|
|
|
+ __IO uint32_t DMAMFBOCR;
|
|
|
+ __IO uint32_t DMARSWTR;
|
|
|
+ uint32_t RESERVED10[8];
|
|
|
+ __IO uint32_t DMACHTDR;
|
|
|
+ __IO uint32_t DMACHRDR;
|
|
|
+ __IO uint32_t DMACHTBAR;
|
|
|
+ __IO uint32_t DMACHRBAR;
|
|
|
+} ETH_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief External Interrupt/Event Controller
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
|
|
|
+} EXTI_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief FLASH Registers
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
|
|
|
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
|
|
|
+} FLASH_TypeDef;
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Flexible Memory Controller
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
|
|
|
+} FMC_Bank1_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Flexible Memory Controller Bank1E
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
|
|
|
+} FMC_Bank1E_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Flexible Memory Controller Bank3
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
|
|
|
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
|
|
|
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
|
|
|
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
|
|
|
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */
|
|
|
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
|
|
|
+} FMC_Bank3_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Flexible Memory Controller Bank5_6
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
|
|
|
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
|
|
|
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
|
|
|
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
|
|
|
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
|
|
|
+} FMC_Bank5_6_TypeDef;
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief General Purpose I/O
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
|
|
|
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
|
|
+} GPIO_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief System configuration controller
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
|
|
|
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
|
|
|
+ __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
|
|
|
+} SYSCFG_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Inter-integrated Circuit Interface
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
|
|
|
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
|
|
|
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
|
|
|
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
|
|
|
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
|
|
|
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
|
|
|
+} I2C_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Independent WATCHDOG
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
|
|
|
+} IWDG_TypeDef;
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief LCD-TFT Display Controller
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
|
|
|
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
|
|
|
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
|
|
|
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
|
|
|
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
|
|
|
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
|
|
|
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
|
|
|
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
|
|
|
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
|
|
|
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
|
|
|
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
|
|
|
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
|
|
|
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
|
|
|
+} LTDC_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief LCD-TFT Display layer x Controller
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
|
|
|
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
|
|
|
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
|
|
|
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
|
|
|
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
|
|
|
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
|
|
|
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
|
|
|
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
|
|
|
+ uint32_t RESERVED0[2]; /*!< Reserved */
|
|
|
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
|
|
|
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
|
|
|
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
|
|
|
+ uint32_t RESERVED1[3]; /*!< Reserved */
|
|
|
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
|
|
|
+
|
|
|
+} LTDC_Layer_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Power Control
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
|
|
|
+ __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
|
|
|
+ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
|
|
|
+ __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
|
|
|
+} PWR_TypeDef;
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Reset and Clock Control
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
|
|
|
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
|
|
|
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
|
|
|
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
|
|
|
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
|
|
|
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
|
|
|
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
|
|
|
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
|
|
|
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
|
|
|
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
|
|
|
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
|
|
|
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
|
|
|
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
|
|
|
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
|
|
|
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
|
|
|
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
|
|
|
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
|
|
|
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
|
|
|
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
|
|
|
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
|
|
|
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
|
|
|
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
|
|
|
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
|
|
|
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
|
|
|
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
|
|
|
+ __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
|
|
|
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
|
|
|
+
|
|
|
+} RCC_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Real-Time Clock
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
|
|
|
+ uint32_t reserved; /*!< Reserved */
|
|
|
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
|
|
|
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
|
|
|
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
|
|
|
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
|
|
|
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
|
|
|
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
|
|
|
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
|
|
|
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
|
|
|
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
|
|
|
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
|
|
|
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
|
|
|
+ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
|
|
|
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
|
|
|
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
|
|
|
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
|
|
|
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
|
|
|
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
|
|
|
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
|
|
|
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
|
|
|
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
|
|
|
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
|
|
|
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
|
|
|
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
|
|
|
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
|
|
|
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
|
|
|
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
|
|
|
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
|
|
|
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
|
|
|
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
|
|
|
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
|
|
|
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
|
|
|
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
|
|
|
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
|
|
|
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
|
|
|
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
|
|
|
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
|
|
|
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
|
|
|
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
|
|
|
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
|
|
|
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
|
|
|
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
|
|
|
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
|
|
|
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
|
|
|
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
|
|
|
+} RTC_TypeDef;
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Serial Audio Interface
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
|
|
|
+} SAI_TypeDef;
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
|
|
|
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
|
|
|
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
|
|
|
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
|
|
|
+} SAI_Block_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief SPDIF-RX Interface
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
|
|
|
+} SPDIFRX_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief SD host Interface
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
|
|
|
+ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
|
|
|
+ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
|
|
|
+ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
|
|
|
+ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
|
|
|
+ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
|
|
|
+ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
|
|
|
+ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
|
|
|
+ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
|
|
|
+ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
|
|
|
+ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
|
|
|
+ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
|
|
|
+ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
|
|
|
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
|
|
|
+ __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
|
|
|
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
|
|
|
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
|
|
|
+} SDMMC_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Serial Peripheral Interface
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
|
|
|
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
|
|
|
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
|
|
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
|
|
|
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
|
|
|
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
|
|
+} SPI_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief QUAD Serial Peripheral Interface
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
|
|
|
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
|
|
|
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
|
|
|
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
|
|
|
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
|
|
|
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
|
|
|
+} QUADSPI_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief TIM
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
|
|
|
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
|
|
|
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
|
|
|
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
|
|
|
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
|
|
|
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
|
|
|
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
|
|
|
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
|
|
|
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
|
|
|
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
|
|
|
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
|
|
|
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
|
|
|
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
|
|
|
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
|
|
|
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
|
|
|
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
|
|
|
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
|
|
|
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
|
|
|
+ __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
|
|
|
+ __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
|
|
|
+ __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */
|
|
|
+ __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */
|
|
|
+
|
|
|
+} TIM_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief LPTIMIMER
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
|
|
|
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
|
|
|
+} LPTIM_TypeDef;
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
|
|
|
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
|
|
|
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
|
|
|
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
|
|
|
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
|
|
|
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
|
|
|
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
|
|
|
+} USART_TypeDef;
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Window WATCHDOG
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
|
|
|
+} WWDG_TypeDef;
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief RNG
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
|
|
|
+} RNG_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief USB_OTG_Core_Registers
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
|
|
|
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
|
|
|
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
|
|
|
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
|
|
|
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
|
|
|
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
|
|
|
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
|
|
|
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
|
|
|
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
|
|
|
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
|
|
|
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
|
|
|
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
|
|
|
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
|
|
|
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
|
|
|
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
|
|
|
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
|
|
|
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
|
|
|
+ uint32_t Reserved6; /*!< Reserved 050h */
|
|
|
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
|
|
|
+ uint32_t Reserved7; /*!< Reserved 058h */
|
|
|
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
|
|
|
+ uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */
|
|
|
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
|
|
|
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */
|
|
|
+} USB_OTG_GlobalTypeDef;
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief USB_OTG_device_Registers
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
|
|
|
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
|
|
|
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
|
|
|
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
|
|
|
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
|
|
|
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
|
|
|
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
|
|
|
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
|
|
|
+ uint32_t Reserved20; /*!< Reserved 820h */
|
|
|
+ uint32_t Reserved9; /*!< Reserved 824h */
|
|
|
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
|
|
|
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
|
|
|
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
|
|
|
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
|
|
|
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
|
|
|
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
|
|
|
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
|
|
|
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
|
|
|
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
|
|
|
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
|
|
|
+} USB_OTG_DeviceTypeDef;
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
|
|
|
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
|
|
|
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
|
|
|
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
|
|
|
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
|
|
|
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
|
|
|
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
|
|
|
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
|
|
|
+} USB_OTG_INEndpointTypeDef;
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
|
|
|
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
|
|
|
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
|
|
|
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
|
|
|
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
|
|
|
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
|
|
|
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
|
|
|
+} USB_OTG_OUTEndpointTypeDef;
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief USB_OTG_Host_Mode_Register_Structures
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
|
|
|
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
|
|
|
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
|
|
|
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
|
|
|
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
|
|
|
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
|
|
|
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
|
|
|
+} USB_OTG_HostTypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief USB_OTG_Host_Channel_Specific_Registers
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
|
|
|
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
|
|
|
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
|
|
|
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
|
|
|
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
|
|
|
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
|
|
|
+ uint32_t Reserved[2]; /*!< Reserved */
|
|
|
+} USB_OTG_HostChannelTypeDef;
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief JPEG Codec
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
|
|
|
+ __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
|
|
|
+ __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
|
|
|
+ __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
|
|
|
+ __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
|
|
|
+ __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
|
|
|
+ __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
|
|
|
+ __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
|
|
|
+ uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
|
|
|
+ __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
|
|
|
+ __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
|
|
|
+ __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
|
|
|
+ uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
|
|
|
+ __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
|
|
|
+ __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
|
|
|
+ uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
|
|
|
+ __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
|
|
|
+ __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
|
|
|
+ __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
|
|
|
+ __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
|
|
|
+ __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
|
|
|
+ __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
|
|
|
+ __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
|
|
|
+ __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
|
|
|
+ uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
|
|
|
+ __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */
|
|
|
+ __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */
|
|
|
+ __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */
|
|
|
+ __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */
|
|
|
+
|
|
|
+} JPEG_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief MDIOS
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */
|
|
|
+ __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */
|
|
|
+ __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */
|
|
|
+ __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */
|
|
|
+ __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */
|
|
|
+ __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */
|
|
|
+ __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */
|
|
|
+ uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
|
|
|
+ __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */
|
|
|
+ __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */
|
|
|
+ __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */
|
|
|
+ __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */
|
|
|
+ __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */
|
|
|
+ __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */
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+ __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */
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+ __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */
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+ __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */
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+ __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */
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+ __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */
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|
+ __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */
|
|
|
+ __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */
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|
+ __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */
|
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|
+ __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */
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+ __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */
|
|
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+ __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */
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+ __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */
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+ __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */
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+ __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */
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|
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+ __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */
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+ __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */
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+ __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */
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+ __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */
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+ __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */
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+ __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */
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+ __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */
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+ __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */
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+ __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */
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+ __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */
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+ __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */
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+ __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */
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+ __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */
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+ __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */
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+ __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */
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+ __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */
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+ __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */
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+ __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */
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+ __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */
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+ __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */
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+ __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */
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+ __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */
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+ __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */
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+ __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */
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+ __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */
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+ __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */
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+ __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */
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+ __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */
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+ __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */
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+ __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */
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+ __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */
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+ __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */
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+ __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */
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+ __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */
|
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+ __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */
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+ __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */
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+ __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */
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+ __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */
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|
|
+ __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */
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|
|
+ __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */
|
|
|
+ __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */
|
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|
+ __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */
|
|
|
+ __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */
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+ __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */
|
|
|
+} MDIOS_TypeDef;
|
|
|
+
|
|
|
+/**
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|
|
+ * @brief DSI Controller
|
|
|
+ */
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|
|
+
|
|
|
+typedef struct
|
|
|
+{
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|
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+ __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
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+ __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
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|
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+ __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
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|
+ __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
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|
+ __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
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|
+ __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
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|
|
+ __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
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|
+ uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
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|
+ __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
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+ __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
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|
+ __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
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|
+ __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
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|
+ __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
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|
+ __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
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|
+ __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
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+ __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
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|
+ __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
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+ __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
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+ __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
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+ __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
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+ __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
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+ __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
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+ __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
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+ __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
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+ __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
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+ __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
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|
+ __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
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+ __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
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|
+ __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
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|
+ __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
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+ __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
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|
+ __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
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+ __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
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|
+ __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
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|
+ __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
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+ __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
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+ __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
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+ uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
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|
+ __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
|
|
|
+ __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
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|
+ uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
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|
+ __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
|
|
|
+ uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
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|
+ __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
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|
+ uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
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+ __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
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|
+ __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
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|
+ uint32_t RESERVED5; /*!< Reserved, 0x114 */
|
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|
+ __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
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|
+ uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
|
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+ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
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+ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
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|
+ __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
|
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|
+ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
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|
+ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
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|
+ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
|
|
|
+ __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
|
|
|
+ __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
|
|
|
+ __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
|
|
|
+ __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
|
|
|
+ __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
|
|
|
+ uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
|
|
|
+ __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
|
|
|
+ uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
|
|
|
+ __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
|
|
|
+ __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
|
|
|
+ __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
|
|
|
+ __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
|
|
|
+ __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
|
|
|
+ uint32_t RESERVED9; /*!< Reserved, 0x414 */
|
|
|
+ __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
|
|
|
+ uint32_t RESERVED10; /*!< Reserved, 0x42C */
|
|
|
+ __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
|
|
|
+} DSI_TypeDef;
|
|
|
+
|
|
|
+/** @addtogroup Peripheral_memory_map
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+#define RAMITCM_BASE 0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
|
|
|
+#define FLASHITCM_BASE 0x00200000UL /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */
|
|
|
+#define FLASHAXI_BASE 0x08000000UL /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
|
|
|
+#define RAMDTCM_BASE 0x20000000UL /*!< Base address of : 128KB system data RAM accessible over DTCM */
|
|
|
+#define PERIPH_BASE 0x40000000UL /*!< Base address of : AHB/ABP Peripherals */
|
|
|
+#define BKPSRAM_BASE 0x40024000UL /*!< Base address of : Backup SRAM(4 KB) */
|
|
|
+#define QSPI_BASE 0x90000000UL /*!< Base address of : QSPI memories accessible over AXI */
|
|
|
+#define FMC_R_BASE 0xA0000000UL /*!< Base address of : FMC Control registers */
|
|
|
+#define QSPI_R_BASE 0xA0001000UL /*!< Base address of : QSPI Control registers */
|
|
|
+#define SRAM1_BASE 0x20020000UL /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */
|
|
|
+#define SRAM2_BASE 0x2007C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
|
|
|
+#define FLASH_END 0x081FFFFFUL /*!< FLASH end address */
|
|
|
+#define FLASH_OTP_BASE 0x1FF0F000UL /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */
|
|
|
+#define FLASH_OTP_END 0x1FF0F41FUL /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */
|
|
|
+
|
|
|
+/* Legacy define */
|
|
|
+#define FLASH_BASE FLASHAXI_BASE
|
|
|
+
|
|
|
+/*!< Peripheral memory map */
|
|
|
+#define APB1PERIPH_BASE PERIPH_BASE
|
|
|
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
|
|
|
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
|
|
|
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
|
|
|
+
|
|
|
+/*!< APB1 peripherals */
|
|
|
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
|
|
|
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
|
|
|
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
|
|
|
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
|
|
|
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
|
|
|
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
|
|
|
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
|
|
|
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
|
|
|
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
|
|
|
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)
|
|
|
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
|
|
|
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
|
|
|
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
|
|
|
+#define CAN3_BASE (APB1PERIPH_BASE + 0x3400UL)
|
|
|
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
|
|
|
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
|
|
|
+#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL)
|
|
|
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
|
|
|
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
|
|
|
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
|
|
|
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
|
|
|
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
|
|
|
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
|
|
|
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
|
|
|
+#define I2C4_BASE (APB1PERIPH_BASE + 0x6000UL)
|
|
|
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
|
|
|
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
|
|
|
+#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL)
|
|
|
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
|
|
|
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
|
|
|
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
|
|
|
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
|
|
|
+
|
|
|
+/*!< APB2 peripherals */
|
|
|
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
|
|
|
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
|
|
|
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
|
|
|
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
|
|
|
+#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00UL)
|
|
|
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
|
|
|
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
|
|
|
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
|
|
|
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL)
|
|
|
+#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL)
|
|
|
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
|
|
|
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
|
|
|
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
|
|
|
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
|
|
|
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
|
|
|
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
|
|
|
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
|
|
|
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
|
|
|
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL)
|
|
|
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
|
|
|
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL)
|
|
|
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
|
|
|
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
|
|
|
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
|
|
|
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
|
|
|
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL)
|
|
|
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL)
|
|
|
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL)
|
|
|
+#define DSI_BASE (APB2PERIPH_BASE + 0x6C00UL)
|
|
|
+#define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400UL)
|
|
|
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
|
|
|
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
|
|
|
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
|
|
|
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
|
|
|
+#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
|
|
|
+#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
|
|
|
+#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
|
|
|
+#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
|
|
|
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
|
|
|
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
|
|
|
+#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
|
|
|
+#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
|
|
|
+#define MDIOS_BASE (APB2PERIPH_BASE + 0x7800UL)
|
|
|
+/*!< AHB1 peripherals */
|
|
|
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
|
|
|
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
|
|
|
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
|
|
|
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
|
|
|
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
|
|
|
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
|
|
|
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
|
|
|
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
|
|
|
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
|
|
|
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL)
|
|
|
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL)
|
|
|
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
|
|
|
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
|
|
|
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
|
|
|
+#define UID_BASE 0x1FF0F420UL /*!< Unique device ID register base address */
|
|
|
+#define FLASHSIZE_BASE 0x1FF0F442UL /*!< FLASH Size register base address */
|
|
|
+#define PACKAGE_BASE 0x1FF0F7E0UL /*!< Package size register base address */
|
|
|
+/* Legacy define */
|
|
|
+#define PACKAGESIZE_BASE PACKAGE_BASE
|
|
|
+
|
|
|
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
|
|
|
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
|
|
|
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
|
|
|
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
|
|
|
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
|
|
|
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
|
|
|
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
|
|
|
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
|
|
|
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
|
|
|
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
|
|
|
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
|
|
|
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
|
|
|
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
|
|
|
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
|
|
|
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
|
|
|
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
|
|
|
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
|
|
|
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
|
|
|
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
|
|
|
+#define ETH_MAC_BASE (ETH_BASE)
|
|
|
+#define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
|
|
|
+#define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
|
|
|
+#define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
|
|
|
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)
|
|
|
+/*!< AHB2 peripherals */
|
|
|
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
|
|
|
+#define JPEG_BASE (AHB2PERIPH_BASE + 0x51000UL)
|
|
|
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
|
|
|
+/*!< FMC Bankx registers base address */
|
|
|
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
|
|
|
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
|
|
|
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
|
|
|
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
|
|
|
+
|
|
|
+/* Debug MCU registers base address */
|
|
|
+#define DBGMCU_BASE 0xE0042000UL
|
|
|
+
|
|
|
+/*!< USB registers base address */
|
|
|
+#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
|
|
|
+#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
|
|
|
+
|
|
|
+#define USB_OTG_GLOBAL_BASE 0x0000UL
|
|
|
+#define USB_OTG_DEVICE_BASE 0x0800UL
|
|
|
+#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL
|
|
|
+#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL
|
|
|
+#define USB_OTG_EP_REG_SIZE 0x0020UL
|
|
|
+#define USB_OTG_HOST_BASE 0x0400UL
|
|
|
+#define USB_OTG_HOST_PORT_BASE 0x0440UL
|
|
|
+#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL
|
|
|
+#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL
|
|
|
+#define USB_OTG_PCGCCTL_BASE 0x0E00UL
|
|
|
+#define USB_OTG_FIFO_BASE 0x1000UL
|
|
|
+#define USB_OTG_FIFO_SIZE 0x1000UL
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/** @addtogroup Peripheral_declaration
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
|
|
|
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
|
|
|
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
|
|
|
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
|
|
|
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
|
|
|
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
|
|
|
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
|
|
|
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
|
|
|
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
|
|
|
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
|
|
|
+#define RTC ((RTC_TypeDef *) RTC_BASE)
|
|
|
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
|
|
|
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
|
|
|
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
|
|
|
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
|
|
|
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
|
|
|
+#define USART2 ((USART_TypeDef *) USART2_BASE)
|
|
|
+#define USART3 ((USART_TypeDef *) USART3_BASE)
|
|
|
+#define UART4 ((USART_TypeDef *) UART4_BASE)
|
|
|
+#define UART5 ((USART_TypeDef *) UART5_BASE)
|
|
|
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
|
|
|
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
|
|
|
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
|
|
|
+#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
|
|
|
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
|
|
|
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
|
|
|
+#define CEC ((CEC_TypeDef *) CEC_BASE)
|
|
|
+#define PWR ((PWR_TypeDef *) PWR_BASE)
|
|
|
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
|
|
|
+#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
|
|
|
+#define UART7 ((USART_TypeDef *) UART7_BASE)
|
|
|
+#define UART8 ((USART_TypeDef *) UART8_BASE)
|
|
|
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
|
|
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
|
|
|
+#define USART1 ((USART_TypeDef *) USART1_BASE)
|
|
|
+#define USART6 ((USART_TypeDef *) USART6_BASE)
|
|
|
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
|
|
|
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
|
|
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
|
|
|
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
|
|
|
+#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
|
|
|
+#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
|
|
|
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
|
|
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
|
|
|
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
|
|
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
|
|
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
|
|
|
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
|
|
|
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
|
|
|
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
|
|
|
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
|
|
|
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
|
|
|
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
|
|
|
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
|
|
|
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
|
|
|
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
|
|
|
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
|
|
|
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
|
|
|
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
|
|
|
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
|
|
|
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
|
|
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
|
|
|
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
|
|
|
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
|
|
|
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
|
|
|
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
|
|
|
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
|
|
|
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
|
|
|
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
|
|
|
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
|
|
|
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
|
|
|
+#define CRC ((CRC_TypeDef *) CRC_BASE)
|
|
|
+#define RCC ((RCC_TypeDef *) RCC_BASE)
|
|
|
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
|
|
|
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
|
|
|
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
|
|
|
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
|
|
|
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
|
|
|
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
|
|
|
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
|
|
|
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
|
|
|
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
|
|
|
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
|
|
|
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
|
|
|
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
|
|
|
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
|
|
|
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
|
|
|
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
|
|
|
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
|
|
|
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
|
|
|
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
|
|
|
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
|
|
|
+#define ETH ((ETH_TypeDef *) ETH_BASE)
|
|
|
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
|
|
|
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
|
|
|
+#define RNG ((RNG_TypeDef *) RNG_BASE)
|
|
|
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
|
|
|
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
|
|
|
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
|
|
|
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
|
|
|
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
|
|
|
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
|
|
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
|
|
|
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
|
|
|
+#define CAN3 ((CAN_TypeDef *) CAN3_BASE)
|
|
|
+#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
|
|
|
+#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
|
|
|
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
|
|
|
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
|
|
|
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
|
|
|
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
|
|
|
+#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
|
|
|
+#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
|
|
|
+#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
|
|
|
+#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
|
|
|
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
|
|
|
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
|
|
|
+#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
|
|
|
+#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
|
|
|
+#define JPEG ((JPEG_TypeDef *) JPEG_BASE)
|
|
|
+#define DSI ((DSI_TypeDef *)DSI_BASE)
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/** @addtogroup Exported_constants
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+ /** @addtogroup Hardware_Constant_Definition
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */
|
|
|
+
|
|
|
+ /**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+ /** @addtogroup Peripheral_Registers_Bits_Definition
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* Peripheral Registers_Bits_Definition */
|
|
|
+/******************************************************************************/
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Analog to Digital Converter */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
|
|
|
+#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF0F44C)) /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
|
|
|
+#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF0F44E)) /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
|
|
|
+
|
|
|
+/******************** Bit definition for ADC_SR register ********************/
|
|
|
+#define ADC_SR_AWD_Pos (0U)
|
|
|
+#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
|
|
|
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
|
|
|
+#define ADC_SR_EOC_Pos (1U)
|
|
|
+#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000002 */
|
|
|
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
|
|
|
+#define ADC_SR_JEOC_Pos (2U)
|
|
|
+#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
|
|
|
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
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+#define ADC_SR_JSTRT_Pos (3U)
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+#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
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+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
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+#define ADC_SR_STRT_Pos (4U)
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+#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */
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+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
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+#define ADC_SR_OVR_Pos (5U)
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+#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */
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+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
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+
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+/******************* Bit definition for ADC_CR1 register ********************/
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+#define ADC_CR1_AWDCH_Pos (0U)
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+#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
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+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
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+#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
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+#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
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+#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
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+#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
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+#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
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+#define ADC_CR1_EOCIE_Pos (5U)
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+#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
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+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
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+#define ADC_CR1_AWDIE_Pos (6U)
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+#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
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+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
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+#define ADC_CR1_JEOCIE_Pos (7U)
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+#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
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+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
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+#define ADC_CR1_SCAN_Pos (8U)
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+#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
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+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
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+#define ADC_CR1_AWDSGL_Pos (9U)
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+#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
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+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
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+#define ADC_CR1_JAUTO_Pos (10U)
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+#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
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+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
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+#define ADC_CR1_DISCEN_Pos (11U)
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+#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
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+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
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+#define ADC_CR1_JDISCEN_Pos (12U)
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+#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
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+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
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+#define ADC_CR1_DISCNUM_Pos (13U)
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+#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
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+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
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+#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
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+#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
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+#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
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+#define ADC_CR1_JAWDEN_Pos (22U)
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+#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
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+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
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+#define ADC_CR1_AWDEN_Pos (23U)
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+#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
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+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
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+#define ADC_CR1_RES_Pos (24U)
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+#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */
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+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
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+#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */
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+#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */
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+#define ADC_CR1_OVRIE_Pos (26U)
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+#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
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+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
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+
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+/******************* Bit definition for ADC_CR2 register ********************/
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+#define ADC_CR2_ADON_Pos (0U)
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+#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
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+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
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+#define ADC_CR2_CONT_Pos (1U)
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+#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
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+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
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+#define ADC_CR2_DMA_Pos (8U)
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+#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
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+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
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+#define ADC_CR2_DDS_Pos (9U)
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+#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
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+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
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+#define ADC_CR2_EOCS_Pos (10U)
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+#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
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+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
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+#define ADC_CR2_ALIGN_Pos (11U)
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+#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
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+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
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+#define ADC_CR2_JEXTSEL_Pos (16U)
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+#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
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+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
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+#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
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+#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
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+#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
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+#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
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+#define ADC_CR2_JEXTEN_Pos (20U)
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+#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
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+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
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+#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
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+#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
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+#define ADC_CR2_JSWSTART_Pos (22U)
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+#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
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+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
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+#define ADC_CR2_EXTSEL_Pos (24U)
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+#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
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+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
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+#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
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+#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
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+#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
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+#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
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+#define ADC_CR2_EXTEN_Pos (28U)
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+#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
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+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
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+#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
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+#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
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+#define ADC_CR2_SWSTART_Pos (30U)
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+#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
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+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
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+
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+/****************** Bit definition for ADC_SMPR1 register *******************/
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+#define ADC_SMPR1_SMP10_Pos (0U)
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+#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
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+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
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+#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
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+#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
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+#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
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+#define ADC_SMPR1_SMP11_Pos (3U)
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+#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
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+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
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+#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
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+#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
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+#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
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+#define ADC_SMPR1_SMP12_Pos (6U)
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+#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
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+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
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+#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
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+#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
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+#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
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+#define ADC_SMPR1_SMP13_Pos (9U)
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+#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
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+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
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+#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
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+#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
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+#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
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+#define ADC_SMPR1_SMP14_Pos (12U)
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+#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
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+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
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+#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
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+#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
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+#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
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+#define ADC_SMPR1_SMP15_Pos (15U)
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+#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
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+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
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+#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
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+#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
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+#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
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+#define ADC_SMPR1_SMP16_Pos (18U)
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+#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
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+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
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+#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
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+#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
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+#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
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+#define ADC_SMPR1_SMP17_Pos (21U)
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+#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
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+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
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+#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
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+#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
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+#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
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+#define ADC_SMPR1_SMP18_Pos (24U)
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+#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
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+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
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+#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
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+#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
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+#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
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+
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+/****************** Bit definition for ADC_SMPR2 register *******************/
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+#define ADC_SMPR2_SMP0_Pos (0U)
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+#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
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+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
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+#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
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+#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
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+#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
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+#define ADC_SMPR2_SMP1_Pos (3U)
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+#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
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+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
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+#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
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+#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
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+#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
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+#define ADC_SMPR2_SMP2_Pos (6U)
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+#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
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+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
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+#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
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+#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
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+#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
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+#define ADC_SMPR2_SMP3_Pos (9U)
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+#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
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+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
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+#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
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+#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
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+#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
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+#define ADC_SMPR2_SMP4_Pos (12U)
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+#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
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+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
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+#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
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+#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
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+#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
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+#define ADC_SMPR2_SMP5_Pos (15U)
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+#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
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+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
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+#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
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+#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
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+#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
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+#define ADC_SMPR2_SMP6_Pos (18U)
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+#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
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+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
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+#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
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+#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
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+#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
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+#define ADC_SMPR2_SMP7_Pos (21U)
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+#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
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+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
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+#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
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+#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
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+#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
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+#define ADC_SMPR2_SMP8_Pos (24U)
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+#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
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+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
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+#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
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+#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
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+#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
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+#define ADC_SMPR2_SMP9_Pos (27U)
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+#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
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+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
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+#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
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+#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
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+#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
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+
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+/****************** Bit definition for ADC_JOFR1 register *******************/
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+#define ADC_JOFR1_JOFFSET1_Pos (0U)
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+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
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+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
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+
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+/****************** Bit definition for ADC_JOFR2 register *******************/
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+#define ADC_JOFR2_JOFFSET2_Pos (0U)
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+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
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+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
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+
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+/****************** Bit definition for ADC_JOFR3 register *******************/
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+#define ADC_JOFR3_JOFFSET3_Pos (0U)
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+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
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+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
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+
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+/****************** Bit definition for ADC_JOFR4 register *******************/
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+#define ADC_JOFR4_JOFFSET4_Pos (0U)
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+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
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+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
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+
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+/******************* Bit definition for ADC_HTR register ********************/
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+#define ADC_HTR_HT_Pos (0U)
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+#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
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+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
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+
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+/******************* Bit definition for ADC_LTR register ********************/
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+#define ADC_LTR_LT_Pos (0U)
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+#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
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+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
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+
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+/******************* Bit definition for ADC_SQR1 register *******************/
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+#define ADC_SQR1_SQ13_Pos (0U)
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+#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
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+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
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+#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
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+#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
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+#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
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+#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
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+#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
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+#define ADC_SQR1_SQ14_Pos (5U)
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+#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
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+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
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+#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
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+#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
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+#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
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+#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
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+#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
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+#define ADC_SQR1_SQ15_Pos (10U)
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+#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
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+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
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+#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
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+#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
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+#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
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+#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
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+#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
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+#define ADC_SQR1_SQ16_Pos (15U)
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+#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
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+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
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+#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
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+#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
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+#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
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+#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
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+#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
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+#define ADC_SQR1_L_Pos (20U)
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+#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
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+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
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+#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */
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+#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */
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+#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */
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+#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */
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+
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+/******************* Bit definition for ADC_SQR2 register *******************/
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+#define ADC_SQR2_SQ7_Pos (0U)
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+#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
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+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
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+#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
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+#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
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+#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
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+#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
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+#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
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+#define ADC_SQR2_SQ8_Pos (5U)
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+#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
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+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
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+#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
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+#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
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+#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
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+#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
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+#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
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+#define ADC_SQR2_SQ9_Pos (10U)
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+#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
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+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
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+#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
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+#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
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+#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
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+#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
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+#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
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+#define ADC_SQR2_SQ10_Pos (15U)
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+#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
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+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
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+#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
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+#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
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+#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
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+#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
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+#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
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+#define ADC_SQR2_SQ11_Pos (20U)
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+#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
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+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
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+#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
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+#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
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+#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
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+#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
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+#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
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+#define ADC_SQR2_SQ12_Pos (25U)
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+#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
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+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
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+#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
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+#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
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+#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
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+#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
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+#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
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+
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+/******************* Bit definition for ADC_SQR3 register *******************/
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+#define ADC_SQR3_SQ1_Pos (0U)
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+#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
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+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
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+#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
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+#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
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+#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
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+#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
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+#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
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+#define ADC_SQR3_SQ2_Pos (5U)
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+#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
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+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
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+#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
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+#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
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+#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
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+#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
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+#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
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+#define ADC_SQR3_SQ3_Pos (10U)
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+#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
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+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
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+#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
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+#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
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+#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
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+#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
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+#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
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+#define ADC_SQR3_SQ4_Pos (15U)
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+#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
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+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
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+#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
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+#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
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+#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
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+#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
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+#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
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+#define ADC_SQR3_SQ5_Pos (20U)
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+#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
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+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
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+#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
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+#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
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+#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
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+#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
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+#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
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+#define ADC_SQR3_SQ6_Pos (25U)
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+#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
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+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
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+#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
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+#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
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+#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
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+#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
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+#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
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+
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+/******************* Bit definition for ADC_JSQR register *******************/
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+#define ADC_JSQR_JSQ1_Pos (0U)
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+#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
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+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
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+#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
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+#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
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+#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
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+#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
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+#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
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+#define ADC_JSQR_JSQ2_Pos (5U)
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+#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
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+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
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+#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
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+#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
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+#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
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+#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
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+#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
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+#define ADC_JSQR_JSQ3_Pos (10U)
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+#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
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+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
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+#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
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+#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
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+#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
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+#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
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+#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
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+#define ADC_JSQR_JSQ4_Pos (15U)
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+#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
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+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
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+#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
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+#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
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+#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
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+#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
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+#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
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+#define ADC_JSQR_JL_Pos (20U)
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+#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
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+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
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+#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
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+#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
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+
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+/******************* Bit definition for ADC_JDR1 register *******************/
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+#define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
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+
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+/******************* Bit definition for ADC_JDR2 register *******************/
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+#define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
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+
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+/******************* Bit definition for ADC_JDR3 register *******************/
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+#define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
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+
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+/******************* Bit definition for ADC_JDR4 register *******************/
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+#define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
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+
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+/******************** Bit definition for ADC_DR register ********************/
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+#define ADC_DR_DATA_Pos (0U)
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+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
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+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
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+#define ADC_DR_ADC2DATA_Pos (16U)
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+#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
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+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
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+
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+/******************* Bit definition for ADC_CSR register ********************/
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+#define ADC_CSR_AWD1_Pos (0U)
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+#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
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+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
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+#define ADC_CSR_EOC1_Pos (1U)
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+#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
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+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
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+#define ADC_CSR_JEOC1_Pos (2U)
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+#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
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+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
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+#define ADC_CSR_JSTRT1_Pos (3U)
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+#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
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+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
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+#define ADC_CSR_STRT1_Pos (4U)
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+#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
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+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
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+#define ADC_CSR_OVR1_Pos (5U)
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+#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
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+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 Overrun flag */
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+#define ADC_CSR_AWD2_Pos (8U)
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+#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
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+#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
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+#define ADC_CSR_EOC2_Pos (9U)
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+#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
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+#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
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+#define ADC_CSR_JEOC2_Pos (10U)
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+#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
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+#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
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+#define ADC_CSR_JSTRT2_Pos (11U)
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+#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
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+#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
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+#define ADC_CSR_STRT2_Pos (12U)
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+#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
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+#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
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+#define ADC_CSR_OVR2_Pos (13U)
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+#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
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+#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 Overrun flag */
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+#define ADC_CSR_AWD3_Pos (16U)
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+#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
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+#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
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+#define ADC_CSR_EOC3_Pos (17U)
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+#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
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+#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
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+#define ADC_CSR_JEOC3_Pos (18U)
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+#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
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+#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
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+#define ADC_CSR_JSTRT3_Pos (19U)
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+#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
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+#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
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+#define ADC_CSR_STRT3_Pos (20U)
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+#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
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+#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
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+#define ADC_CSR_OVR3_Pos (21U)
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+#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
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+#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 Overrun flag */
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+
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+/* Legacy defines */
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+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
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+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
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+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
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+
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+
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+/******************* Bit definition for ADC_CCR register ********************/
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+#define ADC_CCR_MULTI_Pos (0U)
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+#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
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+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
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+#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
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+#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
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+#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
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+#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
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+#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
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+#define ADC_CCR_DELAY_Pos (8U)
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+#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
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+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
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+#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
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+#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
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+#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
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+#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
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+#define ADC_CCR_DDS_Pos (13U)
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+#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
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+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
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+#define ADC_CCR_DMA_Pos (14U)
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+#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
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+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
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+#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
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+#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
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+#define ADC_CCR_ADCPRE_Pos (16U)
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+#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
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+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
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+#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
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+#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
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+#define ADC_CCR_VBATE_Pos (22U)
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+#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
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+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
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+#define ADC_CCR_TSVREFE_Pos (23U)
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+#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
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+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
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+
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+/******************* Bit definition for ADC_CDR register ********************/
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+#define ADC_CDR_DATA1_Pos (0U)
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+#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
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+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
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+#define ADC_CDR_DATA2_Pos (16U)
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+#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
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+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
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+
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|
+/* Legacy defines */
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|
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
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+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
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+
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+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Controller Area Network */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/*!<CAN control and status registers */
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|
|
+/******************* Bit definition for CAN_MCR register ********************/
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+#define CAN_MCR_INRQ_Pos (0U)
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+#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
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+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
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+#define CAN_MCR_SLEEP_Pos (1U)
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+#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
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+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
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+#define CAN_MCR_TXFP_Pos (2U)
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+#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
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+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
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+#define CAN_MCR_RFLM_Pos (3U)
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+#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
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+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
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|
+#define CAN_MCR_NART_Pos (4U)
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+#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */
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+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
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|
+#define CAN_MCR_AWUM_Pos (5U)
|
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|
+#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
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+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
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|
+#define CAN_MCR_ABOM_Pos (6U)
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|
+#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
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|
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
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|
+#define CAN_MCR_TTCM_Pos (7U)
|
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|
+#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
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|
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
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|
+#define CAN_MCR_RESET_Pos (15U)
|
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+#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
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+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
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+
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+/******************* Bit definition for CAN_MSR register ********************/
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+#define CAN_MSR_INAK_Pos (0U)
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+#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
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+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
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+#define CAN_MSR_SLAK_Pos (1U)
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+#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
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+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
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+#define CAN_MSR_ERRI_Pos (2U)
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+#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
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+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
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+#define CAN_MSR_WKUI_Pos (3U)
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+#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
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+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
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+#define CAN_MSR_SLAKI_Pos (4U)
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+#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
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+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
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+#define CAN_MSR_TXM_Pos (8U)
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+#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
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+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
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+#define CAN_MSR_RXM_Pos (9U)
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+#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
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+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
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+#define CAN_MSR_SAMP_Pos (10U)
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+#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
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+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
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+#define CAN_MSR_RX_Pos (11U)
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+#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */
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+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
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+
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+/******************* Bit definition for CAN_TSR register ********************/
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+#define CAN_TSR_RQCP0_Pos (0U)
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+#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
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+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
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+#define CAN_TSR_TXOK0_Pos (1U)
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+#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
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+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
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+#define CAN_TSR_ALST0_Pos (2U)
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+#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
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+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
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+#define CAN_TSR_TERR0_Pos (3U)
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+#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
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+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
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+#define CAN_TSR_ABRQ0_Pos (7U)
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+#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
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+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
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+#define CAN_TSR_RQCP1_Pos (8U)
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+#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
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+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
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+#define CAN_TSR_TXOK1_Pos (9U)
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+#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
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+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
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+#define CAN_TSR_ALST1_Pos (10U)
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+#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
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+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
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+#define CAN_TSR_TERR1_Pos (11U)
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+#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
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+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
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+#define CAN_TSR_ABRQ1_Pos (15U)
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+#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
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+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
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+#define CAN_TSR_RQCP2_Pos (16U)
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+#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
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+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
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+#define CAN_TSR_TXOK2_Pos (17U)
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+#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
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+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
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+#define CAN_TSR_ALST2_Pos (18U)
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+#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
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+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
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+#define CAN_TSR_TERR2_Pos (19U)
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+#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
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+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
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+#define CAN_TSR_ABRQ2_Pos (23U)
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|
+#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
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|
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
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|
+#define CAN_TSR_CODE_Pos (24U)
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|
+#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
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+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
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+
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|
|
+#define CAN_TSR_TME_Pos (26U)
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|
+#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
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+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
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+#define CAN_TSR_TME0_Pos (26U)
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|
+#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
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+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
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+#define CAN_TSR_TME1_Pos (27U)
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+#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
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+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
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+#define CAN_TSR_TME2_Pos (28U)
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+#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
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+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
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+
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|
|
+#define CAN_TSR_LOW_Pos (29U)
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|
+#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
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+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
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+#define CAN_TSR_LOW0_Pos (29U)
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+#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
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+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
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+#define CAN_TSR_LOW1_Pos (30U)
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+#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
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+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
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+#define CAN_TSR_LOW2_Pos (31U)
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+#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
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+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
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+
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+/******************* Bit definition for CAN_RF0R register *******************/
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+#define CAN_RF0R_FMP0_Pos (0U)
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+#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
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+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
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+#define CAN_RF0R_FULL0_Pos (3U)
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+#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
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+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
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+#define CAN_RF0R_FOVR0_Pos (4U)
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+#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
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+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
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+#define CAN_RF0R_RFOM0_Pos (5U)
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+#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
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+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
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+
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+/******************* Bit definition for CAN_RF1R register *******************/
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+#define CAN_RF1R_FMP1_Pos (0U)
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+#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
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+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
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+#define CAN_RF1R_FULL1_Pos (3U)
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+#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
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+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
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+#define CAN_RF1R_FOVR1_Pos (4U)
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+#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
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+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
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+#define CAN_RF1R_RFOM1_Pos (5U)
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+#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
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+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
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+
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|
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+/******************** Bit definition for CAN_IER register *******************/
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+#define CAN_IER_TMEIE_Pos (0U)
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+#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
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+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
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+#define CAN_IER_FMPIE0_Pos (1U)
|
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+#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
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+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
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+#define CAN_IER_FFIE0_Pos (2U)
|
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|
+#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
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+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
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|
+#define CAN_IER_FOVIE0_Pos (3U)
|
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|
+#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
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+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
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+#define CAN_IER_FMPIE1_Pos (4U)
|
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+#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
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+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
|
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+#define CAN_IER_FFIE1_Pos (5U)
|
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|
+#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
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+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
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+#define CAN_IER_FOVIE1_Pos (6U)
|
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|
+#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
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+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
|
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|
+#define CAN_IER_EWGIE_Pos (8U)
|
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|
+#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
|
|
|
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
|
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|
+#define CAN_IER_EPVIE_Pos (9U)
|
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|
+#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
|
|
|
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
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|
+#define CAN_IER_BOFIE_Pos (10U)
|
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+#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
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|
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
|
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|
+#define CAN_IER_LECIE_Pos (11U)
|
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|
+#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
|
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|
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
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|
+#define CAN_IER_ERRIE_Pos (15U)
|
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+#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
|
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+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
|
|
|
+#define CAN_IER_WKUIE_Pos (16U)
|
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|
+#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
|
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|
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
|
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|
+#define CAN_IER_SLKIE_Pos (17U)
|
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+#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
|
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|
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
|
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+
|
|
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+/******************** Bit definition for CAN_ESR register *******************/
|
|
|
+#define CAN_ESR_EWGF_Pos (0U)
|
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|
+#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
|
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+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
|
|
|
+#define CAN_ESR_EPVF_Pos (1U)
|
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|
+#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
|
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+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
|
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|
+#define CAN_ESR_BOFF_Pos (2U)
|
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|
+#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
|
|
|
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
|
|
|
+
|
|
|
+#define CAN_ESR_LEC_Pos (4U)
|
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|
+#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
|
|
|
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
|
|
|
+#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
|
|
|
+#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
|
|
|
+#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
|
|
|
+
|
|
|
+#define CAN_ESR_TEC_Pos (16U)
|
|
|
+#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
|
|
|
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
|
|
|
+#define CAN_ESR_REC_Pos (24U)
|
|
|
+#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
|
|
|
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
|
|
|
+
|
|
|
+/******************* Bit definition for CAN_BTR register ********************/
|
|
|
+#define CAN_BTR_BRP_Pos (0U)
|
|
|
+#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
|
|
|
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
|
|
|
+#define CAN_BTR_TS1_Pos (16U)
|
|
|
+#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
|
|
|
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
|
|
|
+#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
|
|
|
+#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
|
|
|
+#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
|
|
|
+#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
|
|
|
+#define CAN_BTR_TS2_Pos (20U)
|
|
|
+#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
|
|
|
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
|
|
|
+#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
|
|
|
+#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
|
|
|
+#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
|
|
|
+#define CAN_BTR_SJW_Pos (24U)
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|
|
+#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
|
|
|
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
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+#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
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+#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
|
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|
+#define CAN_BTR_LBKM_Pos (30U)
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|
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+#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
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|
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+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
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|
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+#define CAN_BTR_SILM_Pos (31U)
|
|
|
+#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
|
|
|
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
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+
|
|
|
+/*!<Mailbox registers */
|
|
|
+/****************** Bit definition for CAN_TI0R register ********************/
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|
|
+#define CAN_TI0R_TXRQ_Pos (0U)
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+#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
|
|
|
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
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|
|
+#define CAN_TI0R_RTR_Pos (1U)
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|
+#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
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|
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+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
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|
|
+#define CAN_TI0R_IDE_Pos (2U)
|
|
|
+#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
|
|
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+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
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|
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+#define CAN_TI0R_EXID_Pos (3U)
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+#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
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|
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+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
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|
|
+#define CAN_TI0R_STID_Pos (21U)
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|
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+#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
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|
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+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
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+
|
|
|
+/****************** Bit definition for CAN_TDT0R register *******************/
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|
|
+#define CAN_TDT0R_DLC_Pos (0U)
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|
+#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
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+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
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|
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+#define CAN_TDT0R_TGT_Pos (8U)
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|
+#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
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|
|
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
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+#define CAN_TDT0R_TIME_Pos (16U)
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+#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
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+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
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+
|
|
|
+/****************** Bit definition for CAN_TDL0R register *******************/
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+#define CAN_TDL0R_DATA0_Pos (0U)
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|
+#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
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+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
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+#define CAN_TDL0R_DATA1_Pos (8U)
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+#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
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+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
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+#define CAN_TDL0R_DATA2_Pos (16U)
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|
+#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
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|
|
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
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+#define CAN_TDL0R_DATA3_Pos (24U)
|
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|
+#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
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|
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
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+
|
|
|
+/****************** Bit definition for CAN_TDH0R register *******************/
|
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|
+#define CAN_TDH0R_DATA4_Pos (0U)
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|
+#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
|
|
|
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
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|
+#define CAN_TDH0R_DATA5_Pos (8U)
|
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|
+#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
|
|
|
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
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|
|
+#define CAN_TDH0R_DATA6_Pos (16U)
|
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|
+#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
|
|
|
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
|
|
|
+#define CAN_TDH0R_DATA7_Pos (24U)
|
|
|
+#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
|
|
|
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
|
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|
+
|
|
|
+/******************* Bit definition for CAN_TI1R register *******************/
|
|
|
+#define CAN_TI1R_TXRQ_Pos (0U)
|
|
|
+#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
|
|
|
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
|
|
|
+#define CAN_TI1R_RTR_Pos (1U)
|
|
|
+#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
|
|
|
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
|
|
|
+#define CAN_TI1R_IDE_Pos (2U)
|
|
|
+#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
|
|
|
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
|
|
|
+#define CAN_TI1R_EXID_Pos (3U)
|
|
|
+#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
|
|
|
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
|
|
|
+#define CAN_TI1R_STID_Pos (21U)
|
|
|
+#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
|
|
|
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
|
|
|
+
|
|
|
+/******************* Bit definition for CAN_TDT1R register ******************/
|
|
|
+#define CAN_TDT1R_DLC_Pos (0U)
|
|
|
+#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
|
|
|
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
|
|
|
+#define CAN_TDT1R_TGT_Pos (8U)
|
|
|
+#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
|
|
|
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
|
|
|
+#define CAN_TDT1R_TIME_Pos (16U)
|
|
|
+#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
|
|
|
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
|
|
|
+
|
|
|
+/******************* Bit definition for CAN_TDL1R register ******************/
|
|
|
+#define CAN_TDL1R_DATA0_Pos (0U)
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|
|
+#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
|
|
|
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
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|
|
+#define CAN_TDL1R_DATA1_Pos (8U)
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|
|
+#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
|
|
|
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
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|
+#define CAN_TDL1R_DATA2_Pos (16U)
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|
|
+#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
|
|
|
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
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|
|
+#define CAN_TDL1R_DATA3_Pos (24U)
|
|
|
+#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
|
|
|
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
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|
|
+
|
|
|
+/******************* Bit definition for CAN_TDH1R register ******************/
|
|
|
+#define CAN_TDH1R_DATA4_Pos (0U)
|
|
|
+#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
|
|
|
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
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|
|
+#define CAN_TDH1R_DATA5_Pos (8U)
|
|
|
+#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
|
|
|
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
|
|
|
+#define CAN_TDH1R_DATA6_Pos (16U)
|
|
|
+#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
|
|
|
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
|
|
|
+#define CAN_TDH1R_DATA7_Pos (24U)
|
|
|
+#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
|
|
|
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
|
|
|
+
|
|
|
+/******************* Bit definition for CAN_TI2R register *******************/
|
|
|
+#define CAN_TI2R_TXRQ_Pos (0U)
|
|
|
+#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
|
|
|
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
|
|
|
+#define CAN_TI2R_RTR_Pos (1U)
|
|
|
+#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
|
|
|
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
|
|
|
+#define CAN_TI2R_IDE_Pos (2U)
|
|
|
+#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
|
|
|
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
|
|
|
+#define CAN_TI2R_EXID_Pos (3U)
|
|
|
+#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
|
|
|
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
|
|
|
+#define CAN_TI2R_STID_Pos (21U)
|
|
|
+#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
|
|
|
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
|
|
|
+
|
|
|
+/******************* Bit definition for CAN_TDT2R register ******************/
|
|
|
+#define CAN_TDT2R_DLC_Pos (0U)
|
|
|
+#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
|
|
|
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
|
|
|
+#define CAN_TDT2R_TGT_Pos (8U)
|
|
|
+#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
|
|
|
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
|
|
|
+#define CAN_TDT2R_TIME_Pos (16U)
|
|
|
+#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
|
|
|
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
|
|
|
+
|
|
|
+/******************* Bit definition for CAN_TDL2R register ******************/
|
|
|
+#define CAN_TDL2R_DATA0_Pos (0U)
|
|
|
+#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
|
|
|
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
|
|
|
+#define CAN_TDL2R_DATA1_Pos (8U)
|
|
|
+#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
|
|
|
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
|
|
|
+#define CAN_TDL2R_DATA2_Pos (16U)
|
|
|
+#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
|
|
|
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
|
|
|
+#define CAN_TDL2R_DATA3_Pos (24U)
|
|
|
+#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
|
|
|
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
|
|
|
+
|
|
|
+/******************* Bit definition for CAN_TDH2R register ******************/
|
|
|
+#define CAN_TDH2R_DATA4_Pos (0U)
|
|
|
+#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
|
|
|
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
|
|
|
+#define CAN_TDH2R_DATA5_Pos (8U)
|
|
|
+#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
|
|
|
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
|
|
|
+#define CAN_TDH2R_DATA6_Pos (16U)
|
|
|
+#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
|
|
|
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
|
|
|
+#define CAN_TDH2R_DATA7_Pos (24U)
|
|
|
+#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
|
|
|
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
|
|
|
+
|
|
|
+/******************* Bit definition for CAN_RI0R register *******************/
|
|
|
+#define CAN_RI0R_RTR_Pos (1U)
|
|
|
+#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
|
|
|
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
|
|
|
+#define CAN_RI0R_IDE_Pos (2U)
|
|
|
+#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
|
|
|
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
|
|
|
+#define CAN_RI0R_EXID_Pos (3U)
|
|
|
+#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
|
|
|
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
|
|
|
+#define CAN_RI0R_STID_Pos (21U)
|
|
|
+#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
|
|
|
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
|
|
|
+
|
|
|
+/******************* Bit definition for CAN_RDT0R register ******************/
|
|
|
+#define CAN_RDT0R_DLC_Pos (0U)
|
|
|
+#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
|
|
|
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
|
|
|
+#define CAN_RDT0R_FMI_Pos (8U)
|
|
|
+#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
|
|
|
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
|
|
|
+#define CAN_RDT0R_TIME_Pos (16U)
|
|
|
+#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
|
|
|
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
|
|
|
+
|
|
|
+/******************* Bit definition for CAN_RDL0R register ******************/
|
|
|
+#define CAN_RDL0R_DATA0_Pos (0U)
|
|
|
+#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
|
|
|
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
|
|
|
+#define CAN_RDL0R_DATA1_Pos (8U)
|
|
|
+#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
|
|
|
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
|
|
|
+#define CAN_RDL0R_DATA2_Pos (16U)
|
|
|
+#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
|
|
|
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
|
|
|
+#define CAN_RDL0R_DATA3_Pos (24U)
|
|
|
+#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
|
|
|
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
|
|
|
+
|
|
|
+/******************* Bit definition for CAN_RDH0R register ******************/
|
|
|
+#define CAN_RDH0R_DATA4_Pos (0U)
|
|
|
+#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
|
|
|
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
|
|
|
+#define CAN_RDH0R_DATA5_Pos (8U)
|
|
|
+#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
|
|
|
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
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+#define CAN_RDH0R_DATA6_Pos (16U)
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+#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
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+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
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+#define CAN_RDH0R_DATA7_Pos (24U)
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+#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
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+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
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+
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+/******************* Bit definition for CAN_RI1R register *******************/
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+#define CAN_RI1R_RTR_Pos (1U)
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+#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
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+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
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+#define CAN_RI1R_IDE_Pos (2U)
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+#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
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+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
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+#define CAN_RI1R_EXID_Pos (3U)
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+#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
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+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
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+#define CAN_RI1R_STID_Pos (21U)
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+#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
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+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
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+
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+/******************* Bit definition for CAN_RDT1R register ******************/
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+#define CAN_RDT1R_DLC_Pos (0U)
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+#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
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+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
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+#define CAN_RDT1R_FMI_Pos (8U)
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+#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
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+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
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+#define CAN_RDT1R_TIME_Pos (16U)
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+#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
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+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
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+
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+/******************* Bit definition for CAN_RDL1R register ******************/
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+#define CAN_RDL1R_DATA0_Pos (0U)
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+#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
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+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
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+#define CAN_RDL1R_DATA1_Pos (8U)
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+#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
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+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
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+#define CAN_RDL1R_DATA2_Pos (16U)
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+#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
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+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
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+#define CAN_RDL1R_DATA3_Pos (24U)
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+#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
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+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
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+
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+/******************* Bit definition for CAN_RDH1R register ******************/
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+#define CAN_RDH1R_DATA4_Pos (0U)
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+#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
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+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
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+#define CAN_RDH1R_DATA5_Pos (8U)
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+#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
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+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
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+#define CAN_RDH1R_DATA6_Pos (16U)
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+#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
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+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
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+#define CAN_RDH1R_DATA7_Pos (24U)
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+#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
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+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
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+
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+/*!<CAN filter registers */
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+/******************* Bit definition for CAN_FMR register ********************/
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+#define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
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+#define CAN_FMR_CAN2SB_Pos (8U)
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+#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
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+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
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+
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+/******************* Bit definition for CAN_FM1R register *******************/
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+#define CAN_FM1R_FBM_Pos (0U)
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+#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
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+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
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+#define CAN_FM1R_FBM0_Pos (0U)
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+#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
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+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
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+#define CAN_FM1R_FBM1_Pos (1U)
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+#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
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+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
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+#define CAN_FM1R_FBM2_Pos (2U)
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+#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
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+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
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+#define CAN_FM1R_FBM3_Pos (3U)
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+#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
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+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
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+#define CAN_FM1R_FBM4_Pos (4U)
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+#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
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+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
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+#define CAN_FM1R_FBM5_Pos (5U)
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+#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
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+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
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+#define CAN_FM1R_FBM6_Pos (6U)
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+#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
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+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
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+#define CAN_FM1R_FBM7_Pos (7U)
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+#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
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+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
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+#define CAN_FM1R_FBM8_Pos (8U)
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+#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
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+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
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+#define CAN_FM1R_FBM9_Pos (9U)
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+#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
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+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
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+#define CAN_FM1R_FBM10_Pos (10U)
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+#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
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+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
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+#define CAN_FM1R_FBM11_Pos (11U)
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+#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
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+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
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+#define CAN_FM1R_FBM12_Pos (12U)
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+#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
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+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
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+#define CAN_FM1R_FBM13_Pos (13U)
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+#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
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+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
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+
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+/******************* Bit definition for CAN_FS1R register *******************/
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+#define CAN_FS1R_FSC_Pos (0U)
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+#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
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+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
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+#define CAN_FS1R_FSC0_Pos (0U)
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+#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
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+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
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+#define CAN_FS1R_FSC1_Pos (1U)
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+#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
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+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
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+#define CAN_FS1R_FSC2_Pos (2U)
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+#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
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+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
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+#define CAN_FS1R_FSC3_Pos (3U)
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+#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
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+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
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+#define CAN_FS1R_FSC4_Pos (4U)
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+#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
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+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
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+#define CAN_FS1R_FSC5_Pos (5U)
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+#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
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+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
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+#define CAN_FS1R_FSC6_Pos (6U)
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+#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
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+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
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+#define CAN_FS1R_FSC7_Pos (7U)
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+#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
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+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
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+#define CAN_FS1R_FSC8_Pos (8U)
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+#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
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+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
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+#define CAN_FS1R_FSC9_Pos (9U)
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+#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
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+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
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+#define CAN_FS1R_FSC10_Pos (10U)
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+#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
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+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
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+#define CAN_FS1R_FSC11_Pos (11U)
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+#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
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+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
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+#define CAN_FS1R_FSC12_Pos (12U)
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+#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
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+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
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+#define CAN_FS1R_FSC13_Pos (13U)
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+#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
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+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
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+
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|
|
+/****************** Bit definition for CAN_FFA1R register *******************/
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|
+#define CAN_FFA1R_FFA_Pos (0U)
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+#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
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+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
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+#define CAN_FFA1R_FFA0_Pos (0U)
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+#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
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+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
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+#define CAN_FFA1R_FFA1_Pos (1U)
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+#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
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|
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
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+#define CAN_FFA1R_FFA2_Pos (2U)
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+#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
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|
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
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+#define CAN_FFA1R_FFA3_Pos (3U)
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+#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
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+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
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+#define CAN_FFA1R_FFA4_Pos (4U)
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+#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
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|
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
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|
+#define CAN_FFA1R_FFA5_Pos (5U)
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|
+#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
|
|
|
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
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|
+#define CAN_FFA1R_FFA6_Pos (6U)
|
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+#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
|
|
|
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
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|
|
+#define CAN_FFA1R_FFA7_Pos (7U)
|
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|
+#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
|
|
|
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
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|
|
+#define CAN_FFA1R_FFA8_Pos (8U)
|
|
|
+#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
|
|
|
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
|
|
|
+#define CAN_FFA1R_FFA9_Pos (9U)
|
|
|
+#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
|
|
|
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
|
|
|
+#define CAN_FFA1R_FFA10_Pos (10U)
|
|
|
+#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
|
|
|
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
|
|
|
+#define CAN_FFA1R_FFA11_Pos (11U)
|
|
|
+#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
|
|
|
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
|
|
|
+#define CAN_FFA1R_FFA12_Pos (12U)
|
|
|
+#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
|
|
|
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
|
|
|
+#define CAN_FFA1R_FFA13_Pos (13U)
|
|
|
+#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
|
|
|
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
|
|
|
+
|
|
|
+/******************* Bit definition for CAN_FA1R register *******************/
|
|
|
+#define CAN_FA1R_FACT_Pos (0U)
|
|
|
+#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
|
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+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
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+#define CAN_FA1R_FACT0_Pos (0U)
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+#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
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+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
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+#define CAN_FA1R_FACT1_Pos (1U)
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+#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
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+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
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+#define CAN_FA1R_FACT2_Pos (2U)
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+#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
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+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
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+#define CAN_FA1R_FACT3_Pos (3U)
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+#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
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+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
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+#define CAN_FA1R_FACT4_Pos (4U)
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+#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
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+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
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+#define CAN_FA1R_FACT5_Pos (5U)
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+#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
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+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
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+#define CAN_FA1R_FACT6_Pos (6U)
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+#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
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+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
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+#define CAN_FA1R_FACT7_Pos (7U)
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+#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
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+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
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+#define CAN_FA1R_FACT8_Pos (8U)
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+#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
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+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
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+#define CAN_FA1R_FACT9_Pos (9U)
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+#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
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+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
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+#define CAN_FA1R_FACT10_Pos (10U)
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+#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
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+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
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+#define CAN_FA1R_FACT11_Pos (11U)
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+#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
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+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
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+#define CAN_FA1R_FACT12_Pos (12U)
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+#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
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+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
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+#define CAN_FA1R_FACT13_Pos (13U)
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+#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
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+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
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+
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+/******************* Bit definition for CAN_F0R1 register *******************/
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+#define CAN_F0R1_FB0_Pos (0U)
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+#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F0R1_FB1_Pos (1U)
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+#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F0R1_FB2_Pos (2U)
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+#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F0R1_FB3_Pos (3U)
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+#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F0R1_FB4_Pos (4U)
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+#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F0R1_FB5_Pos (5U)
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+#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F0R1_FB6_Pos (6U)
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+#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F0R1_FB7_Pos (7U)
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+#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F0R1_FB8_Pos (8U)
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+#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F0R1_FB9_Pos (9U)
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+#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F0R1_FB10_Pos (10U)
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+#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F0R1_FB11_Pos (11U)
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+#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F0R1_FB12_Pos (12U)
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+#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F0R1_FB13_Pos (13U)
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+#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F0R1_FB14_Pos (14U)
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+#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F0R1_FB15_Pos (15U)
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+#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F0R1_FB16_Pos (16U)
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+#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F0R1_FB17_Pos (17U)
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+#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F0R1_FB18_Pos (18U)
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+#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F0R1_FB19_Pos (19U)
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+#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F0R1_FB20_Pos (20U)
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+#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F0R1_FB21_Pos (21U)
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+#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F0R1_FB22_Pos (22U)
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+#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F0R1_FB23_Pos (23U)
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+#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F0R1_FB24_Pos (24U)
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+#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F0R1_FB25_Pos (25U)
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+#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F0R1_FB26_Pos (26U)
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+#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F0R1_FB27_Pos (27U)
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+#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F0R1_FB28_Pos (28U)
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+#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F0R1_FB29_Pos (29U)
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+#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F0R1_FB30_Pos (30U)
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+#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F0R1_FB31_Pos (31U)
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+#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F1R1 register *******************/
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+#define CAN_F1R1_FB0_Pos (0U)
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+#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F1R1_FB1_Pos (1U)
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+#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F1R1_FB2_Pos (2U)
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+#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F1R1_FB3_Pos (3U)
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+#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F1R1_FB4_Pos (4U)
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+#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F1R1_FB5_Pos (5U)
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+#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F1R1_FB6_Pos (6U)
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+#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F1R1_FB7_Pos (7U)
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+#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F1R1_FB8_Pos (8U)
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+#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F1R1_FB9_Pos (9U)
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+#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F1R1_FB10_Pos (10U)
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+#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F1R1_FB11_Pos (11U)
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+#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F1R1_FB12_Pos (12U)
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+#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F1R1_FB13_Pos (13U)
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+#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F1R1_FB14_Pos (14U)
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+#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F1R1_FB15_Pos (15U)
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+#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F1R1_FB16_Pos (16U)
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+#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F1R1_FB17_Pos (17U)
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+#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F1R1_FB18_Pos (18U)
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+#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F1R1_FB19_Pos (19U)
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+#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F1R1_FB20_Pos (20U)
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+#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F1R1_FB21_Pos (21U)
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+#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F1R1_FB22_Pos (22U)
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+#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F1R1_FB23_Pos (23U)
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+#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F1R1_FB24_Pos (24U)
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+#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F1R1_FB25_Pos (25U)
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+#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F1R1_FB26_Pos (26U)
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+#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F1R1_FB27_Pos (27U)
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+#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F1R1_FB28_Pos (28U)
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+#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F1R1_FB29_Pos (29U)
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+#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F1R1_FB30_Pos (30U)
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+#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F1R1_FB31_Pos (31U)
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+#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F2R1 register *******************/
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+#define CAN_F2R1_FB0_Pos (0U)
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+#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F2R1_FB1_Pos (1U)
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+#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F2R1_FB2_Pos (2U)
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+#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F2R1_FB3_Pos (3U)
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+#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F2R1_FB4_Pos (4U)
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+#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F2R1_FB5_Pos (5U)
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+#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F2R1_FB6_Pos (6U)
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+#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F2R1_FB7_Pos (7U)
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+#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F2R1_FB8_Pos (8U)
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+#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F2R1_FB9_Pos (9U)
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+#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F2R1_FB10_Pos (10U)
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+#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F2R1_FB11_Pos (11U)
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+#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F2R1_FB12_Pos (12U)
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+#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F2R1_FB13_Pos (13U)
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+#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F2R1_FB14_Pos (14U)
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+#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F2R1_FB15_Pos (15U)
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+#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F2R1_FB16_Pos (16U)
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+#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F2R1_FB17_Pos (17U)
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+#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F2R1_FB18_Pos (18U)
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+#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F2R1_FB19_Pos (19U)
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+#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F2R1_FB20_Pos (20U)
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+#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F2R1_FB21_Pos (21U)
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+#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F2R1_FB22_Pos (22U)
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+#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F2R1_FB23_Pos (23U)
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+#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F2R1_FB24_Pos (24U)
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+#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F2R1_FB25_Pos (25U)
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+#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F2R1_FB26_Pos (26U)
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+#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F2R1_FB27_Pos (27U)
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+#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F2R1_FB28_Pos (28U)
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+#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F2R1_FB29_Pos (29U)
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+#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F2R1_FB30_Pos (30U)
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+#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F2R1_FB31_Pos (31U)
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+#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F3R1 register *******************/
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+#define CAN_F3R1_FB0_Pos (0U)
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+#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F3R1_FB1_Pos (1U)
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+#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F3R1_FB2_Pos (2U)
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+#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F3R1_FB3_Pos (3U)
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+#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F3R1_FB4_Pos (4U)
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+#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F3R1_FB5_Pos (5U)
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+#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F3R1_FB6_Pos (6U)
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+#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F3R1_FB7_Pos (7U)
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+#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F3R1_FB8_Pos (8U)
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+#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F3R1_FB9_Pos (9U)
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+#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F3R1_FB10_Pos (10U)
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+#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F3R1_FB11_Pos (11U)
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+#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F3R1_FB12_Pos (12U)
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+#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F3R1_FB13_Pos (13U)
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+#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F3R1_FB14_Pos (14U)
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+#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F3R1_FB15_Pos (15U)
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+#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F3R1_FB16_Pos (16U)
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+#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F3R1_FB17_Pos (17U)
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+#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F3R1_FB18_Pos (18U)
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+#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F3R1_FB19_Pos (19U)
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+#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F3R1_FB20_Pos (20U)
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+#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F3R1_FB21_Pos (21U)
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+#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F3R1_FB22_Pos (22U)
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+#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F3R1_FB23_Pos (23U)
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+#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F3R1_FB24_Pos (24U)
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+#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F3R1_FB25_Pos (25U)
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+#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F3R1_FB26_Pos (26U)
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+#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F3R1_FB27_Pos (27U)
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+#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F3R1_FB28_Pos (28U)
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+#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F3R1_FB29_Pos (29U)
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+#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F3R1_FB30_Pos (30U)
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+#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F3R1_FB31_Pos (31U)
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+#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F4R1 register *******************/
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+#define CAN_F4R1_FB0_Pos (0U)
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+#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F4R1_FB1_Pos (1U)
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+#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F4R1_FB2_Pos (2U)
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+#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F4R1_FB3_Pos (3U)
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+#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F4R1_FB4_Pos (4U)
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+#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F4R1_FB5_Pos (5U)
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+#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F4R1_FB6_Pos (6U)
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+#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F4R1_FB7_Pos (7U)
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+#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F4R1_FB8_Pos (8U)
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+#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F4R1_FB9_Pos (9U)
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+#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F4R1_FB10_Pos (10U)
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+#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F4R1_FB11_Pos (11U)
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+#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F4R1_FB12_Pos (12U)
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+#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F4R1_FB13_Pos (13U)
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+#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F4R1_FB14_Pos (14U)
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+#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F4R1_FB15_Pos (15U)
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+#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F4R1_FB16_Pos (16U)
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+#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F4R1_FB17_Pos (17U)
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+#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F4R1_FB18_Pos (18U)
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+#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F4R1_FB19_Pos (19U)
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+#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F4R1_FB20_Pos (20U)
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+#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F4R1_FB21_Pos (21U)
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+#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F4R1_FB22_Pos (22U)
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+#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F4R1_FB23_Pos (23U)
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+#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F4R1_FB24_Pos (24U)
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+#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F4R1_FB25_Pos (25U)
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+#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F4R1_FB26_Pos (26U)
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+#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F4R1_FB27_Pos (27U)
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+#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F4R1_FB28_Pos (28U)
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+#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F4R1_FB29_Pos (29U)
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+#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F4R1_FB30_Pos (30U)
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+#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F4R1_FB31_Pos (31U)
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+#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F5R1 register *******************/
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+#define CAN_F5R1_FB0_Pos (0U)
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+#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F5R1_FB1_Pos (1U)
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+#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F5R1_FB2_Pos (2U)
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+#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F5R1_FB3_Pos (3U)
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+#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F5R1_FB4_Pos (4U)
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+#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F5R1_FB5_Pos (5U)
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+#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F5R1_FB6_Pos (6U)
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+#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F5R1_FB7_Pos (7U)
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+#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F5R1_FB8_Pos (8U)
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+#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F5R1_FB9_Pos (9U)
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+#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F5R1_FB10_Pos (10U)
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+#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F5R1_FB11_Pos (11U)
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+#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F5R1_FB12_Pos (12U)
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+#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F5R1_FB13_Pos (13U)
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+#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F5R1_FB14_Pos (14U)
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+#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F5R1_FB15_Pos (15U)
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+#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F5R1_FB16_Pos (16U)
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+#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F5R1_FB17_Pos (17U)
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+#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F5R1_FB18_Pos (18U)
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+#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F5R1_FB19_Pos (19U)
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+#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F5R1_FB20_Pos (20U)
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+#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F5R1_FB21_Pos (21U)
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+#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F5R1_FB22_Pos (22U)
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+#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F5R1_FB23_Pos (23U)
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+#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F5R1_FB24_Pos (24U)
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+#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F5R1_FB25_Pos (25U)
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+#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F5R1_FB26_Pos (26U)
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+#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F5R1_FB27_Pos (27U)
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+#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F5R1_FB28_Pos (28U)
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+#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F5R1_FB29_Pos (29U)
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+#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F5R1_FB30_Pos (30U)
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+#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F5R1_FB31_Pos (31U)
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+#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F6R1 register *******************/
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+#define CAN_F6R1_FB0_Pos (0U)
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+#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F6R1_FB1_Pos (1U)
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+#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F6R1_FB2_Pos (2U)
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+#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F6R1_FB3_Pos (3U)
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+#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F6R1_FB4_Pos (4U)
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+#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F6R1_FB5_Pos (5U)
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+#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F6R1_FB6_Pos (6U)
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+#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F6R1_FB7_Pos (7U)
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+#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F6R1_FB8_Pos (8U)
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+#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F6R1_FB9_Pos (9U)
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+#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F6R1_FB10_Pos (10U)
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+#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F6R1_FB11_Pos (11U)
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+#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F6R1_FB12_Pos (12U)
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+#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F6R1_FB13_Pos (13U)
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+#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F6R1_FB14_Pos (14U)
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+#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F6R1_FB15_Pos (15U)
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+#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F6R1_FB16_Pos (16U)
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+#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F6R1_FB17_Pos (17U)
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+#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F6R1_FB18_Pos (18U)
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+#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F6R1_FB19_Pos (19U)
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+#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F6R1_FB20_Pos (20U)
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+#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F6R1_FB21_Pos (21U)
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+#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F6R1_FB22_Pos (22U)
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+#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F6R1_FB23_Pos (23U)
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+#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F6R1_FB24_Pos (24U)
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+#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F6R1_FB25_Pos (25U)
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+#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F6R1_FB26_Pos (26U)
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+#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F6R1_FB27_Pos (27U)
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+#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F6R1_FB28_Pos (28U)
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+#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F6R1_FB29_Pos (29U)
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+#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F6R1_FB30_Pos (30U)
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+#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F6R1_FB31_Pos (31U)
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+#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F7R1 register *******************/
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+#define CAN_F7R1_FB0_Pos (0U)
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+#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F7R1_FB1_Pos (1U)
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+#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F7R1_FB2_Pos (2U)
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+#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F7R1_FB3_Pos (3U)
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+#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F7R1_FB4_Pos (4U)
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+#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F7R1_FB5_Pos (5U)
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+#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F7R1_FB6_Pos (6U)
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+#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F7R1_FB7_Pos (7U)
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+#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F7R1_FB8_Pos (8U)
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+#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F7R1_FB9_Pos (9U)
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+#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F7R1_FB10_Pos (10U)
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+#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F7R1_FB11_Pos (11U)
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+#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F7R1_FB12_Pos (12U)
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+#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F7R1_FB13_Pos (13U)
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+#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F7R1_FB14_Pos (14U)
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+#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F7R1_FB15_Pos (15U)
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+#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F7R1_FB16_Pos (16U)
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+#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F7R1_FB17_Pos (17U)
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+#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F7R1_FB18_Pos (18U)
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+#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F7R1_FB19_Pos (19U)
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+#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F7R1_FB20_Pos (20U)
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+#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F7R1_FB21_Pos (21U)
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+#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F7R1_FB22_Pos (22U)
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+#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F7R1_FB23_Pos (23U)
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+#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F7R1_FB24_Pos (24U)
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+#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F7R1_FB25_Pos (25U)
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+#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F7R1_FB26_Pos (26U)
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+#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F7R1_FB27_Pos (27U)
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+#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F7R1_FB28_Pos (28U)
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+#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F7R1_FB29_Pos (29U)
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+#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F7R1_FB30_Pos (30U)
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+#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F7R1_FB31_Pos (31U)
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+#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
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+
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|
+/******************* Bit definition for CAN_F8R1 register *******************/
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+#define CAN_F8R1_FB0_Pos (0U)
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+#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F8R1_FB1_Pos (1U)
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+#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F8R1_FB2_Pos (2U)
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+#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F8R1_FB3_Pos (3U)
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+#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F8R1_FB4_Pos (4U)
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+#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F8R1_FB5_Pos (5U)
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+#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F8R1_FB6_Pos (6U)
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+#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F8R1_FB7_Pos (7U)
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+#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F8R1_FB8_Pos (8U)
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+#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F8R1_FB9_Pos (9U)
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+#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F8R1_FB10_Pos (10U)
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+#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F8R1_FB11_Pos (11U)
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+#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F8R1_FB12_Pos (12U)
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+#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F8R1_FB13_Pos (13U)
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+#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F8R1_FB14_Pos (14U)
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+#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F8R1_FB15_Pos (15U)
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+#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F8R1_FB16_Pos (16U)
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+#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F8R1_FB17_Pos (17U)
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+#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F8R1_FB18_Pos (18U)
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+#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F8R1_FB19_Pos (19U)
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+#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F8R1_FB20_Pos (20U)
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+#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F8R1_FB21_Pos (21U)
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+#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F8R1_FB22_Pos (22U)
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+#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F8R1_FB23_Pos (23U)
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+#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F8R1_FB24_Pos (24U)
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+#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F8R1_FB25_Pos (25U)
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+#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F8R1_FB26_Pos (26U)
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+#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F8R1_FB27_Pos (27U)
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+#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F8R1_FB28_Pos (28U)
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+#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F8R1_FB29_Pos (29U)
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+#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F8R1_FB30_Pos (30U)
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+#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F8R1_FB31_Pos (31U)
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+#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F9R1 register *******************/
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+#define CAN_F9R1_FB0_Pos (0U)
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+#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F9R1_FB1_Pos (1U)
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+#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F9R1_FB2_Pos (2U)
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+#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F9R1_FB3_Pos (3U)
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+#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F9R1_FB4_Pos (4U)
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+#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F9R1_FB5_Pos (5U)
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+#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F9R1_FB6_Pos (6U)
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+#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F9R1_FB7_Pos (7U)
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+#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F9R1_FB8_Pos (8U)
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+#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F9R1_FB9_Pos (9U)
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+#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F9R1_FB10_Pos (10U)
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+#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F9R1_FB11_Pos (11U)
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+#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F9R1_FB12_Pos (12U)
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+#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F9R1_FB13_Pos (13U)
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+#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F9R1_FB14_Pos (14U)
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+#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F9R1_FB15_Pos (15U)
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+#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F9R1_FB16_Pos (16U)
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+#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F9R1_FB17_Pos (17U)
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+#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F9R1_FB18_Pos (18U)
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+#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F9R1_FB19_Pos (19U)
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+#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F9R1_FB20_Pos (20U)
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+#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F9R1_FB21_Pos (21U)
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+#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F9R1_FB22_Pos (22U)
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+#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F9R1_FB23_Pos (23U)
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+#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F9R1_FB24_Pos (24U)
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+#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F9R1_FB25_Pos (25U)
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+#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F9R1_FB26_Pos (26U)
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+#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F9R1_FB27_Pos (27U)
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+#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F9R1_FB28_Pos (28U)
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+#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F9R1_FB29_Pos (29U)
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+#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F9R1_FB30_Pos (30U)
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+#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F9R1_FB31_Pos (31U)
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+#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F10R1 register ******************/
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+#define CAN_F10R1_FB0_Pos (0U)
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+#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F10R1_FB1_Pos (1U)
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+#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F10R1_FB2_Pos (2U)
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+#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F10R1_FB3_Pos (3U)
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+#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F10R1_FB4_Pos (4U)
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+#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F10R1_FB5_Pos (5U)
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+#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F10R1_FB6_Pos (6U)
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+#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F10R1_FB7_Pos (7U)
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+#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F10R1_FB8_Pos (8U)
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+#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F10R1_FB9_Pos (9U)
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+#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F10R1_FB10_Pos (10U)
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+#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F10R1_FB11_Pos (11U)
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+#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F10R1_FB12_Pos (12U)
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+#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F10R1_FB13_Pos (13U)
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+#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F10R1_FB14_Pos (14U)
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+#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F10R1_FB15_Pos (15U)
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+#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F10R1_FB16_Pos (16U)
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+#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F10R1_FB17_Pos (17U)
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+#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F10R1_FB18_Pos (18U)
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+#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F10R1_FB19_Pos (19U)
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+#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F10R1_FB20_Pos (20U)
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+#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F10R1_FB21_Pos (21U)
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+#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F10R1_FB22_Pos (22U)
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+#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F10R1_FB23_Pos (23U)
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+#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F10R1_FB24_Pos (24U)
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+#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F10R1_FB25_Pos (25U)
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+#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F10R1_FB26_Pos (26U)
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+#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F10R1_FB27_Pos (27U)
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+#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F10R1_FB28_Pos (28U)
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+#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F10R1_FB29_Pos (29U)
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+#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F10R1_FB30_Pos (30U)
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+#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F10R1_FB31_Pos (31U)
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+#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F11R1 register ******************/
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+#define CAN_F11R1_FB0_Pos (0U)
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+#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F11R1_FB1_Pos (1U)
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+#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F11R1_FB2_Pos (2U)
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+#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F11R1_FB3_Pos (3U)
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+#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F11R1_FB4_Pos (4U)
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+#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F11R1_FB5_Pos (5U)
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+#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F11R1_FB6_Pos (6U)
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+#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F11R1_FB7_Pos (7U)
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+#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F11R1_FB8_Pos (8U)
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+#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F11R1_FB9_Pos (9U)
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+#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F11R1_FB10_Pos (10U)
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+#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F11R1_FB11_Pos (11U)
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+#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F11R1_FB12_Pos (12U)
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+#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F11R1_FB13_Pos (13U)
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+#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F11R1_FB14_Pos (14U)
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+#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F11R1_FB15_Pos (15U)
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+#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F11R1_FB16_Pos (16U)
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+#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F11R1_FB17_Pos (17U)
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+#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F11R1_FB18_Pos (18U)
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+#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F11R1_FB19_Pos (19U)
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+#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F11R1_FB20_Pos (20U)
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+#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F11R1_FB21_Pos (21U)
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+#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F11R1_FB22_Pos (22U)
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+#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F11R1_FB23_Pos (23U)
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+#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F11R1_FB24_Pos (24U)
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+#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F11R1_FB25_Pos (25U)
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+#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F11R1_FB26_Pos (26U)
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+#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F11R1_FB27_Pos (27U)
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+#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F11R1_FB28_Pos (28U)
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+#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F11R1_FB29_Pos (29U)
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+#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F11R1_FB30_Pos (30U)
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+#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F11R1_FB31_Pos (31U)
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+#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F12R1 register ******************/
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+#define CAN_F12R1_FB0_Pos (0U)
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+#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F12R1_FB1_Pos (1U)
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+#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F12R1_FB2_Pos (2U)
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+#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F12R1_FB3_Pos (3U)
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+#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F12R1_FB4_Pos (4U)
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+#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F12R1_FB5_Pos (5U)
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+#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F12R1_FB6_Pos (6U)
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+#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F12R1_FB7_Pos (7U)
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+#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F12R1_FB8_Pos (8U)
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+#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F12R1_FB9_Pos (9U)
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+#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F12R1_FB10_Pos (10U)
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+#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F12R1_FB11_Pos (11U)
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+#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F12R1_FB12_Pos (12U)
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+#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F12R1_FB13_Pos (13U)
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+#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F12R1_FB14_Pos (14U)
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+#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F12R1_FB15_Pos (15U)
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+#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F12R1_FB16_Pos (16U)
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+#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F12R1_FB17_Pos (17U)
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+#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F12R1_FB18_Pos (18U)
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+#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F12R1_FB19_Pos (19U)
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+#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F12R1_FB20_Pos (20U)
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+#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F12R1_FB21_Pos (21U)
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+#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F12R1_FB22_Pos (22U)
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+#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F12R1_FB23_Pos (23U)
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+#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F12R1_FB24_Pos (24U)
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+#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F12R1_FB25_Pos (25U)
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+#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F12R1_FB26_Pos (26U)
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+#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F12R1_FB27_Pos (27U)
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+#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F12R1_FB28_Pos (28U)
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+#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F12R1_FB29_Pos (29U)
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+#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F12R1_FB30_Pos (30U)
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+#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F12R1_FB31_Pos (31U)
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+#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F13R1 register ******************/
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+#define CAN_F13R1_FB0_Pos (0U)
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+#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F13R1_FB1_Pos (1U)
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+#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F13R1_FB2_Pos (2U)
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+#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F13R1_FB3_Pos (3U)
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+#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F13R1_FB4_Pos (4U)
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+#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F13R1_FB5_Pos (5U)
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+#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F13R1_FB6_Pos (6U)
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+#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F13R1_FB7_Pos (7U)
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+#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F13R1_FB8_Pos (8U)
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+#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F13R1_FB9_Pos (9U)
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+#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F13R1_FB10_Pos (10U)
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+#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F13R1_FB11_Pos (11U)
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+#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F13R1_FB12_Pos (12U)
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+#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F13R1_FB13_Pos (13U)
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+#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F13R1_FB14_Pos (14U)
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+#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F13R1_FB15_Pos (15U)
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+#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F13R1_FB16_Pos (16U)
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+#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F13R1_FB17_Pos (17U)
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+#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F13R1_FB18_Pos (18U)
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+#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F13R1_FB19_Pos (19U)
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+#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F13R1_FB20_Pos (20U)
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+#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F13R1_FB21_Pos (21U)
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+#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F13R1_FB22_Pos (22U)
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+#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F13R1_FB23_Pos (23U)
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+#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F13R1_FB24_Pos (24U)
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+#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F13R1_FB25_Pos (25U)
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+#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F13R1_FB26_Pos (26U)
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+#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F13R1_FB27_Pos (27U)
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+#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F13R1_FB28_Pos (28U)
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+#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F13R1_FB29_Pos (29U)
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+#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F13R1_FB30_Pos (30U)
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+#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F13R1_FB31_Pos (31U)
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+#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F0R2 register *******************/
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+#define CAN_F0R2_FB0_Pos (0U)
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+#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F0R2_FB1_Pos (1U)
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+#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F0R2_FB2_Pos (2U)
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+#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F0R2_FB3_Pos (3U)
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+#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F0R2_FB4_Pos (4U)
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+#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F0R2_FB5_Pos (5U)
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+#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F0R2_FB6_Pos (6U)
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+#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F0R2_FB7_Pos (7U)
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+#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F0R2_FB8_Pos (8U)
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+#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F0R2_FB9_Pos (9U)
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+#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F0R2_FB10_Pos (10U)
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+#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F0R2_FB11_Pos (11U)
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+#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F0R2_FB12_Pos (12U)
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+#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F0R2_FB13_Pos (13U)
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+#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F0R2_FB14_Pos (14U)
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+#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F0R2_FB15_Pos (15U)
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+#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F0R2_FB16_Pos (16U)
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+#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F0R2_FB17_Pos (17U)
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+#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F0R2_FB18_Pos (18U)
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+#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F0R2_FB19_Pos (19U)
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+#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F0R2_FB20_Pos (20U)
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+#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F0R2_FB21_Pos (21U)
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+#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F0R2_FB22_Pos (22U)
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+#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F0R2_FB23_Pos (23U)
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+#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F0R2_FB24_Pos (24U)
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+#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F0R2_FB25_Pos (25U)
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+#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F0R2_FB26_Pos (26U)
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+#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F0R2_FB27_Pos (27U)
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+#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F0R2_FB28_Pos (28U)
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+#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F0R2_FB29_Pos (29U)
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+#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F0R2_FB30_Pos (30U)
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+#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F0R2_FB31_Pos (31U)
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+#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F1R2 register *******************/
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+#define CAN_F1R2_FB0_Pos (0U)
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+#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F1R2_FB1_Pos (1U)
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+#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F1R2_FB2_Pos (2U)
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+#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F1R2_FB3_Pos (3U)
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+#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F1R2_FB4_Pos (4U)
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+#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F1R2_FB5_Pos (5U)
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+#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F1R2_FB6_Pos (6U)
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+#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F1R2_FB7_Pos (7U)
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+#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F1R2_FB8_Pos (8U)
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+#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F1R2_FB9_Pos (9U)
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+#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F1R2_FB10_Pos (10U)
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+#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F1R2_FB11_Pos (11U)
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+#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F1R2_FB12_Pos (12U)
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+#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F1R2_FB13_Pos (13U)
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+#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F1R2_FB14_Pos (14U)
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+#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F1R2_FB15_Pos (15U)
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+#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F1R2_FB16_Pos (16U)
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+#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F1R2_FB17_Pos (17U)
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+#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F1R2_FB18_Pos (18U)
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+#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F1R2_FB19_Pos (19U)
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+#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F1R2_FB20_Pos (20U)
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+#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F1R2_FB21_Pos (21U)
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+#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F1R2_FB22_Pos (22U)
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+#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F1R2_FB23_Pos (23U)
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+#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F1R2_FB24_Pos (24U)
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+#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F1R2_FB25_Pos (25U)
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+#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F1R2_FB26_Pos (26U)
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+#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F1R2_FB27_Pos (27U)
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+#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F1R2_FB28_Pos (28U)
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+#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F1R2_FB29_Pos (29U)
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+#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F1R2_FB30_Pos (30U)
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+#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F1R2_FB31_Pos (31U)
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+#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F2R2 register *******************/
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+#define CAN_F2R2_FB0_Pos (0U)
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+#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F2R2_FB1_Pos (1U)
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+#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F2R2_FB2_Pos (2U)
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+#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F2R2_FB3_Pos (3U)
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+#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F2R2_FB4_Pos (4U)
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+#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F2R2_FB5_Pos (5U)
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+#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F2R2_FB6_Pos (6U)
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+#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F2R2_FB7_Pos (7U)
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+#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F2R2_FB8_Pos (8U)
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+#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F2R2_FB9_Pos (9U)
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+#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F2R2_FB10_Pos (10U)
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+#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F2R2_FB11_Pos (11U)
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+#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F2R2_FB12_Pos (12U)
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+#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F2R2_FB13_Pos (13U)
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+#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F2R2_FB14_Pos (14U)
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+#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F2R2_FB15_Pos (15U)
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+#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F2R2_FB16_Pos (16U)
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+#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F2R2_FB17_Pos (17U)
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+#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F2R2_FB18_Pos (18U)
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+#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F2R2_FB19_Pos (19U)
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+#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F2R2_FB20_Pos (20U)
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+#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F2R2_FB21_Pos (21U)
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+#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F2R2_FB22_Pos (22U)
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+#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F2R2_FB23_Pos (23U)
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+#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F2R2_FB24_Pos (24U)
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+#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F2R2_FB25_Pos (25U)
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+#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F2R2_FB26_Pos (26U)
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+#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F2R2_FB27_Pos (27U)
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+#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F2R2_FB28_Pos (28U)
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+#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F2R2_FB29_Pos (29U)
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+#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F2R2_FB30_Pos (30U)
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+#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F2R2_FB31_Pos (31U)
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+#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F3R2 register *******************/
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+#define CAN_F3R2_FB0_Pos (0U)
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+#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F3R2_FB1_Pos (1U)
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+#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F3R2_FB2_Pos (2U)
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+#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F3R2_FB3_Pos (3U)
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+#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F3R2_FB4_Pos (4U)
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+#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F3R2_FB5_Pos (5U)
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+#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F3R2_FB6_Pos (6U)
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+#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F3R2_FB7_Pos (7U)
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+#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F3R2_FB8_Pos (8U)
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+#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F3R2_FB9_Pos (9U)
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+#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F3R2_FB10_Pos (10U)
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+#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F3R2_FB11_Pos (11U)
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+#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F3R2_FB12_Pos (12U)
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+#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F3R2_FB13_Pos (13U)
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+#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F3R2_FB14_Pos (14U)
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+#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F3R2_FB15_Pos (15U)
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+#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F3R2_FB16_Pos (16U)
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+#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F3R2_FB17_Pos (17U)
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+#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F3R2_FB18_Pos (18U)
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+#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F3R2_FB19_Pos (19U)
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+#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F3R2_FB20_Pos (20U)
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+#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F3R2_FB21_Pos (21U)
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+#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F3R2_FB22_Pos (22U)
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+#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F3R2_FB23_Pos (23U)
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+#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F3R2_FB24_Pos (24U)
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+#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F3R2_FB25_Pos (25U)
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+#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F3R2_FB26_Pos (26U)
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+#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F3R2_FB27_Pos (27U)
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+#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F3R2_FB28_Pos (28U)
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+#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F3R2_FB29_Pos (29U)
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+#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F3R2_FB30_Pos (30U)
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+#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F3R2_FB31_Pos (31U)
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+#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F4R2 register *******************/
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+#define CAN_F4R2_FB0_Pos (0U)
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+#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F4R2_FB1_Pos (1U)
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+#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F4R2_FB2_Pos (2U)
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+#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F4R2_FB3_Pos (3U)
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+#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F4R2_FB4_Pos (4U)
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+#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F4R2_FB5_Pos (5U)
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+#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F4R2_FB6_Pos (6U)
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+#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F4R2_FB7_Pos (7U)
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+#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F4R2_FB8_Pos (8U)
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+#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F4R2_FB9_Pos (9U)
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+#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F4R2_FB10_Pos (10U)
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+#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F4R2_FB11_Pos (11U)
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+#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F4R2_FB12_Pos (12U)
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+#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F4R2_FB13_Pos (13U)
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+#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F4R2_FB14_Pos (14U)
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+#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F4R2_FB15_Pos (15U)
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+#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F4R2_FB16_Pos (16U)
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+#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F4R2_FB17_Pos (17U)
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+#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F4R2_FB18_Pos (18U)
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+#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F4R2_FB19_Pos (19U)
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+#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F4R2_FB20_Pos (20U)
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+#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F4R2_FB21_Pos (21U)
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+#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F4R2_FB22_Pos (22U)
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+#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F4R2_FB23_Pos (23U)
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+#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F4R2_FB24_Pos (24U)
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+#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F4R2_FB25_Pos (25U)
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+#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F4R2_FB26_Pos (26U)
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+#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F4R2_FB27_Pos (27U)
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+#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F4R2_FB28_Pos (28U)
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+#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F4R2_FB29_Pos (29U)
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+#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F4R2_FB30_Pos (30U)
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+#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F4R2_FB31_Pos (31U)
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+#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F5R2 register *******************/
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+#define CAN_F5R2_FB0_Pos (0U)
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+#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F5R2_FB1_Pos (1U)
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+#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F5R2_FB2_Pos (2U)
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+#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F5R2_FB3_Pos (3U)
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+#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F5R2_FB4_Pos (4U)
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+#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F5R2_FB5_Pos (5U)
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+#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F5R2_FB6_Pos (6U)
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+#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F5R2_FB7_Pos (7U)
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+#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F5R2_FB8_Pos (8U)
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+#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F5R2_FB9_Pos (9U)
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+#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F5R2_FB10_Pos (10U)
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+#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F5R2_FB11_Pos (11U)
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+#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F5R2_FB12_Pos (12U)
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+#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F5R2_FB13_Pos (13U)
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+#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F5R2_FB14_Pos (14U)
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+#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F5R2_FB15_Pos (15U)
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+#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F5R2_FB16_Pos (16U)
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+#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F5R2_FB17_Pos (17U)
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+#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F5R2_FB18_Pos (18U)
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+#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F5R2_FB19_Pos (19U)
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+#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F5R2_FB20_Pos (20U)
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+#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F5R2_FB21_Pos (21U)
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+#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F5R2_FB22_Pos (22U)
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+#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F5R2_FB23_Pos (23U)
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+#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F5R2_FB24_Pos (24U)
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+#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F5R2_FB25_Pos (25U)
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+#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F5R2_FB26_Pos (26U)
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+#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F5R2_FB27_Pos (27U)
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+#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F5R2_FB28_Pos (28U)
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+#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F5R2_FB29_Pos (29U)
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+#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F5R2_FB30_Pos (30U)
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+#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F5R2_FB31_Pos (31U)
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+#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F6R2 register *******************/
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+#define CAN_F6R2_FB0_Pos (0U)
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+#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F6R2_FB1_Pos (1U)
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+#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F6R2_FB2_Pos (2U)
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+#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F6R2_FB3_Pos (3U)
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+#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F6R2_FB4_Pos (4U)
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+#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F6R2_FB5_Pos (5U)
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+#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F6R2_FB6_Pos (6U)
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+#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F6R2_FB7_Pos (7U)
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+#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F6R2_FB8_Pos (8U)
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+#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F6R2_FB9_Pos (9U)
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+#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F6R2_FB10_Pos (10U)
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+#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F6R2_FB11_Pos (11U)
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+#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F6R2_FB12_Pos (12U)
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+#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F6R2_FB13_Pos (13U)
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+#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F6R2_FB14_Pos (14U)
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+#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F6R2_FB15_Pos (15U)
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+#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F6R2_FB16_Pos (16U)
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+#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F6R2_FB17_Pos (17U)
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+#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F6R2_FB18_Pos (18U)
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+#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F6R2_FB19_Pos (19U)
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+#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F6R2_FB20_Pos (20U)
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+#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F6R2_FB21_Pos (21U)
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+#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F6R2_FB22_Pos (22U)
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+#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F6R2_FB23_Pos (23U)
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+#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F6R2_FB24_Pos (24U)
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+#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F6R2_FB25_Pos (25U)
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+#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F6R2_FB26_Pos (26U)
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+#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F6R2_FB27_Pos (27U)
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+#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F6R2_FB28_Pos (28U)
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+#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F6R2_FB29_Pos (29U)
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+#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F6R2_FB30_Pos (30U)
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+#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F6R2_FB31_Pos (31U)
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+#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F7R2 register *******************/
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+#define CAN_F7R2_FB0_Pos (0U)
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+#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F7R2_FB1_Pos (1U)
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+#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F7R2_FB2_Pos (2U)
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+#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F7R2_FB3_Pos (3U)
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+#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F7R2_FB4_Pos (4U)
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+#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F7R2_FB5_Pos (5U)
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+#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F7R2_FB6_Pos (6U)
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+#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F7R2_FB7_Pos (7U)
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+#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F7R2_FB8_Pos (8U)
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+#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F7R2_FB9_Pos (9U)
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+#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F7R2_FB10_Pos (10U)
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+#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F7R2_FB11_Pos (11U)
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+#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F7R2_FB12_Pos (12U)
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+#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F7R2_FB13_Pos (13U)
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+#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F7R2_FB14_Pos (14U)
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+#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F7R2_FB15_Pos (15U)
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+#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F7R2_FB16_Pos (16U)
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+#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F7R2_FB17_Pos (17U)
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+#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F7R2_FB18_Pos (18U)
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+#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F7R2_FB19_Pos (19U)
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+#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F7R2_FB20_Pos (20U)
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+#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F7R2_FB21_Pos (21U)
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+#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F7R2_FB22_Pos (22U)
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+#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F7R2_FB23_Pos (23U)
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+#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F7R2_FB24_Pos (24U)
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+#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F7R2_FB25_Pos (25U)
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+#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F7R2_FB26_Pos (26U)
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+#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F7R2_FB27_Pos (27U)
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+#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F7R2_FB28_Pos (28U)
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+#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F7R2_FB29_Pos (29U)
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+#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F7R2_FB30_Pos (30U)
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+#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F7R2_FB31_Pos (31U)
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+#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F8R2 register *******************/
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+#define CAN_F8R2_FB0_Pos (0U)
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+#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F8R2_FB1_Pos (1U)
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+#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F8R2_FB2_Pos (2U)
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+#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F8R2_FB3_Pos (3U)
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+#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F8R2_FB4_Pos (4U)
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+#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F8R2_FB5_Pos (5U)
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+#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F8R2_FB6_Pos (6U)
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+#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F8R2_FB7_Pos (7U)
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+#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F8R2_FB8_Pos (8U)
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+#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F8R2_FB9_Pos (9U)
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+#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F8R2_FB10_Pos (10U)
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+#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F8R2_FB11_Pos (11U)
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+#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F8R2_FB12_Pos (12U)
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+#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F8R2_FB13_Pos (13U)
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+#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F8R2_FB14_Pos (14U)
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+#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F8R2_FB15_Pos (15U)
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+#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F8R2_FB16_Pos (16U)
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+#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F8R2_FB17_Pos (17U)
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+#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F8R2_FB18_Pos (18U)
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+#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F8R2_FB19_Pos (19U)
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+#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F8R2_FB20_Pos (20U)
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+#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F8R2_FB21_Pos (21U)
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+#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F8R2_FB22_Pos (22U)
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+#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F8R2_FB23_Pos (23U)
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+#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F8R2_FB24_Pos (24U)
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+#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F8R2_FB25_Pos (25U)
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+#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F8R2_FB26_Pos (26U)
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+#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F8R2_FB27_Pos (27U)
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+#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F8R2_FB28_Pos (28U)
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+#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F8R2_FB29_Pos (29U)
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+#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F8R2_FB30_Pos (30U)
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+#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F8R2_FB31_Pos (31U)
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+#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F9R2 register *******************/
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+#define CAN_F9R2_FB0_Pos (0U)
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+#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F9R2_FB1_Pos (1U)
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+#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F9R2_FB2_Pos (2U)
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+#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F9R2_FB3_Pos (3U)
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+#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F9R2_FB4_Pos (4U)
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+#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F9R2_FB5_Pos (5U)
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+#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F9R2_FB6_Pos (6U)
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+#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F9R2_FB7_Pos (7U)
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+#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F9R2_FB8_Pos (8U)
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+#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F9R2_FB9_Pos (9U)
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+#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F9R2_FB10_Pos (10U)
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+#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F9R2_FB11_Pos (11U)
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+#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F9R2_FB12_Pos (12U)
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+#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F9R2_FB13_Pos (13U)
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+#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F9R2_FB14_Pos (14U)
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+#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F9R2_FB15_Pos (15U)
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+#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F9R2_FB16_Pos (16U)
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+#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F9R2_FB17_Pos (17U)
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+#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F9R2_FB18_Pos (18U)
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+#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F9R2_FB19_Pos (19U)
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+#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F9R2_FB20_Pos (20U)
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+#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F9R2_FB21_Pos (21U)
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+#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F9R2_FB22_Pos (22U)
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+#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F9R2_FB23_Pos (23U)
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+#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F9R2_FB24_Pos (24U)
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+#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F9R2_FB25_Pos (25U)
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+#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F9R2_FB26_Pos (26U)
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+#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F9R2_FB27_Pos (27U)
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+#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F9R2_FB28_Pos (28U)
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+#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F9R2_FB29_Pos (29U)
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+#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F9R2_FB30_Pos (30U)
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+#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F9R2_FB31_Pos (31U)
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+#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F10R2 register ******************/
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+#define CAN_F10R2_FB0_Pos (0U)
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+#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F10R2_FB1_Pos (1U)
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+#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F10R2_FB2_Pos (2U)
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+#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F10R2_FB3_Pos (3U)
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+#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F10R2_FB4_Pos (4U)
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+#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F10R2_FB5_Pos (5U)
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+#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F10R2_FB6_Pos (6U)
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+#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F10R2_FB7_Pos (7U)
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+#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F10R2_FB8_Pos (8U)
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+#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F10R2_FB9_Pos (9U)
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+#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F10R2_FB10_Pos (10U)
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+#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F10R2_FB11_Pos (11U)
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+#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F10R2_FB12_Pos (12U)
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+#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F10R2_FB13_Pos (13U)
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+#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F10R2_FB14_Pos (14U)
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+#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F10R2_FB15_Pos (15U)
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+#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F10R2_FB16_Pos (16U)
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+#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F10R2_FB17_Pos (17U)
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+#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F10R2_FB18_Pos (18U)
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+#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F10R2_FB19_Pos (19U)
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+#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F10R2_FB20_Pos (20U)
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+#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F10R2_FB21_Pos (21U)
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+#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F10R2_FB22_Pos (22U)
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+#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F10R2_FB23_Pos (23U)
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+#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F10R2_FB24_Pos (24U)
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+#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F10R2_FB25_Pos (25U)
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+#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F10R2_FB26_Pos (26U)
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+#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F10R2_FB27_Pos (27U)
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+#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F10R2_FB28_Pos (28U)
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+#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F10R2_FB29_Pos (29U)
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+#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F10R2_FB30_Pos (30U)
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+#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F10R2_FB31_Pos (31U)
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+#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
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+
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|
|
+/******************* Bit definition for CAN_F11R2 register ******************/
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|
|
+#define CAN_F11R2_FB0_Pos (0U)
|
|
|
+#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F11R2_FB1_Pos (1U)
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+#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F11R2_FB2_Pos (2U)
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+#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F11R2_FB3_Pos (3U)
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+#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F11R2_FB4_Pos (4U)
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+#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F11R2_FB5_Pos (5U)
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+#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F11R2_FB6_Pos (6U)
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+#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F11R2_FB7_Pos (7U)
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+#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F11R2_FB8_Pos (8U)
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+#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F11R2_FB9_Pos (9U)
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+#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F11R2_FB10_Pos (10U)
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+#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F11R2_FB11_Pos (11U)
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+#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F11R2_FB12_Pos (12U)
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+#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F11R2_FB13_Pos (13U)
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+#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F11R2_FB14_Pos (14U)
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+#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F11R2_FB15_Pos (15U)
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+#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F11R2_FB16_Pos (16U)
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+#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F11R2_FB17_Pos (17U)
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+#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F11R2_FB18_Pos (18U)
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+#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F11R2_FB19_Pos (19U)
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+#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F11R2_FB20_Pos (20U)
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+#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F11R2_FB21_Pos (21U)
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+#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F11R2_FB22_Pos (22U)
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+#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F11R2_FB23_Pos (23U)
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+#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F11R2_FB24_Pos (24U)
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+#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F11R2_FB25_Pos (25U)
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+#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F11R2_FB26_Pos (26U)
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+#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F11R2_FB27_Pos (27U)
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+#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F11R2_FB28_Pos (28U)
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+#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F11R2_FB29_Pos (29U)
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+#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F11R2_FB30_Pos (30U)
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+#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F11R2_FB31_Pos (31U)
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+#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F12R2 register ******************/
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+#define CAN_F12R2_FB0_Pos (0U)
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+#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F12R2_FB1_Pos (1U)
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+#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F12R2_FB2_Pos (2U)
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+#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F12R2_FB3_Pos (3U)
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+#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F12R2_FB4_Pos (4U)
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+#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F12R2_FB5_Pos (5U)
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+#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F12R2_FB6_Pos (6U)
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+#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F12R2_FB7_Pos (7U)
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+#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F12R2_FB8_Pos (8U)
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+#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F12R2_FB9_Pos (9U)
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+#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F12R2_FB10_Pos (10U)
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+#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F12R2_FB11_Pos (11U)
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+#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F12R2_FB12_Pos (12U)
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+#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F12R2_FB13_Pos (13U)
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+#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F12R2_FB14_Pos (14U)
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+#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F12R2_FB15_Pos (15U)
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+#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F12R2_FB16_Pos (16U)
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+#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F12R2_FB17_Pos (17U)
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+#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F12R2_FB18_Pos (18U)
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+#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F12R2_FB19_Pos (19U)
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+#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F12R2_FB20_Pos (20U)
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+#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F12R2_FB21_Pos (21U)
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+#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F12R2_FB22_Pos (22U)
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+#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F12R2_FB23_Pos (23U)
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+#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F12R2_FB24_Pos (24U)
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+#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F12R2_FB25_Pos (25U)
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+#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F12R2_FB26_Pos (26U)
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+#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F12R2_FB27_Pos (27U)
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+#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F12R2_FB28_Pos (28U)
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+#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F12R2_FB29_Pos (29U)
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+#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F12R2_FB30_Pos (30U)
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+#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F12R2_FB31_Pos (31U)
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+#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************* Bit definition for CAN_F13R2 register ******************/
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+#define CAN_F13R2_FB0_Pos (0U)
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+#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
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+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
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+#define CAN_F13R2_FB1_Pos (1U)
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+#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
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+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
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+#define CAN_F13R2_FB2_Pos (2U)
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+#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
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+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
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+#define CAN_F13R2_FB3_Pos (3U)
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+#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
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+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
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+#define CAN_F13R2_FB4_Pos (4U)
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+#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
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+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
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+#define CAN_F13R2_FB5_Pos (5U)
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+#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
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+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
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+#define CAN_F13R2_FB6_Pos (6U)
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+#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
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+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
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+#define CAN_F13R2_FB7_Pos (7U)
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+#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
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+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
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+#define CAN_F13R2_FB8_Pos (8U)
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+#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
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+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
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+#define CAN_F13R2_FB9_Pos (9U)
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+#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
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+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
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+#define CAN_F13R2_FB10_Pos (10U)
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+#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
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+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
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+#define CAN_F13R2_FB11_Pos (11U)
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+#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
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+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
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+#define CAN_F13R2_FB12_Pos (12U)
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+#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
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+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
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+#define CAN_F13R2_FB13_Pos (13U)
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+#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
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+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
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+#define CAN_F13R2_FB14_Pos (14U)
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+#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
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+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
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+#define CAN_F13R2_FB15_Pos (15U)
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+#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
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+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
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+#define CAN_F13R2_FB16_Pos (16U)
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+#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
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+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
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+#define CAN_F13R2_FB17_Pos (17U)
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+#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
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+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
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+#define CAN_F13R2_FB18_Pos (18U)
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+#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
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+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
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+#define CAN_F13R2_FB19_Pos (19U)
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+#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
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+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
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+#define CAN_F13R2_FB20_Pos (20U)
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+#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
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+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
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+#define CAN_F13R2_FB21_Pos (21U)
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+#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
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+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
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+#define CAN_F13R2_FB22_Pos (22U)
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+#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
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+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
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+#define CAN_F13R2_FB23_Pos (23U)
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+#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
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+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
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+#define CAN_F13R2_FB24_Pos (24U)
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+#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
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+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
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+#define CAN_F13R2_FB25_Pos (25U)
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+#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
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+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
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+#define CAN_F13R2_FB26_Pos (26U)
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+#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
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+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
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+#define CAN_F13R2_FB27_Pos (27U)
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+#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
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+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
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+#define CAN_F13R2_FB28_Pos (28U)
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+#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
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+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
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+#define CAN_F13R2_FB29_Pos (29U)
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+#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
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+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
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+#define CAN_F13R2_FB30_Pos (30U)
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+#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
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+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
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+#define CAN_F13R2_FB31_Pos (31U)
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+#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
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+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
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+
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+/******************************************************************************/
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+/* */
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+/* HDMI-CEC (CEC) */
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+/* */
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+/******************************************************************************/
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+
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+/******************* Bit definition for CEC_CR register *********************/
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+#define CEC_CR_CECEN_Pos (0U)
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+#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
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+#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
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+#define CEC_CR_TXSOM_Pos (1U)
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+#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
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+#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
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+#define CEC_CR_TXEOM_Pos (2U)
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+#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
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+#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
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+
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+/******************* Bit definition for CEC_CFGR register *******************/
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+#define CEC_CFGR_SFT_Pos (0U)
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+#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
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+#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
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+#define CEC_CFGR_RXTOL_Pos (3U)
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+#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
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+#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
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+#define CEC_CFGR_BRESTP_Pos (4U)
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+#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
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+#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
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+#define CEC_CFGR_BREGEN_Pos (5U)
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+#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
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+#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
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+#define CEC_CFGR_LBPEGEN_Pos (6U)
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+#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
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+#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Period Error generation */
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+#define CEC_CFGR_BRDNOGEN_Pos (7U)
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+#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
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+#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast no Error generation */
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+#define CEC_CFGR_SFTOPT_Pos (8U)
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+#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
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+#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
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+#define CEC_CFGR_OAR_Pos (16U)
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+#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
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+#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
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+#define CEC_CFGR_LSTN_Pos (31U)
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+#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
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+#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
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+
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+/******************* Bit definition for CEC_TXDR register *******************/
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+#define CEC_TXDR_TXD_Pos (0U)
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+#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
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+#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
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+
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+/******************* Bit definition for CEC_RXDR register *******************/
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+#define CEC_RXDR_RXD_Pos (0U)
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+#define CEC_RXDR_RXD_Msk (0xFFU << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
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+#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
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+
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+/******************* Bit definition for CEC_ISR register ********************/
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+#define CEC_ISR_RXBR_Pos (0U)
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+#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
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+#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
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+#define CEC_ISR_RXEND_Pos (1U)
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+#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
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+#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
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+#define CEC_ISR_RXOVR_Pos (2U)
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+#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
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+#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
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+#define CEC_ISR_BRE_Pos (3U)
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+#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
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+#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
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+#define CEC_ISR_SBPE_Pos (4U)
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+#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
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+#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
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+#define CEC_ISR_LBPE_Pos (5U)
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+#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
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+#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
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+#define CEC_ISR_RXACKE_Pos (6U)
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+#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
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+#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
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+#define CEC_ISR_ARBLST_Pos (7U)
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+#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
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+#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
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+#define CEC_ISR_TXBR_Pos (8U)
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+#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
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+#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
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+#define CEC_ISR_TXEND_Pos (9U)
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+#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
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+#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
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+#define CEC_ISR_TXUDR_Pos (10U)
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+#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
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+#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
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+#define CEC_ISR_TXERR_Pos (11U)
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+#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
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+#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
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+#define CEC_ISR_TXACKE_Pos (12U)
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+#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
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+#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
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+
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+/******************* Bit definition for CEC_IER register ********************/
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+#define CEC_IER_RXBRIE_Pos (0U)
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+#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
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+#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
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+#define CEC_IER_RXENDIE_Pos (1U)
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+#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
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+#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
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+#define CEC_IER_RXOVRIE_Pos (2U)
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+#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
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+#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
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+#define CEC_IER_BREIE_Pos (3U)
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+#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
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+#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
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+#define CEC_IER_SBPEIE_Pos (4U)
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+#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
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+#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/
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+#define CEC_IER_LBPEIE_Pos (5U)
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+#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
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|
+#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
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|
+#define CEC_IER_RXACKEIE_Pos (6U)
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|
+#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
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|
+#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
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+#define CEC_IER_ARBLSTIE_Pos (7U)
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|
+#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
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|
+#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
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|
+#define CEC_IER_TXBRIE_Pos (8U)
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|
+#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
|
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|
+#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
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|
+#define CEC_IER_TXENDIE_Pos (9U)
|
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|
+#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
|
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|
+#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
|
|
|
+#define CEC_IER_TXUDRIE_Pos (10U)
|
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|
+#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
|
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|
+#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
|
|
|
+#define CEC_IER_TXERRIE_Pos (11U)
|
|
|
+#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
|
|
|
+#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
|
|
|
+#define CEC_IER_TXACKEIE_Pos (12U)
|
|
|
+#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
|
|
|
+#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
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|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* CRC calculation unit */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************* Bit definition for CRC_DR register *********************/
|
|
|
+#define CRC_DR_DR_Pos (0U)
|
|
|
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
|
|
|
+
|
|
|
+/******************* Bit definition for CRC_IDR register ********************/
|
|
|
+#define CRC_IDR_IDR_Pos (0U)
|
|
|
+#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
|
|
|
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
|
|
|
+
|
|
|
+/******************** Bit definition for CRC_CR register ********************/
|
|
|
+#define CRC_CR_RESET_Pos (0U)
|
|
|
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
|
|
|
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
|
|
|
+#define CRC_CR_POLYSIZE_Pos (3U)
|
|
|
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
|
|
|
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
|
|
|
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
|
|
|
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
|
|
|
+#define CRC_CR_REV_IN_Pos (5U)
|
|
|
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
|
|
|
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
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|
|
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
|
|
|
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
|
|
|
+#define CRC_CR_REV_OUT_Pos (7U)
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|
|
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
|
|
|
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
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|
|
+
|
|
|
+/******************* Bit definition for CRC_INIT register *******************/
|
|
|
+#define CRC_INIT_INIT_Pos (0U)
|
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|
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
|
|
|
+
|
|
|
+/******************* Bit definition for CRC_POL register ********************/
|
|
|
+#define CRC_POL_POL_Pos (0U)
|
|
|
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
|
|
|
+
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Digital to Analog Converter */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************** Bit definition for DAC_CR register ********************/
|
|
|
+#define DAC_CR_EN1_Pos (0U)
|
|
|
+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
|
|
|
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
|
|
|
+#define DAC_CR_BOFF1_Pos (1U)
|
|
|
+#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
|
|
|
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
|
|
|
+#define DAC_CR_TEN1_Pos (2U)
|
|
|
+#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
|
|
|
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
|
|
|
+#define DAC_CR_TSEL1_Pos (3U)
|
|
|
+#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
|
|
|
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
|
|
|
+#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
|
|
|
+#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
|
|
|
+#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
|
|
|
+#define DAC_CR_WAVE1_Pos (6U)
|
|
|
+#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
|
|
|
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
|
|
|
+#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
|
|
|
+#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
|
|
|
+#define DAC_CR_MAMP1_Pos (8U)
|
|
|
+#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
|
|
|
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
|
|
|
+#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
|
|
|
+#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
|
|
|
+#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
|
|
|
+#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
|
|
|
+#define DAC_CR_DMAEN1_Pos (12U)
|
|
|
+#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
|
|
|
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
|
|
|
+#define DAC_CR_DMAUDRIE1_Pos (13U)
|
|
|
+#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
|
|
|
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable */
|
|
|
+#define DAC_CR_EN2_Pos (16U)
|
|
|
+#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
|
|
|
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
|
|
|
+#define DAC_CR_BOFF2_Pos (17U)
|
|
|
+#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
|
|
|
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
|
|
|
+#define DAC_CR_TEN2_Pos (18U)
|
|
|
+#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
|
|
|
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
|
|
|
+#define DAC_CR_TSEL2_Pos (19U)
|
|
|
+#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
|
|
|
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
|
|
|
+#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
|
|
|
+#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
|
|
|
+#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
|
|
|
+#define DAC_CR_WAVE2_Pos (22U)
|
|
|
+#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
|
|
|
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
|
|
|
+#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
|
|
|
+#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
|
|
|
+#define DAC_CR_MAMP2_Pos (24U)
|
|
|
+#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
|
|
|
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
|
|
|
+#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
|
|
|
+#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
|
|
|
+#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
|
|
|
+#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
|
|
|
+#define DAC_CR_DMAEN2_Pos (28U)
|
|
|
+#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
|
|
|
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enable */
|
|
|
+#define DAC_CR_DMAUDRIE2_Pos (29U)
|
|
|
+#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
|
|
|
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */
|
|
|
+
|
|
|
+/***************** Bit definition for DAC_SWTRIGR register ******************/
|
|
|
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
|
|
|
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
|
|
|
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
|
|
|
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
|
|
|
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
|
|
|
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
|
|
|
+
|
|
|
+/***************** Bit definition for DAC_DHR12R1 register ******************/
|
|
|
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
|
|
|
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
|
|
|
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
|
|
|
+
|
|
|
+/***************** Bit definition for DAC_DHR12L1 register ******************/
|
|
|
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
|
|
|
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
|
|
|
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
|
|
|
+
|
|
|
+/****************** Bit definition for DAC_DHR8R1 register ******************/
|
|
|
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
|
|
|
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
|
|
|
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
|
|
|
+
|
|
|
+/***************** Bit definition for DAC_DHR12R2 register ******************/
|
|
|
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
|
|
|
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
|
|
|
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
|
|
|
+
|
|
|
+/***************** Bit definition for DAC_DHR12L2 register ******************/
|
|
|
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
|
|
|
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
|
|
|
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
|
|
|
+
|
|
|
+/****************** Bit definition for DAC_DHR8R2 register ******************/
|
|
|
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
|
|
|
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
|
|
|
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
|
|
|
+
|
|
|
+/***************** Bit definition for DAC_DHR12RD register ******************/
|
|
|
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
|
|
|
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
|
|
|
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
|
|
|
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
|
|
|
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
|
|
|
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
|
|
|
+
|
|
|
+/***************** Bit definition for DAC_DHR12LD register ******************/
|
|
|
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
|
|
|
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
|
|
|
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
|
|
|
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
|
|
|
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
|
|
|
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
|
|
|
+
|
|
|
+/****************** Bit definition for DAC_DHR8RD register ******************/
|
|
|
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
|
|
|
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
|
|
|
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
|
|
|
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
|
|
|
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
|
|
|
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
|
|
|
+
|
|
|
+/******************* Bit definition for DAC_DOR1 register *******************/
|
|
|
+#define DAC_DOR1_DACC1DOR_Pos (0U)
|
|
|
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
|
|
|
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
|
|
|
+
|
|
|
+/******************* Bit definition for DAC_DOR2 register *******************/
|
|
|
+#define DAC_DOR2_DACC2DOR_Pos (0U)
|
|
|
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
|
|
|
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
|
|
|
+
|
|
|
+/******************** Bit definition for DAC_SR register ********************/
|
|
|
+#define DAC_SR_DMAUDR1_Pos (13U)
|
|
|
+#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
|
|
|
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
|
|
|
+#define DAC_SR_DMAUDR2_Pos (29U)
|
|
|
+#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
|
|
|
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Digital Filter for Sigma Delta Modulators */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+
|
|
|
+/**************** DFSDM channel configuration registers ********************/
|
|
|
+
|
|
|
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
|
|
|
+#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
|
|
|
+#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
|
|
|
+#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
|
|
|
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
|
|
|
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
|
|
|
+#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
|
|
|
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
|
|
|
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
|
|
|
+#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
|
|
|
+#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
|
|
|
+#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
|
|
|
+#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
|
|
|
+#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
|
|
|
+#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
|
|
|
+#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
|
|
|
+#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
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+#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
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+#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
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+#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
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+#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
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+#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
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+#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
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+#define DFSDM_CHCFGR1_CHEN_Pos (7U)
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+#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
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+#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
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+#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
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+#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
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+#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
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+#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
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+#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
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+#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
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+#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
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+#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
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+#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
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+#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
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+#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
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+#define DFSDM_CHCFGR1_SITP_Pos (0U)
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+#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
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+#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
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+#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
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+#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
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+
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+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
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+#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
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+#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
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+#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
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+#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
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+#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
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+#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
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+
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+/****************** Bit definition for DFSDM_CHAWSCDR register *****************/
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+#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
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+#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
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+#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
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+#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
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+#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
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+#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
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+#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
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+#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
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+#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
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+#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
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+#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
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+#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
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+#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
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+#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
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+
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+/**************** Bit definition for DFSDM_CHWDATR register *******************/
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+#define DFSDM_CHWDATR_WDATA_Pos (0U)
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+#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
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+#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
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+
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+/**************** Bit definition for DFSDM_CHDATINR register *****************/
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+#define DFSDM_CHDATINR_INDAT0_Pos (0U)
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+#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
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+#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
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+#define DFSDM_CHDATINR_INDAT1_Pos (16U)
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+#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
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+#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
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+
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+/************************ DFSDM module registers ****************************/
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+
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+/******************** Bit definition for DFSDM_FLTCR1 register *******************/
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+#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
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+#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
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+#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
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+#define DFSDM_FLTCR1_FAST_Pos (29U)
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+#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
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+#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
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+#define DFSDM_FLTCR1_RCH_Pos (24U)
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+#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
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+#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
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+#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
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+#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
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+#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
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+#define DFSDM_FLTCR1_RSYNC_Pos (19U)
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+#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
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+#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
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+#define DFSDM_FLTCR1_RCONT_Pos (18U)
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+#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
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+#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
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+#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
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+#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
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+#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
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+#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
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+#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
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+#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
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+#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
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+#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
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+#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
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+#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
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+#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
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+#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
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+#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
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+#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
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+#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
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+#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
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+#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
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+#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
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+#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
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+#define DFSDM_FLTCR1_JSCAN_Pos (4U)
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+#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
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+#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
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+#define DFSDM_FLTCR1_JSYNC_Pos (3U)
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+#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
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+#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
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+#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
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+#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
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+#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
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+#define DFSDM_FLTCR1_DFEN_Pos (0U)
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+#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
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+#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
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+
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+/******************** Bit definition for DFSDM_FLTCR2 register *******************/
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+#define DFSDM_FLTCR2_AWDCH_Pos (16U)
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+#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
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+#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
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+#define DFSDM_FLTCR2_EXCH_Pos (8U)
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+#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
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+#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
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+#define DFSDM_FLTCR2_CKABIE_Pos (6U)
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+#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
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+#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
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+#define DFSDM_FLTCR2_SCDIE_Pos (5U)
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+#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
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+#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
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+#define DFSDM_FLTCR2_AWDIE_Pos (4U)
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+#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
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+#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
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+#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
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+#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
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+#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
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+#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
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+#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
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+#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
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+#define DFSDM_FLTCR2_REOCIE_Pos (1U)
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+#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
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+#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
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+#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
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+#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
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+#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
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+
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+/******************** Bit definition for DFSDM_FLTISR register *******************/
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+#define DFSDM_FLTISR_SCDF_Pos (24U)
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+#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
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+#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
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+#define DFSDM_FLTISR_CKABF_Pos (16U)
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+#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
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+#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
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+#define DFSDM_FLTISR_RCIP_Pos (14U)
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+#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
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+#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
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+#define DFSDM_FLTISR_JCIP_Pos (13U)
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+#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
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+#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
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+#define DFSDM_FLTISR_AWDF_Pos (4U)
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+#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
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+#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
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+#define DFSDM_FLTISR_ROVRF_Pos (3U)
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+#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
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+#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
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+#define DFSDM_FLTISR_JOVRF_Pos (2U)
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+#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
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+#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
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+#define DFSDM_FLTISR_REOCF_Pos (1U)
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+#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
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+#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
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+#define DFSDM_FLTISR_JEOCF_Pos (0U)
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+#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
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+#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
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+
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+/******************** Bit definition for DFSDM_FLTICR register *******************/
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+#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
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+#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
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+#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
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+#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
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+#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
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+#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
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+#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
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+#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
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|
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+#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
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|
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+#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
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|
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+#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
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|
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+#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
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|
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+
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|
|
+/******************* Bit definition for DFSDM_FLTJCHGR register ******************/
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|
|
+#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
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+#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
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|
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+#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
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+
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|
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+/******************** Bit definition for DFSDM_FLTFCR register *******************/
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+#define DFSDM_FLTFCR_FORD_Pos (29U)
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+#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
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|
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+#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
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+#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
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+#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
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+#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
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+#define DFSDM_FLTFCR_FOSR_Pos (16U)
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+#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
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+#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
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+#define DFSDM_FLTFCR_IOSR_Pos (0U)
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+#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
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+#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
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+
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+/****************** Bit definition for DFSDM_FLTJDATAR register *****************/
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+#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
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+#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
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+#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
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+#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
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+#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
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+#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
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+
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+/****************** Bit definition for DFSDM_FLTRDATAR register *****************/
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+#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
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+#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
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+#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
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+#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
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|
+#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
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|
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+#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
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|
|
+#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
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|
|
+#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
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|
|
+#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
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|
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+
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|
|
+/****************** Bit definition for DFSDM_FLTAWHTR register ******************/
|
|
|
+#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
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+#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
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+#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
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|
|
+#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
|
|
|
+#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
|
|
|
+#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
|
|
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+
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|
|
+/****************** Bit definition for DFSDM_FLTAWLTR register ******************/
|
|
|
+#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
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|
|
+#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
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|
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+#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
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|
|
+#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
|
|
|
+#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
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|
|
+#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
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|
|
+
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|
|
+/****************** Bit definition for DFSDM_FLTAWSR register ******************/
|
|
|
+#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
|
|
|
+#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
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|
|
+#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
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|
|
+#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
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|
|
+#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
|
|
|
+#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
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|
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+
|
|
|
+/****************** Bit definition for DFSDM_FLTAWCFR register *****************/
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|
|
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
|
|
|
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
|
|
|
+#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
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|
|
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
|
|
|
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
|
|
|
+#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
|
|
|
+
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|
|
+/****************** Bit definition for DFSDM_FLTEXMAX register ******************/
|
|
|
+#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
|
|
|
+#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
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|
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+#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
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|
|
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
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|
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
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|
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+#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
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+
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+/****************** Bit definition for DFSDM_FLTEXMIN register ******************/
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|
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+#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
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+#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
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+#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
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+#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
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+#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
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+#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
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+
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+/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
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|
|
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
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+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
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+#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
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+
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|
+/* Legacy Defines */
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|
|
+#define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos
|
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|
+#define DFSDM_FLTICR_CLRSCSDF_Msk DFSDM_FLTICR_CLRSCDF_Msk
|
|
|
+#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCDF
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+
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|
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+/******************************************************************************/
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|
|
+/* */
|
|
|
+/* Debug MCU */
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|
|
+/* */
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|
|
+/******************************************************************************/
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|
+
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|
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+/******************************************************************************/
|
|
|
+/* */
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|
|
+/* DCMI */
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|
|
+/* */
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|
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+/******************************************************************************/
|
|
|
+/******************** Bits definition for DCMI_CR register ******************/
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|
+#define DCMI_CR_CAPTURE_Pos (0U)
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|
+#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
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|
|
+#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
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|
|
+#define DCMI_CR_CM_Pos (1U)
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|
|
+#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
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|
|
+#define DCMI_CR_CM DCMI_CR_CM_Msk
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|
|
+#define DCMI_CR_CROP_Pos (2U)
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|
+#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
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|
|
+#define DCMI_CR_CROP DCMI_CR_CROP_Msk
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|
|
+#define DCMI_CR_JPEG_Pos (3U)
|
|
|
+#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
|
|
|
+#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
|
|
|
+#define DCMI_CR_ESS_Pos (4U)
|
|
|
+#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
|
|
|
+#define DCMI_CR_ESS DCMI_CR_ESS_Msk
|
|
|
+#define DCMI_CR_PCKPOL_Pos (5U)
|
|
|
+#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
|
|
|
+#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
|
|
|
+#define DCMI_CR_HSPOL_Pos (6U)
|
|
|
+#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
|
|
|
+#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
|
|
|
+#define DCMI_CR_VSPOL_Pos (7U)
|
|
|
+#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
|
|
+#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
|
|
+#define DCMI_CR_FCRC_0 0x00000100U
|
|
|
+#define DCMI_CR_FCRC_1 0x00000200U
|
|
|
+#define DCMI_CR_EDM_0 0x00000400U
|
|
|
+#define DCMI_CR_EDM_1 0x00000800U
|
|
|
+#define DCMI_CR_CRE_Pos (12U)
|
|
|
+#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
|
|
+#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
|
|
+#define DCMI_CR_ENABLE_Pos (14U)
|
|
|
+#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
|
|
|
+#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
|
|
|
+#define DCMI_CR_BSM_Pos (16U)
|
|
|
+#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
|
|
|
+#define DCMI_CR_BSM DCMI_CR_BSM_Msk
|
|
|
+#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
|
|
|
+#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
|
|
|
+#define DCMI_CR_OEBS_Pos (18U)
|
|
|
+#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
|
|
|
+#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
|
|
|
+#define DCMI_CR_LSM_Pos (19U)
|
|
|
+#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
|
|
|
+#define DCMI_CR_LSM DCMI_CR_LSM_Msk
|
|
|
+#define DCMI_CR_OELS_Pos (20U)
|
|
|
+#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
|
|
|
+#define DCMI_CR_OELS DCMI_CR_OELS_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for DCMI_SR register ******************/
|
|
|
+#define DCMI_SR_HSYNC_Pos (0U)
|
|
|
+#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
|
|
|
+#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
|
|
|
+#define DCMI_SR_VSYNC_Pos (1U)
|
|
|
+#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
|
|
|
+#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
|
|
|
+#define DCMI_SR_FNE_Pos (2U)
|
|
|
+#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
|
|
|
+#define DCMI_SR_FNE DCMI_SR_FNE_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for DCMI_RIS register ****************/
|
|
|
+#define DCMI_RIS_FRAME_RIS_Pos (0U)
|
|
|
+#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
|
|
|
+#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
|
|
|
+#define DCMI_RIS_OVR_RIS_Pos (1U)
|
|
|
+#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
|
|
|
+#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
|
|
|
+#define DCMI_RIS_ERR_RIS_Pos (2U)
|
|
|
+#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
|
|
|
+#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
|
|
|
+#define DCMI_RIS_VSYNC_RIS_Pos (3U)
|
|
|
+#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
|
|
|
+#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
|
|
|
+#define DCMI_RIS_LINE_RIS_Pos (4U)
|
|
|
+#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
|
|
|
+#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
|
|
|
+
|
|
|
+/* Legacy defines */
|
|
|
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
|
|
|
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
|
|
|
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
|
|
|
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
|
|
|
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
|
|
|
+
|
|
|
+/******************** Bits definition for DCMI_IER register *****************/
|
|
|
+#define DCMI_IER_FRAME_IE_Pos (0U)
|
|
|
+#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
|
|
|
+#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
|
|
|
+#define DCMI_IER_OVR_IE_Pos (1U)
|
|
|
+#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
|
|
|
+#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
|
|
|
+#define DCMI_IER_ERR_IE_Pos (2U)
|
|
|
+#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
|
|
|
+#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
|
|
|
+#define DCMI_IER_VSYNC_IE_Pos (3U)
|
|
|
+#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
|
|
|
+#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
|
|
|
+#define DCMI_IER_LINE_IE_Pos (4U)
|
|
|
+#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
|
|
|
+#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
|
|
|
+
|
|
|
+
|
|
|
+/******************** Bits definition for DCMI_MIS register *****************/
|
|
|
+#define DCMI_MIS_FRAME_MIS_Pos (0U)
|
|
|
+#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
|
|
|
+#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
|
|
|
+#define DCMI_MIS_OVR_MIS_Pos (1U)
|
|
|
+#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
|
|
|
+#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
|
|
|
+#define DCMI_MIS_ERR_MIS_Pos (2U)
|
|
|
+#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
|
|
|
+#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
|
|
|
+#define DCMI_MIS_VSYNC_MIS_Pos (3U)
|
|
|
+#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
|
|
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+#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
|
|
|
+#define DCMI_MIS_LINE_MIS_Pos (4U)
|
|
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+#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
|
|
|
+#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
|
|
|
+
|
|
|
+
|
|
|
+/******************** Bits definition for DCMI_ICR register *****************/
|
|
|
+#define DCMI_ICR_FRAME_ISC_Pos (0U)
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+#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
|
|
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+#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
|
|
|
+#define DCMI_ICR_OVR_ISC_Pos (1U)
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+#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
|
|
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+#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
|
|
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+#define DCMI_ICR_ERR_ISC_Pos (2U)
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+#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
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+#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
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|
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+#define DCMI_ICR_VSYNC_ISC_Pos (3U)
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+#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
|
|
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+#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
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|
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+#define DCMI_ICR_LINE_ISC_Pos (4U)
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+#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
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|
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+#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
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+
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+
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|
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+/******************** Bits definition for DCMI_ESCR register ******************/
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|
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+#define DCMI_ESCR_FSC_Pos (0U)
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|
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+#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
|
|
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+#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
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|
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+#define DCMI_ESCR_LSC_Pos (8U)
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+#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
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+#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
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+#define DCMI_ESCR_LEC_Pos (16U)
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+#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
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|
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+#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
|
|
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+#define DCMI_ESCR_FEC_Pos (24U)
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+#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
|
|
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+#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
|
|
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+
|
|
|
+/******************** Bits definition for DCMI_ESUR register ******************/
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|
|
+#define DCMI_ESUR_FSU_Pos (0U)
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|
|
+#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
|
|
|
+#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
|
|
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+#define DCMI_ESUR_LSU_Pos (8U)
|
|
|
+#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
|
|
|
+#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
|
|
|
+#define DCMI_ESUR_LEU_Pos (16U)
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|
|
+#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
|
|
|
+#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
|
|
|
+#define DCMI_ESUR_FEU_Pos (24U)
|
|
|
+#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
|
|
|
+#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
|
|
|
+
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|
|
+/******************** Bits definition for DCMI_CWSTRT register ******************/
|
|
|
+#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
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|
+#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
|
|
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+#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
|
|
|
+#define DCMI_CWSTRT_VST_Pos (16U)
|
|
|
+#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
|
|
|
+#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for DCMI_CWSIZE register ******************/
|
|
|
+#define DCMI_CWSIZE_CAPCNT_Pos (0U)
|
|
|
+#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
|
|
|
+#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
|
|
|
+#define DCMI_CWSIZE_VLINE_Pos (16U)
|
|
|
+#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
|
|
|
+#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for DCMI_DR register ******************/
|
|
|
+#define DCMI_DR_BYTE0_Pos (0U)
|
|
|
+#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
|
|
|
+#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
|
|
|
+#define DCMI_DR_BYTE1_Pos (8U)
|
|
|
+#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
|
|
|
+#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
|
|
|
+#define DCMI_DR_BYTE2_Pos (16U)
|
|
|
+#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
|
|
|
+#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
|
|
|
+#define DCMI_DR_BYTE3_Pos (24U)
|
|
|
+#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
|
|
|
+#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* DMA Controller */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************** Bits definition for DMA_SxCR register *****************/
|
|
|
+#define DMA_SxCR_CHSEL_Pos (25U)
|
|
|
+#define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
|
|
|
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
|
|
|
+#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
|
|
|
+#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
|
|
|
+#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
|
|
|
+#define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
|
|
|
+#define DMA_SxCR_MBURST_Pos (23U)
|
|
|
+#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
|
|
|
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
|
|
|
+#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
|
|
|
+#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
|
|
|
+#define DMA_SxCR_PBURST_Pos (21U)
|
|
|
+#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
|
|
|
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
|
|
|
+#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
|
|
|
+#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
|
|
|
+#define DMA_SxCR_CT_Pos (19U)
|
|
|
+#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
|
|
|
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
|
|
|
+#define DMA_SxCR_DBM_Pos (18U)
|
|
|
+#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
|
|
|
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
|
|
|
+#define DMA_SxCR_PL_Pos (16U)
|
|
|
+#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
|
|
|
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
|
|
|
+#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
|
|
|
+#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
|
|
|
+#define DMA_SxCR_PINCOS_Pos (15U)
|
|
|
+#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
|
|
|
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
|
|
|
+#define DMA_SxCR_MSIZE_Pos (13U)
|
|
|
+#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
|
|
|
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
|
|
|
+#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
|
|
|
+#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
|
|
|
+#define DMA_SxCR_PSIZE_Pos (11U)
|
|
|
+#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
|
|
|
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
|
|
|
+#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
|
|
|
+#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
|
|
|
+#define DMA_SxCR_MINC_Pos (10U)
|
|
|
+#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
|
|
|
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
|
|
|
+#define DMA_SxCR_PINC_Pos (9U)
|
|
|
+#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
|
|
|
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
|
|
|
+#define DMA_SxCR_CIRC_Pos (8U)
|
|
|
+#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
|
|
|
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
|
|
|
+#define DMA_SxCR_DIR_Pos (6U)
|
|
|
+#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
|
|
|
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
|
|
|
+#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
|
|
|
+#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
|
|
|
+#define DMA_SxCR_PFCTRL_Pos (5U)
|
|
|
+#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
|
|
|
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
|
|
|
+#define DMA_SxCR_TCIE_Pos (4U)
|
|
|
+#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
|
|
|
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
|
|
|
+#define DMA_SxCR_HTIE_Pos (3U)
|
|
|
+#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
|
|
|
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
|
|
|
+#define DMA_SxCR_TEIE_Pos (2U)
|
|
|
+#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
|
|
|
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
|
|
|
+#define DMA_SxCR_DMEIE_Pos (1U)
|
|
|
+#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
|
|
|
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
|
|
|
+#define DMA_SxCR_EN_Pos (0U)
|
|
|
+#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
|
|
|
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for DMA_SxCNDTR register **************/
|
|
|
+#define DMA_SxNDT_Pos (0U)
|
|
|
+#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
|
|
|
+#define DMA_SxNDT DMA_SxNDT_Msk
|
|
|
+#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
|
|
|
+#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
|
|
|
+#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
|
|
|
+#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
|
|
|
+#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
|
|
|
+#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
|
|
|
+#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
|
|
|
+#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
|
|
|
+#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
|
|
|
+#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
|
|
|
+#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
|
|
|
+#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
|
|
|
+#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
|
|
|
+#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
|
|
|
+#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
|
|
|
+#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
|
|
|
+
|
|
|
+/******************** Bits definition for DMA_SxFCR register ****************/
|
|
|
+#define DMA_SxFCR_FEIE_Pos (7U)
|
|
|
+#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
|
|
|
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
|
|
|
+#define DMA_SxFCR_FS_Pos (3U)
|
|
|
+#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
|
|
|
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
|
|
|
+#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
|
|
|
+#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
|
|
|
+#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
|
|
|
+#define DMA_SxFCR_DMDIS_Pos (2U)
|
|
|
+#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
|
|
|
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
|
|
|
+#define DMA_SxFCR_FTH_Pos (0U)
|
|
|
+#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
|
|
|
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
|
|
|
+#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
|
|
|
+#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
|
|
|
+
|
|
|
+/******************** Bits definition for DMA_LISR register *****************/
|
|
|
+#define DMA_LISR_TCIF3_Pos (27U)
|
|
|
+#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
|
|
|
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
|
|
|
+#define DMA_LISR_HTIF3_Pos (26U)
|
|
|
+#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
|
|
|
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
|
|
|
+#define DMA_LISR_TEIF3_Pos (25U)
|
|
|
+#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
|
|
|
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
|
|
|
+#define DMA_LISR_DMEIF3_Pos (24U)
|
|
|
+#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
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+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
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+#define DMA_LISR_FEIF3_Pos (22U)
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+#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
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+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
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+#define DMA_LISR_TCIF2_Pos (21U)
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+#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
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+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
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+#define DMA_LISR_HTIF2_Pos (20U)
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+#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
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+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
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+#define DMA_LISR_TEIF2_Pos (19U)
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+#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
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+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
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+#define DMA_LISR_DMEIF2_Pos (18U)
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+#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
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+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
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+#define DMA_LISR_FEIF2_Pos (16U)
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+#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
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+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
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+#define DMA_LISR_TCIF1_Pos (11U)
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+#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
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+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
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+#define DMA_LISR_HTIF1_Pos (10U)
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+#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
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+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
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+#define DMA_LISR_TEIF1_Pos (9U)
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+#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
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+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
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+#define DMA_LISR_DMEIF1_Pos (8U)
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+#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
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+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
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+#define DMA_LISR_FEIF1_Pos (6U)
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+#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
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+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
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+#define DMA_LISR_TCIF0_Pos (5U)
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+#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
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+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
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+#define DMA_LISR_HTIF0_Pos (4U)
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+#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
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+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
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+#define DMA_LISR_TEIF0_Pos (3U)
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+#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
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+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
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+#define DMA_LISR_DMEIF0_Pos (2U)
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+#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
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+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
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+#define DMA_LISR_FEIF0_Pos (0U)
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+#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
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+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
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+
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+/******************** Bits definition for DMA_HISR register *****************/
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+#define DMA_HISR_TCIF7_Pos (27U)
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+#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
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+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
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+#define DMA_HISR_HTIF7_Pos (26U)
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+#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
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+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
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+#define DMA_HISR_TEIF7_Pos (25U)
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+#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
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+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
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+#define DMA_HISR_DMEIF7_Pos (24U)
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+#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
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+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
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+#define DMA_HISR_FEIF7_Pos (22U)
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+#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
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+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
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+#define DMA_HISR_TCIF6_Pos (21U)
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+#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
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+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
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+#define DMA_HISR_HTIF6_Pos (20U)
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+#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
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+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
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+#define DMA_HISR_TEIF6_Pos (19U)
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+#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
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+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
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+#define DMA_HISR_DMEIF6_Pos (18U)
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+#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
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+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
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+#define DMA_HISR_FEIF6_Pos (16U)
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+#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
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+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
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+#define DMA_HISR_TCIF5_Pos (11U)
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+#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
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+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
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+#define DMA_HISR_HTIF5_Pos (10U)
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+#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
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+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
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+#define DMA_HISR_TEIF5_Pos (9U)
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+#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
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+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
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+#define DMA_HISR_DMEIF5_Pos (8U)
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+#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
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+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
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+#define DMA_HISR_FEIF5_Pos (6U)
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+#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
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+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
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+#define DMA_HISR_TCIF4_Pos (5U)
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+#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
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+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
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+#define DMA_HISR_HTIF4_Pos (4U)
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+#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
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+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
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+#define DMA_HISR_TEIF4_Pos (3U)
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+#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
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+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
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+#define DMA_HISR_DMEIF4_Pos (2U)
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+#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
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+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
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+#define DMA_HISR_FEIF4_Pos (0U)
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+#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
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+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
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+
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+/******************** Bits definition for DMA_LIFCR register ****************/
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+#define DMA_LIFCR_CTCIF3_Pos (27U)
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+#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
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+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
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+#define DMA_LIFCR_CHTIF3_Pos (26U)
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+#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
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+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
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+#define DMA_LIFCR_CTEIF3_Pos (25U)
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+#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
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+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
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+#define DMA_LIFCR_CDMEIF3_Pos (24U)
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+#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
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+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
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+#define DMA_LIFCR_CFEIF3_Pos (22U)
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+#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
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+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
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+#define DMA_LIFCR_CTCIF2_Pos (21U)
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+#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
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+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
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+#define DMA_LIFCR_CHTIF2_Pos (20U)
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+#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
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+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
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+#define DMA_LIFCR_CTEIF2_Pos (19U)
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+#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
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+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
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+#define DMA_LIFCR_CDMEIF2_Pos (18U)
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+#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
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+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
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+#define DMA_LIFCR_CFEIF2_Pos (16U)
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+#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
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+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
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+#define DMA_LIFCR_CTCIF1_Pos (11U)
|
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+#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
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|
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
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+#define DMA_LIFCR_CHTIF1_Pos (10U)
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+#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
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+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
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+#define DMA_LIFCR_CTEIF1_Pos (9U)
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|
+#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
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+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
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+#define DMA_LIFCR_CDMEIF1_Pos (8U)
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|
+#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
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+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
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+#define DMA_LIFCR_CFEIF1_Pos (6U)
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|
+#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
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+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
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+#define DMA_LIFCR_CTCIF0_Pos (5U)
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|
+#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
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+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
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+#define DMA_LIFCR_CHTIF0_Pos (4U)
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+#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
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+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
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+#define DMA_LIFCR_CTEIF0_Pos (3U)
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|
+#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
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+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
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+#define DMA_LIFCR_CDMEIF0_Pos (2U)
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|
+#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
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+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
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+#define DMA_LIFCR_CFEIF0_Pos (0U)
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|
+#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
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+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
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+
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|
+/******************** Bits definition for DMA_HIFCR register ****************/
|
|
|
+#define DMA_HIFCR_CTCIF7_Pos (27U)
|
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|
+#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
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|
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
|
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|
+#define DMA_HIFCR_CHTIF7_Pos (26U)
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+#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
|
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|
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
|
|
|
+#define DMA_HIFCR_CTEIF7_Pos (25U)
|
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|
+#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
|
|
|
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
|
|
|
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
|
|
|
+#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
|
|
|
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
|
|
|
+#define DMA_HIFCR_CFEIF7_Pos (22U)
|
|
|
+#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
|
|
|
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
|
|
|
+#define DMA_HIFCR_CTCIF6_Pos (21U)
|
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|
+#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
|
|
|
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
|
|
|
+#define DMA_HIFCR_CHTIF6_Pos (20U)
|
|
|
+#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
|
|
|
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
|
|
|
+#define DMA_HIFCR_CTEIF6_Pos (19U)
|
|
|
+#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
|
|
|
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
|
|
|
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
|
|
|
+#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
|
|
|
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
|
|
|
+#define DMA_HIFCR_CFEIF6_Pos (16U)
|
|
|
+#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
|
|
|
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
|
|
|
+#define DMA_HIFCR_CTCIF5_Pos (11U)
|
|
|
+#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
|
|
|
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
|
|
|
+#define DMA_HIFCR_CHTIF5_Pos (10U)
|
|
|
+#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
|
|
|
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
|
|
|
+#define DMA_HIFCR_CTEIF5_Pos (9U)
|
|
|
+#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
|
|
|
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
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|
|
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
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|
|
+#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
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|
|
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
|
|
|
+#define DMA_HIFCR_CFEIF5_Pos (6U)
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|
|
+#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
|
|
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+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
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|
|
+#define DMA_HIFCR_CTCIF4_Pos (5U)
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|
|
+#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
|
|
|
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
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|
|
+#define DMA_HIFCR_CHTIF4_Pos (4U)
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|
|
+#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
|
|
|
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
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|
|
+#define DMA_HIFCR_CTEIF4_Pos (3U)
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|
|
+#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
|
|
|
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
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|
|
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
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|
|
+#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
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|
|
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
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|
|
+#define DMA_HIFCR_CFEIF4_Pos (0U)
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|
+#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
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|
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+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
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|
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+
|
|
|
+/****************** Bit definition for DMA_SxPAR register ********************/
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|
|
+#define DMA_SxPAR_PA_Pos (0U)
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|
|
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
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|
|
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
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+
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|
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+/****************** Bit definition for DMA_SxM0AR register ********************/
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|
|
+#define DMA_SxM0AR_M0A_Pos (0U)
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|
|
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
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|
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+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
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+
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|
|
+/****************** Bit definition for DMA_SxM1AR register ********************/
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+#define DMA_SxM1AR_M1A_Pos (0U)
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+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
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|
|
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
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+
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|
|
+/******************************************************************************/
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|
|
+/* */
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|
|
+/* AHB Master DMA2D Controller (DMA2D) */
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+/* */
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|
|
+/******************************************************************************/
|
|
|
+/*
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|
|
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
|
|
+ */
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|
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+#define DMA2D_ALPHA_INV_RB_SWAP_SUPPORT
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|
+/******************** Bit definition for DMA2D_CR register ******************/
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+
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|
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+#define DMA2D_CR_START_Pos (0U)
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+#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
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+#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
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|
|
+#define DMA2D_CR_SUSP_Pos (1U)
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|
+#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
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+#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
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|
|
+#define DMA2D_CR_ABORT_Pos (2U)
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|
+#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
|
|
|
+#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
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|
|
+#define DMA2D_CR_TEIE_Pos (8U)
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|
|
+#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
|
|
|
+#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
|
|
|
+#define DMA2D_CR_TCIE_Pos (9U)
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|
+#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
|
|
|
+#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
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|
|
+#define DMA2D_CR_TWIE_Pos (10U)
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|
|
+#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
|
|
|
+#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
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|
|
+#define DMA2D_CR_CAEIE_Pos (11U)
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|
|
+#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
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|
|
+#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
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|
|
+#define DMA2D_CR_CTCIE_Pos (12U)
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|
|
+#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
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|
|
+#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
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|
|
+#define DMA2D_CR_CEIE_Pos (13U)
|
|
|
+#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
|
|
|
+#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
|
|
|
+#define DMA2D_CR_MODE_Pos (16U)
|
|
|
+#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
|
|
|
+#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
|
|
|
+#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
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|
|
+#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
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|
|
+
|
|
|
+/******************** Bit definition for DMA2D_ISR register *****************/
|
|
|
+
|
|
|
+#define DMA2D_ISR_TEIF_Pos (0U)
|
|
|
+#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
|
|
|
+#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
|
|
|
+#define DMA2D_ISR_TCIF_Pos (1U)
|
|
|
+#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
|
|
|
+#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
|
|
|
+#define DMA2D_ISR_TWIF_Pos (2U)
|
|
|
+#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
|
|
|
+#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
|
|
|
+#define DMA2D_ISR_CAEIF_Pos (3U)
|
|
|
+#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
|
|
|
+#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
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|
|
+#define DMA2D_ISR_CTCIF_Pos (4U)
|
|
|
+#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
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|
|
+#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
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|
|
+#define DMA2D_ISR_CEIF_Pos (5U)
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|
+#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
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|
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+#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
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+
|
|
|
+/******************** Bit definition for DMA2D_IFCR register ****************/
|
|
|
+
|
|
|
+#define DMA2D_IFCR_CTEIF_Pos (0U)
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|
+#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
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|
|
+#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
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|
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+#define DMA2D_IFCR_CTCIF_Pos (1U)
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|
+#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
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|
+#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
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|
|
+#define DMA2D_IFCR_CTWIF_Pos (2U)
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|
+#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
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|
|
+#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
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|
+#define DMA2D_IFCR_CAECIF_Pos (3U)
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|
+#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
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|
+#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
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|
|
+#define DMA2D_IFCR_CCTCIF_Pos (4U)
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|
+#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
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|
|
+#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
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|
|
+#define DMA2D_IFCR_CCEIF_Pos (5U)
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|
|
+#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
|
|
|
+#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
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|
|
+
|
|
|
+/* Legacy defines */
|
|
|
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
|
|
|
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
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|
|
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
|
|
|
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
|
|
|
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
|
|
|
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
|
|
|
+
|
|
|
+/******************** Bit definition for DMA2D_FGMAR register ***************/
|
|
|
+
|
|
|
+#define DMA2D_FGMAR_MA_Pos (0U)
|
|
|
+#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
|
|
|
+
|
|
|
+/******************** Bit definition for DMA2D_FGOR register ****************/
|
|
|
+
|
|
|
+#define DMA2D_FGOR_LO_Pos (0U)
|
|
|
+#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
|
|
|
+#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
|
|
|
+
|
|
|
+/******************** Bit definition for DMA2D_BGMAR register ***************/
|
|
|
+
|
|
|
+#define DMA2D_BGMAR_MA_Pos (0U)
|
|
|
+#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
|
|
|
+
|
|
|
+/******************** Bit definition for DMA2D_BGOR register ****************/
|
|
|
+
|
|
|
+#define DMA2D_BGOR_LO_Pos (0U)
|
|
|
+#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
|
|
|
+#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
|
|
|
+
|
|
|
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
|
|
|
+
|
|
|
+#define DMA2D_FGPFCCR_CM_Pos (0U)
|
|
|
+#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
|
|
|
+#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
|
|
|
+#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
|
|
|
+#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
|
|
|
+#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
|
|
|
+#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
|
|
|
+#define DMA2D_FGPFCCR_CCM_Pos (4U)
|
|
|
+#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
|
|
|
+#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
|
|
|
+#define DMA2D_FGPFCCR_START_Pos (5U)
|
|
|
+#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
|
|
|
+#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
|
|
|
+#define DMA2D_FGPFCCR_CS_Pos (8U)
|
|
|
+#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
|
|
|
+#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
|
|
|
+#define DMA2D_FGPFCCR_AM_Pos (16U)
|
|
|
+#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
|
|
|
+#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
|
|
|
+#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
|
|
|
+#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
|
|
|
+#define DMA2D_FGPFCCR_AI_Pos (20U)
|
|
|
+#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
|
|
|
+#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
|
|
|
+#define DMA2D_FGPFCCR_RBS_Pos (21U)
|
|
|
+#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
|
|
|
+#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
|
|
|
+#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
|
|
|
+#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
|
|
|
+#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
|
|
|
+
|
|
|
+/******************** Bit definition for DMA2D_FGCOLR register **************/
|
|
|
+
|
|
|
+#define DMA2D_FGCOLR_BLUE_Pos (0U)
|
|
|
+#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
|
|
|
+#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
|
|
|
+#define DMA2D_FGCOLR_GREEN_Pos (8U)
|
|
|
+#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
|
|
|
+#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
|
|
|
+#define DMA2D_FGCOLR_RED_Pos (16U)
|
|
|
+#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
|
|
|
+#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
|
|
|
+
|
|
|
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
|
|
|
+
|
|
|
+#define DMA2D_BGPFCCR_CM_Pos (0U)
|
|
|
+#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
|
|
|
+#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
|
|
|
+#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
|
|
|
+#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
|
|
|
+#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
|
|
|
+#define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
|
|
|
+#define DMA2D_BGPFCCR_CCM_Pos (4U)
|
|
|
+#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
|
|
|
+#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
|
|
|
+#define DMA2D_BGPFCCR_START_Pos (5U)
|
|
|
+#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
|
|
|
+#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
|
|
|
+#define DMA2D_BGPFCCR_CS_Pos (8U)
|
|
|
+#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
|
|
|
+#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
|
|
|
+#define DMA2D_BGPFCCR_AM_Pos (16U)
|
|
|
+#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
|
|
|
+#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
|
|
|
+#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
|
|
|
+#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
|
|
|
+#define DMA2D_BGPFCCR_AI_Pos (20U)
|
|
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+#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
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|
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+#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
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|
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+#define DMA2D_BGPFCCR_RBS_Pos (21U)
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+#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
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|
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+#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
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|
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+#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
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+#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
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+#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
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+
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|
|
+/******************** Bit definition for DMA2D_BGCOLR register **************/
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+
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+#define DMA2D_BGCOLR_BLUE_Pos (0U)
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+#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
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+#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
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+#define DMA2D_BGCOLR_GREEN_Pos (8U)
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+#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
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+#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
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+#define DMA2D_BGCOLR_RED_Pos (16U)
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+#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
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+#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
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+
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|
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+/******************** Bit definition for DMA2D_FGCMAR register **************/
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+
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+#define DMA2D_FGCMAR_MA_Pos (0U)
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+#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
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+#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
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+
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+/******************** Bit definition for DMA2D_BGCMAR register **************/
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+
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+#define DMA2D_BGCMAR_MA_Pos (0U)
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+#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
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+#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
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+
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+/******************** Bit definition for DMA2D_OPFCCR register **************/
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+
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+#define DMA2D_OPFCCR_CM_Pos (0U)
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+#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
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+#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
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+#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
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+#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
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+#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
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+#define DMA2D_OPFCCR_AI_Pos (20U)
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+#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
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+#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
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+#define DMA2D_OPFCCR_RBS_Pos (21U)
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+#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
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+#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
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+
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|
|
+/******************** Bit definition for DMA2D_OCOLR register ***************/
|
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+
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|
|
+/*!<Mode_ARGB8888/RGB888 */
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+
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|
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+#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
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+#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
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+#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
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+#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
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+
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|
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+/*!<Mode_RGB565 */
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+#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
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+#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
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|
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+#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
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|
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+
|
|
|
+/*!<Mode_ARGB1555 */
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|
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+#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
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|
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+#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
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+#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
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|
|
+#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
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+
|
|
|
+/*!<Mode_ARGB4444 */
|
|
|
+#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
|
|
|
+#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
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|
|
+#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
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|
|
+#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
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+
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|
|
+/******************** Bit definition for DMA2D_OMAR register ****************/
|
|
|
+
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|
|
+#define DMA2D_OMAR_MA_Pos (0U)
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|
|
+#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
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|
|
+#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
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|
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+
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|
|
+/******************** Bit definition for DMA2D_OOR register *****************/
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|
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+
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|
|
+#define DMA2D_OOR_LO_Pos (0U)
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|
+#define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
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|
|
+#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
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+
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|
|
+/******************** Bit definition for DMA2D_NLR register *****************/
|
|
|
+
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|
|
+#define DMA2D_NLR_NL_Pos (0U)
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|
|
+#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
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|
|
+#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
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|
|
+#define DMA2D_NLR_PL_Pos (16U)
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|
|
+#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
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|
|
+#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
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|
+
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|
|
+/******************** Bit definition for DMA2D_LWR register *****************/
|
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+
|
|
|
+#define DMA2D_LWR_LW_Pos (0U)
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|
+#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
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|
|
+#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
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|
|
+
|
|
|
+/******************** Bit definition for DMA2D_AMTCR register ***************/
|
|
|
+
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|
|
+#define DMA2D_AMTCR_EN_Pos (0U)
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|
|
+#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
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|
|
+#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
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|
|
+#define DMA2D_AMTCR_DT_Pos (8U)
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|
|
+#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
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|
|
+#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
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+
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+
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|
|
+/******************** Bit definition for DMA2D_FGCLUT register **************/
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+
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|
|
+/******************** Bit definition for DMA2D_BGCLUT register **************/
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|
+
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|
|
+/******************************************************************************/
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|
|
+/* */
|
|
|
+/* External Interrupt/Event Controller */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************* Bit definition for EXTI_IMR register *******************/
|
|
|
+#define EXTI_IMR_MR0_Pos (0U)
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|
+#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
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+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
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|
+#define EXTI_IMR_MR1_Pos (1U)
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|
+#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
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+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
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|
+#define EXTI_IMR_MR2_Pos (2U)
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|
+#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
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+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
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+#define EXTI_IMR_MR3_Pos (3U)
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|
+#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
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|
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+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
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+#define EXTI_IMR_MR4_Pos (4U)
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|
+#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
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|
|
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
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|
+#define EXTI_IMR_MR5_Pos (5U)
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|
+#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
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|
|
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
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|
|
+#define EXTI_IMR_MR6_Pos (6U)
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|
|
+#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
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|
|
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
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|
+#define EXTI_IMR_MR7_Pos (7U)
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|
+#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
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|
|
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
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|
|
+#define EXTI_IMR_MR8_Pos (8U)
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|
|
+#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
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|
|
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
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|
|
+#define EXTI_IMR_MR9_Pos (9U)
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|
|
+#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
|
|
|
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
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|
|
+#define EXTI_IMR_MR10_Pos (10U)
|
|
|
+#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
|
|
|
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
|
|
|
+#define EXTI_IMR_MR11_Pos (11U)
|
|
|
+#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
|
|
|
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
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|
|
+#define EXTI_IMR_MR12_Pos (12U)
|
|
|
+#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
|
|
|
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
|
|
|
+#define EXTI_IMR_MR13_Pos (13U)
|
|
|
+#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
|
|
|
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
|
|
|
+#define EXTI_IMR_MR14_Pos (14U)
|
|
|
+#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
|
|
|
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
|
|
|
+#define EXTI_IMR_MR15_Pos (15U)
|
|
|
+#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
|
|
|
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
|
|
|
+#define EXTI_IMR_MR16_Pos (16U)
|
|
|
+#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
|
|
|
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
|
|
|
+#define EXTI_IMR_MR17_Pos (17U)
|
|
|
+#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
|
|
|
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
|
|
|
+#define EXTI_IMR_MR18_Pos (18U)
|
|
|
+#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
|
|
|
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
|
|
|
+#define EXTI_IMR_MR19_Pos (19U)
|
|
|
+#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
|
|
|
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
|
|
|
+#define EXTI_IMR_MR20_Pos (20U)
|
|
|
+#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
|
|
|
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
|
|
|
+#define EXTI_IMR_MR21_Pos (21U)
|
|
|
+#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
|
|
|
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
|
|
|
+#define EXTI_IMR_MR22_Pos (22U)
|
|
|
+#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
|
|
|
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
|
|
|
+#define EXTI_IMR_MR23_Pos (23U)
|
|
|
+#define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
|
|
|
+#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
|
|
|
+#define EXTI_IMR_MR24_Pos (24U)
|
|
|
+#define EXTI_IMR_MR24_Msk (0x1UL << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */
|
|
|
+#define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */
|
|
|
+
|
|
|
+/* Reference Defines */
|
|
|
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
|
|
|
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
|
|
|
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
|
|
|
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
|
|
|
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
|
|
|
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
|
|
|
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
|
|
|
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
|
|
|
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
|
|
|
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
|
|
|
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
|
|
|
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
|
|
|
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
|
|
|
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
|
|
|
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
|
|
|
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
|
|
|
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
|
|
|
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
|
|
|
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
|
|
|
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
|
|
|
+#define EXTI_IMR_IM20 EXTI_IMR_MR20
|
|
|
+#define EXTI_IMR_IM21 EXTI_IMR_MR21
|
|
|
+#define EXTI_IMR_IM22 EXTI_IMR_MR22
|
|
|
+#define EXTI_IMR_IM23 EXTI_IMR_MR23
|
|
|
+#define EXTI_IMR_IM24 EXTI_IMR_MR24
|
|
|
+
|
|
|
+#define EXTI_IMR_IM_Pos (0U)
|
|
|
+#define EXTI_IMR_IM_Msk (0x1FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x01FFFFFF */
|
|
|
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
|
|
|
+
|
|
|
+/******************* Bit definition for EXTI_EMR register *******************/
|
|
|
+#define EXTI_EMR_MR0_Pos (0U)
|
|
|
+#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
|
|
|
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
|
|
|
+#define EXTI_EMR_MR1_Pos (1U)
|
|
|
+#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
|
|
|
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
|
|
|
+#define EXTI_EMR_MR2_Pos (2U)
|
|
|
+#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
|
|
|
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
|
|
|
+#define EXTI_EMR_MR3_Pos (3U)
|
|
|
+#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
|
|
|
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
|
|
|
+#define EXTI_EMR_MR4_Pos (4U)
|
|
|
+#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
|
|
|
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
|
|
|
+#define EXTI_EMR_MR5_Pos (5U)
|
|
|
+#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
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+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
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+#define EXTI_EMR_MR6_Pos (6U)
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+#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
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+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
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+#define EXTI_EMR_MR7_Pos (7U)
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+#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
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+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
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+#define EXTI_EMR_MR8_Pos (8U)
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+#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
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+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
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+#define EXTI_EMR_MR9_Pos (9U)
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+#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
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+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
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+#define EXTI_EMR_MR10_Pos (10U)
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+#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
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+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
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+#define EXTI_EMR_MR11_Pos (11U)
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+#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
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+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
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+#define EXTI_EMR_MR12_Pos (12U)
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+#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
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+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
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+#define EXTI_EMR_MR13_Pos (13U)
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+#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
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+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
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+#define EXTI_EMR_MR14_Pos (14U)
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+#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
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+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
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+#define EXTI_EMR_MR15_Pos (15U)
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+#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
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+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
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+#define EXTI_EMR_MR16_Pos (16U)
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+#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
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+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
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+#define EXTI_EMR_MR17_Pos (17U)
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+#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
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+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
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+#define EXTI_EMR_MR18_Pos (18U)
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+#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
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+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
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+#define EXTI_EMR_MR19_Pos (19U)
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+#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
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+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
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+#define EXTI_EMR_MR20_Pos (20U)
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+#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
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+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
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+#define EXTI_EMR_MR21_Pos (21U)
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+#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
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+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
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+#define EXTI_EMR_MR22_Pos (22U)
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+#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
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+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
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+#define EXTI_EMR_MR23_Pos (23U)
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+#define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
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+#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
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+#define EXTI_EMR_MR24_Pos (24U)
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+#define EXTI_EMR_MR24_Msk (0x1UL << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */
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+#define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */
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+
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+/* Reference Defines */
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+#define EXTI_EMR_EM0 EXTI_EMR_MR0
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+#define EXTI_EMR_EM1 EXTI_EMR_MR1
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+#define EXTI_EMR_EM2 EXTI_EMR_MR2
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+#define EXTI_EMR_EM3 EXTI_EMR_MR3
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+#define EXTI_EMR_EM4 EXTI_EMR_MR4
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+#define EXTI_EMR_EM5 EXTI_EMR_MR5
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+#define EXTI_EMR_EM6 EXTI_EMR_MR6
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+#define EXTI_EMR_EM7 EXTI_EMR_MR7
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+#define EXTI_EMR_EM8 EXTI_EMR_MR8
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+#define EXTI_EMR_EM9 EXTI_EMR_MR9
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+#define EXTI_EMR_EM10 EXTI_EMR_MR10
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+#define EXTI_EMR_EM11 EXTI_EMR_MR11
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+#define EXTI_EMR_EM12 EXTI_EMR_MR12
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+#define EXTI_EMR_EM13 EXTI_EMR_MR13
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+#define EXTI_EMR_EM14 EXTI_EMR_MR14
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+#define EXTI_EMR_EM15 EXTI_EMR_MR15
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+#define EXTI_EMR_EM16 EXTI_EMR_MR16
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+#define EXTI_EMR_EM17 EXTI_EMR_MR17
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+#define EXTI_EMR_EM18 EXTI_EMR_MR18
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+#define EXTI_EMR_EM19 EXTI_EMR_MR19
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+#define EXTI_EMR_EM20 EXTI_EMR_MR20
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+#define EXTI_EMR_EM21 EXTI_EMR_MR21
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+#define EXTI_EMR_EM22 EXTI_EMR_MR22
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+#define EXTI_EMR_EM23 EXTI_EMR_MR23
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+#define EXTI_EMR_EM24 EXTI_EMR_MR24
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+
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+
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+/****************** Bit definition for EXTI_RTSR register *******************/
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+#define EXTI_RTSR_TR0_Pos (0U)
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+#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
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+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
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+#define EXTI_RTSR_TR1_Pos (1U)
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+#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
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+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
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+#define EXTI_RTSR_TR2_Pos (2U)
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+#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
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+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
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+#define EXTI_RTSR_TR3_Pos (3U)
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+#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
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+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
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+#define EXTI_RTSR_TR4_Pos (4U)
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+#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
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+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
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+#define EXTI_RTSR_TR5_Pos (5U)
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+#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
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+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
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+#define EXTI_RTSR_TR6_Pos (6U)
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+#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
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+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
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+#define EXTI_RTSR_TR7_Pos (7U)
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+#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
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+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
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+#define EXTI_RTSR_TR8_Pos (8U)
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+#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
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+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
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+#define EXTI_RTSR_TR9_Pos (9U)
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+#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
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+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
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+#define EXTI_RTSR_TR10_Pos (10U)
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+#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
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+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
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+#define EXTI_RTSR_TR11_Pos (11U)
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+#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
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+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
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+#define EXTI_RTSR_TR12_Pos (12U)
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+#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
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+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
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+#define EXTI_RTSR_TR13_Pos (13U)
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+#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
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+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
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+#define EXTI_RTSR_TR14_Pos (14U)
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+#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
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+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
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+#define EXTI_RTSR_TR15_Pos (15U)
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+#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
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+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
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+#define EXTI_RTSR_TR16_Pos (16U)
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+#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
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+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
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+#define EXTI_RTSR_TR17_Pos (17U)
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+#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
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+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
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+#define EXTI_RTSR_TR18_Pos (18U)
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+#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
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+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
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+#define EXTI_RTSR_TR19_Pos (19U)
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+#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
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+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
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+#define EXTI_RTSR_TR20_Pos (20U)
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+#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
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+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
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+#define EXTI_RTSR_TR21_Pos (21U)
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+#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
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+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
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+#define EXTI_RTSR_TR22_Pos (22U)
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+#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
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+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
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+#define EXTI_RTSR_TR23_Pos (23U)
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+#define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
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+#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
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+#define EXTI_RTSR_TR24_Pos (24U)
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+#define EXTI_RTSR_TR24_Msk (0x1UL << EXTI_RTSR_TR24_Pos) /*!< 0x01000000 */
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+#define EXTI_RTSR_TR24 EXTI_RTSR_TR24_Msk /*!< Rising trigger event configuration bit of line 24 */
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+
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+/****************** Bit definition for EXTI_FTSR register *******************/
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+#define EXTI_FTSR_TR0_Pos (0U)
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+#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
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+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
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+#define EXTI_FTSR_TR1_Pos (1U)
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+#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
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+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
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+#define EXTI_FTSR_TR2_Pos (2U)
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+#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
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+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
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+#define EXTI_FTSR_TR3_Pos (3U)
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+#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
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+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
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+#define EXTI_FTSR_TR4_Pos (4U)
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+#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
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+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
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+#define EXTI_FTSR_TR5_Pos (5U)
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|
|
+#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
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+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
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+#define EXTI_FTSR_TR6_Pos (6U)
|
|
|
+#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
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+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
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+#define EXTI_FTSR_TR7_Pos (7U)
|
|
|
+#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
|
|
|
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
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|
+#define EXTI_FTSR_TR8_Pos (8U)
|
|
|
+#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
|
|
|
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
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|
+#define EXTI_FTSR_TR9_Pos (9U)
|
|
|
+#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
|
|
|
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
|
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|
+#define EXTI_FTSR_TR10_Pos (10U)
|
|
|
+#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
|
|
|
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
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|
+#define EXTI_FTSR_TR11_Pos (11U)
|
|
|
+#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
|
|
|
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
|
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|
+#define EXTI_FTSR_TR12_Pos (12U)
|
|
|
+#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
|
|
|
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
|
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|
+#define EXTI_FTSR_TR13_Pos (13U)
|
|
|
+#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
|
|
|
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
|
|
|
+#define EXTI_FTSR_TR14_Pos (14U)
|
|
|
+#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
|
|
|
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
|
|
|
+#define EXTI_FTSR_TR15_Pos (15U)
|
|
|
+#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
|
|
|
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
|
|
|
+#define EXTI_FTSR_TR16_Pos (16U)
|
|
|
+#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
|
|
|
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
|
|
|
+#define EXTI_FTSR_TR17_Pos (17U)
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+#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
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|
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+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
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|
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+#define EXTI_FTSR_TR18_Pos (18U)
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+#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
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|
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+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
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+#define EXTI_FTSR_TR19_Pos (19U)
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+#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
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|
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+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
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+#define EXTI_FTSR_TR20_Pos (20U)
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+#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
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|
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+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
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+#define EXTI_FTSR_TR21_Pos (21U)
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+#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
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|
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+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
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+#define EXTI_FTSR_TR22_Pos (22U)
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+#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
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+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
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+#define EXTI_FTSR_TR23_Pos (23U)
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+#define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
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|
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+#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
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+#define EXTI_FTSR_TR24_Pos (24U)
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+#define EXTI_FTSR_TR24_Msk (0x1UL << EXTI_FTSR_TR24_Pos) /*!< 0x01000000 */
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+#define EXTI_FTSR_TR24 EXTI_FTSR_TR24_Msk /*!< Falling trigger event configuration bit of line 24 */
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+
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+/****************** Bit definition for EXTI_SWIER register ******************/
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+#define EXTI_SWIER_SWIER0_Pos (0U)
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+#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
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+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
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+#define EXTI_SWIER_SWIER1_Pos (1U)
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+#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
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+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
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+#define EXTI_SWIER_SWIER2_Pos (2U)
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+#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
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+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
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+#define EXTI_SWIER_SWIER3_Pos (3U)
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+#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
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+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
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+#define EXTI_SWIER_SWIER4_Pos (4U)
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+#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
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+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
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+#define EXTI_SWIER_SWIER5_Pos (5U)
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+#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
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+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
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+#define EXTI_SWIER_SWIER6_Pos (6U)
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+#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
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+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
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+#define EXTI_SWIER_SWIER7_Pos (7U)
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|
+#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
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+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
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+#define EXTI_SWIER_SWIER8_Pos (8U)
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|
|
+#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
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+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
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+#define EXTI_SWIER_SWIER9_Pos (9U)
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|
|
+#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
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|
|
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
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|
+#define EXTI_SWIER_SWIER10_Pos (10U)
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|
|
+#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
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|
|
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
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+#define EXTI_SWIER_SWIER11_Pos (11U)
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|
|
+#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
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|
|
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
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|
+#define EXTI_SWIER_SWIER12_Pos (12U)
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|
|
+#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
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|
|
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
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+#define EXTI_SWIER_SWIER13_Pos (13U)
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|
|
+#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
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|
|
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
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|
+#define EXTI_SWIER_SWIER14_Pos (14U)
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|
|
+#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
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|
|
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
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+#define EXTI_SWIER_SWIER15_Pos (15U)
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|
|
+#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
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|
|
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
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+#define EXTI_SWIER_SWIER16_Pos (16U)
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|
|
+#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
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|
|
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
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|
+#define EXTI_SWIER_SWIER17_Pos (17U)
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|
|
+#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
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|
|
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
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|
+#define EXTI_SWIER_SWIER18_Pos (18U)
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|
+#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
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|
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
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+#define EXTI_SWIER_SWIER19_Pos (19U)
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|
+#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
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|
|
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
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+#define EXTI_SWIER_SWIER20_Pos (20U)
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|
+#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
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+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
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+#define EXTI_SWIER_SWIER21_Pos (21U)
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|
+#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
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|
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+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
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+#define EXTI_SWIER_SWIER22_Pos (22U)
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|
|
+#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
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|
|
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
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+#define EXTI_SWIER_SWIER23_Pos (23U)
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+#define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
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+#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
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+#define EXTI_SWIER_SWIER24_Pos (24U)
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+#define EXTI_SWIER_SWIER24_Msk (0x1UL << EXTI_SWIER_SWIER24_Pos) /*!< 0x01000000 */
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+#define EXTI_SWIER_SWIER24 EXTI_SWIER_SWIER24_Msk /*!< Software Interrupt on line 24 */
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+
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+/******************* Bit definition for EXTI_PR register ********************/
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|
+#define EXTI_PR_PR0_Pos (0U)
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|
+#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
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+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
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+#define EXTI_PR_PR1_Pos (1U)
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+#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
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+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
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+#define EXTI_PR_PR2_Pos (2U)
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+#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
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+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
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+#define EXTI_PR_PR3_Pos (3U)
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+#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
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+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
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+#define EXTI_PR_PR4_Pos (4U)
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+#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
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+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
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+#define EXTI_PR_PR5_Pos (5U)
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+#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
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+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
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+#define EXTI_PR_PR6_Pos (6U)
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+#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
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+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
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|
+#define EXTI_PR_PR7_Pos (7U)
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|
+#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
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+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
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|
+#define EXTI_PR_PR8_Pos (8U)
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|
+#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
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+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
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|
+#define EXTI_PR_PR9_Pos (9U)
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|
+#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
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|
|
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
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|
|
+#define EXTI_PR_PR10_Pos (10U)
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|
|
+#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
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|
|
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
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|
|
+#define EXTI_PR_PR11_Pos (11U)
|
|
|
+#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
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|
|
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
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|
|
+#define EXTI_PR_PR12_Pos (12U)
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|
|
+#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
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|
|
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
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|
|
+#define EXTI_PR_PR13_Pos (13U)
|
|
|
+#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
|
|
|
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
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|
+#define EXTI_PR_PR14_Pos (14U)
|
|
|
+#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
|
|
|
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
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|
|
+#define EXTI_PR_PR15_Pos (15U)
|
|
|
+#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
|
|
|
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
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|
|
+#define EXTI_PR_PR16_Pos (16U)
|
|
|
+#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
|
|
|
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
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|
|
+#define EXTI_PR_PR17_Pos (17U)
|
|
|
+#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
|
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|
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
|
|
|
+#define EXTI_PR_PR18_Pos (18U)
|
|
|
+#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
|
|
|
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
|
|
|
+#define EXTI_PR_PR19_Pos (19U)
|
|
|
+#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
|
|
|
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
|
|
|
+#define EXTI_PR_PR20_Pos (20U)
|
|
|
+#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
|
|
|
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
|
|
|
+#define EXTI_PR_PR21_Pos (21U)
|
|
|
+#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
|
|
|
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
|
|
|
+#define EXTI_PR_PR22_Pos (22U)
|
|
|
+#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
|
|
|
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
|
|
|
+#define EXTI_PR_PR23_Pos (23U)
|
|
|
+#define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
|
|
|
+#define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
|
|
|
+#define EXTI_PR_PR24_Pos (24U)
|
|
|
+#define EXTI_PR_PR24_Msk (0x1UL << EXTI_PR_PR24_Pos) /*!< 0x01000000 */
|
|
|
+#define EXTI_PR_PR24 EXTI_PR_PR24_Msk /*!< Pending bit for line 24 */
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* FLASH */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/*
|
|
|
+* @brief FLASH Total Sectors Number
|
|
|
+*/
|
|
|
+#define FLASH_SECTOR_TOTAL 24
|
|
|
+
|
|
|
+/******************* Bits definition for FLASH_ACR register *****************/
|
|
|
+#define FLASH_ACR_LATENCY_Pos (0U)
|
|
|
+#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
|
|
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
|
|
|
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
|
|
|
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
|
|
|
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
|
|
|
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
|
|
|
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
|
|
|
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
|
|
|
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
|
|
|
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
|
|
|
+#define FLASH_ACR_LATENCY_8WS 0x00000008U
|
|
|
+#define FLASH_ACR_LATENCY_9WS 0x00000009U
|
|
|
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU
|
|
|
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU
|
|
|
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU
|
|
|
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU
|
|
|
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU
|
|
|
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU
|
|
|
+#define FLASH_ACR_PRFTEN_Pos (8U)
|
|
|
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
|
|
|
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
|
|
|
+#define FLASH_ACR_ARTEN_Pos (9U)
|
|
|
+#define FLASH_ACR_ARTEN_Msk (0x1UL << FLASH_ACR_ARTEN_Pos) /*!< 0x00000200 */
|
|
|
+#define FLASH_ACR_ARTEN FLASH_ACR_ARTEN_Msk
|
|
|
+#define FLASH_ACR_ARTRST_Pos (11U)
|
|
|
+#define FLASH_ACR_ARTRST_Msk (0x1UL << FLASH_ACR_ARTRST_Pos) /*!< 0x00000800 */
|
|
|
+#define FLASH_ACR_ARTRST FLASH_ACR_ARTRST_Msk
|
|
|
+
|
|
|
+/******************* Bits definition for FLASH_SR register ******************/
|
|
|
+#define FLASH_SR_EOP_Pos (0U)
|
|
|
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
|
|
|
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
|
|
|
+#define FLASH_SR_OPERR_Pos (1U)
|
|
|
+#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
|
|
|
+#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
|
|
|
+#define FLASH_SR_WRPERR_Pos (4U)
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|
|
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
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|
|
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
|
|
|
+#define FLASH_SR_PGAERR_Pos (5U)
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|
|
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
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|
|
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
|
|
|
+#define FLASH_SR_PGPERR_Pos (6U)
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|
|
+#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
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+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
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|
|
+#define FLASH_SR_ERSERR_Pos (7U)
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|
+#define FLASH_SR_ERSERR_Msk (0x1UL << FLASH_SR_ERSERR_Pos) /*!< 0x00000080 */
|
|
|
+#define FLASH_SR_ERSERR FLASH_SR_ERSERR_Msk
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|
|
+#define FLASH_SR_BSY_Pos (16U)
|
|
|
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
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|
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+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
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+
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|
|
+/******************* Bits definition for FLASH_CR register ******************/
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|
|
+#define FLASH_CR_PG_Pos (0U)
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+#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
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+#define FLASH_CR_PG FLASH_CR_PG_Msk
|
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+#define FLASH_CR_SER_Pos (1U)
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+#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000002 */
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|
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+#define FLASH_CR_SER FLASH_CR_SER_Msk
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+#define FLASH_CR_MER_Pos (2U)
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+#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */
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|
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+#define FLASH_CR_MER FLASH_CR_MER_Msk
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+#define FLASH_CR_MER1 FLASH_CR_MER
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+#define FLASH_CR_SNB_Pos (3U)
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+#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
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|
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+#define FLASH_CR_SNB FLASH_CR_SNB_Msk
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+#define FLASH_CR_SNB_0 0x00000008U
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+#define FLASH_CR_SNB_1 0x00000010U
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+#define FLASH_CR_SNB_2 0x00000020U
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+#define FLASH_CR_SNB_3 0x00000040U
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+#define FLASH_CR_SNB_4 0x00000080U
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+#define FLASH_CR_PSIZE_Pos (8U)
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+#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
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+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
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+#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
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+#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
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+#define FLASH_CR_MER2_Pos (15U)
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+#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
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+#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
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+#define FLASH_CR_STRT_Pos (16U)
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+#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
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+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
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+#define FLASH_CR_EOPIE_Pos (24U)
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+#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
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+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
|
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|
+#define FLASH_CR_ERRIE_Pos (25U)
|
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|
+#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
|
|
|
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
|
|
|
+#define FLASH_CR_LOCK_Pos (31U)
|
|
|
+#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
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|
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+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
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+
|
|
|
+/******************* Bits definition for FLASH_OPTCR register ***************/
|
|
|
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)
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|
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
|
|
|
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
|
|
|
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)
|
|
|
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
|
|
|
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
|
|
|
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)
|
|
|
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
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|
|
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
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+#define FLASH_OPTCR_BOR_LEV_0 (0x1UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000004 */
|
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+#define FLASH_OPTCR_BOR_LEV_1 (0x2UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000008 */
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|
|
+#define FLASH_OPTCR_WWDG_SW_Pos (4U)
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|
+#define FLASH_OPTCR_WWDG_SW_Msk (0x1UL << FLASH_OPTCR_WWDG_SW_Pos) /*!< 0x00000010 */
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|
|
+#define FLASH_OPTCR_WWDG_SW FLASH_OPTCR_WWDG_SW_Msk
|
|
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+#define FLASH_OPTCR_IWDG_SW_Pos (5U)
|
|
|
+#define FLASH_OPTCR_IWDG_SW_Msk (0x1UL << FLASH_OPTCR_IWDG_SW_Pos) /*!< 0x00000020 */
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|
|
+#define FLASH_OPTCR_IWDG_SW FLASH_OPTCR_IWDG_SW_Msk
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|
|
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)
|
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+#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
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|
|
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
|
|
|
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
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|
|
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
|
|
|
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
|
|
|
+#define FLASH_OPTCR_RDP_Pos (8U)
|
|
|
+#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
|
|
|
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
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|
|
+#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
|
|
|
+#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
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|
|
+#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
|
|
|
+#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
|
|
|
+#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
|
|
|
+#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
|
|
|
+#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
|
|
|
+#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
|
|
|
+#define FLASH_OPTCR_nWRP_Pos (16U)
|
|
|
+#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
|
|
|
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
|
|
|
+#define FLASH_OPTCR_nWRP_0 0x00010000U
|
|
|
+#define FLASH_OPTCR_nWRP_1 0x00020000U
|
|
|
+#define FLASH_OPTCR_nWRP_2 0x00040000U
|
|
|
+#define FLASH_OPTCR_nWRP_3 0x00080000U
|
|
|
+#define FLASH_OPTCR_nWRP_4 0x00100000U
|
|
|
+#define FLASH_OPTCR_nWRP_5 0x00200000U
|
|
|
+#define FLASH_OPTCR_nWRP_6 0x00400000U
|
|
|
+#define FLASH_OPTCR_nWRP_7 0x00800000U
|
|
|
+#define FLASH_OPTCR_nWRP_8 0x01000000U
|
|
|
+#define FLASH_OPTCR_nWRP_9 0x02000000U
|
|
|
+#define FLASH_OPTCR_nWRP_10 0x04000000U
|
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+#define FLASH_OPTCR_nWRP_11 0x08000000U
|
|
|
+#define FLASH_OPTCR_nDBOOT_Pos (28U)
|
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|
+#define FLASH_OPTCR_nDBOOT_Msk (0x1UL << FLASH_OPTCR_nDBOOT_Pos) /*!< 0x10000000 */
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|
|
+#define FLASH_OPTCR_nDBOOT FLASH_OPTCR_nDBOOT_Msk
|
|
|
+#define FLASH_OPTCR_nDBANK_Pos (29U)
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|
|
+#define FLASH_OPTCR_nDBANK_Msk (0x1UL << FLASH_OPTCR_nDBANK_Pos) /*!< 0x20000000 */
|
|
|
+#define FLASH_OPTCR_nDBANK FLASH_OPTCR_nDBANK_Msk
|
|
|
+#define FLASH_OPTCR_IWDG_STDBY_Pos (30U)
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|
+#define FLASH_OPTCR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTCR_IWDG_STDBY_Pos) /*!< 0x40000000 */
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|
|
+#define FLASH_OPTCR_IWDG_STDBY FLASH_OPTCR_IWDG_STDBY_Msk
|
|
|
+#define FLASH_OPTCR_IWDG_STOP_Pos (31U)
|
|
|
+#define FLASH_OPTCR_IWDG_STOP_Msk (0x1UL << FLASH_OPTCR_IWDG_STOP_Pos) /*!< 0x80000000 */
|
|
|
+#define FLASH_OPTCR_IWDG_STOP FLASH_OPTCR_IWDG_STOP_Msk
|
|
|
+
|
|
|
+/******************* Bits definition for FLASH_OPTCR1 register ***************/
|
|
|
+#define FLASH_OPTCR1_BOOT_ADD0_Pos (0U)
|
|
|
+#define FLASH_OPTCR1_BOOT_ADD0_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
|
|
|
+#define FLASH_OPTCR1_BOOT_ADD0 FLASH_OPTCR1_BOOT_ADD0_Msk
|
|
|
+#define FLASH_OPTCR1_BOOT_ADD1_Pos (16U)
|
|
|
+#define FLASH_OPTCR1_BOOT_ADD1_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
|
|
|
+#define FLASH_OPTCR1_BOOT_ADD1 FLASH_OPTCR1_BOOT_ADD1_Msk
|
|
|
+
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Flexible Memory Controller */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/****************** Bit definition for FMC_BCR1 register *******************/
|
|
|
+#define FMC_BCR1_MBKEN_Pos (0U)
|
|
|
+#define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
|
|
|
+#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
|
|
|
+#define FMC_BCR1_MUXEN_Pos (1U)
|
|
|
+#define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
|
|
|
+#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
|
|
|
+#define FMC_BCR1_MTYP_Pos (2U)
|
|
|
+#define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
|
|
|
+#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
|
|
|
+#define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
|
|
|
+#define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
|
|
|
+#define FMC_BCR1_MWID_Pos (4U)
|
|
|
+#define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
|
|
|
+#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
|
|
|
+#define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
|
|
|
+#define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
|
|
|
+#define FMC_BCR1_FACCEN_Pos (6U)
|
|
|
+#define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
|
|
|
+#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
|
|
|
+#define FMC_BCR1_BURSTEN_Pos (8U)
|
|
|
+#define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
|
|
|
+#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
|
|
|
+#define FMC_BCR1_WAITPOL_Pos (9U)
|
|
|
+#define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
|
|
|
+#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
|
|
|
+#define FMC_BCR1_WRAPMOD_Pos (10U)
|
|
|
+#define FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
|
|
|
+#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
|
|
|
+#define FMC_BCR1_WAITCFG_Pos (11U)
|
|
|
+#define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
|
|
|
+#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
|
|
|
+#define FMC_BCR1_WREN_Pos (12U)
|
|
|
+#define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
|
|
|
+#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
|
|
|
+#define FMC_BCR1_WAITEN_Pos (13U)
|
|
|
+#define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
|
|
|
+#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
|
|
|
+#define FMC_BCR1_EXTMOD_Pos (14U)
|
|
|
+#define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
|
|
|
+#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
|
|
|
+#define FMC_BCR1_ASYNCWAIT_Pos (15U)
|
|
|
+#define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
|
|
|
+#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
|
|
|
+#define FMC_BCR1_CPSIZE_Pos (16U)
|
|
|
+#define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
|
|
|
+#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
|
|
|
+#define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
|
|
|
+#define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
|
|
|
+#define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
|
|
|
+#define FMC_BCR1_CBURSTRW_Pos (19U)
|
|
|
+#define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
|
|
|
+#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
|
|
+#define FMC_BCR1_CCLKEN_Pos (20U)
|
|
|
+#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
|
|
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
|
|
+#define FMC_BCR1_WFDIS_Pos (21U)
|
|
|
+#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
|
|
+#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
|
|
+
|
|
|
+/****************** Bit definition for FMC_BCR2 register *******************/
|
|
|
+#define FMC_BCR2_MBKEN_Pos (0U)
|
|
|
+#define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
|
|
|
+#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
|
|
|
+#define FMC_BCR2_MUXEN_Pos (1U)
|
|
|
+#define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
|
|
|
+#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
|
|
|
+#define FMC_BCR2_MTYP_Pos (2U)
|
|
|
+#define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
|
|
|
+#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
|
|
|
+#define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
|
|
|
+#define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
|
|
|
+#define FMC_BCR2_MWID_Pos (4U)
|
|
|
+#define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
|
|
|
+#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
|
|
|
+#define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
|
|
|
+#define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
|
|
|
+#define FMC_BCR2_FACCEN_Pos (6U)
|
|
|
+#define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
|
|
|
+#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
|
|
|
+#define FMC_BCR2_BURSTEN_Pos (8U)
|
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+#define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
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+#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
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+#define FMC_BCR2_WAITPOL_Pos (9U)
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+#define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
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+#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
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+#define FMC_BCR2_WRAPMOD_Pos (10U)
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+#define FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
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+#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
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+#define FMC_BCR2_WAITCFG_Pos (11U)
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+#define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
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+#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
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+#define FMC_BCR2_WREN_Pos (12U)
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+#define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
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+#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
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+#define FMC_BCR2_WAITEN_Pos (13U)
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+#define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
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+#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
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+#define FMC_BCR2_EXTMOD_Pos (14U)
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+#define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
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+#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
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+#define FMC_BCR2_ASYNCWAIT_Pos (15U)
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+#define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
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+#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
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+#define FMC_BCR2_CPSIZE_Pos (16U)
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+#define FMC_BCR2_CPSIZE_Msk (0x7UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
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+#define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
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+#define FMC_BCR2_CPSIZE_0 (0x1UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
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+#define FMC_BCR2_CPSIZE_1 (0x2UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
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+#define FMC_BCR2_CPSIZE_2 (0x4UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
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+#define FMC_BCR2_CBURSTRW_Pos (19U)
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+#define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
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+#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
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+
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+/****************** Bit definition for FMC_BCR3 register *******************/
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+#define FMC_BCR3_MBKEN_Pos (0U)
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+#define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
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+#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
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+#define FMC_BCR3_MUXEN_Pos (1U)
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+#define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
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+#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
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+#define FMC_BCR3_MTYP_Pos (2U)
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+#define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
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+#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
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+#define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
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+#define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
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+#define FMC_BCR3_MWID_Pos (4U)
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+#define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
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+#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
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+#define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
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+#define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
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+#define FMC_BCR3_FACCEN_Pos (6U)
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+#define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
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+#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
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+#define FMC_BCR3_BURSTEN_Pos (8U)
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+#define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
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+#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
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+#define FMC_BCR3_WAITPOL_Pos (9U)
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+#define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
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+#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
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+#define FMC_BCR3_WRAPMOD_Pos (10U)
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+#define FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
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+#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
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+#define FMC_BCR3_WAITCFG_Pos (11U)
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+#define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
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+#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
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+#define FMC_BCR3_WREN_Pos (12U)
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+#define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
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+#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
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+#define FMC_BCR3_WAITEN_Pos (13U)
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+#define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
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+#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
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+#define FMC_BCR3_EXTMOD_Pos (14U)
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+#define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
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+#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
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+#define FMC_BCR3_ASYNCWAIT_Pos (15U)
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+#define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
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+#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
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+#define FMC_BCR3_CPSIZE_Pos (16U)
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+#define FMC_BCR3_CPSIZE_Msk (0x7UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
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+#define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
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+#define FMC_BCR3_CPSIZE_0 (0x1UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
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+#define FMC_BCR3_CPSIZE_1 (0x2UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
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+#define FMC_BCR3_CPSIZE_2 (0x4UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
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+#define FMC_BCR3_CBURSTRW_Pos (19U)
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+#define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
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+#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
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+
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+/****************** Bit definition for FMC_BCR4 register *******************/
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+#define FMC_BCR4_MBKEN_Pos (0U)
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+#define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
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+#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
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+#define FMC_BCR4_MUXEN_Pos (1U)
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+#define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
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+#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
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+#define FMC_BCR4_MTYP_Pos (2U)
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+#define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
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+#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
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+#define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
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+#define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
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+#define FMC_BCR4_MWID_Pos (4U)
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+#define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
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+#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
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+#define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
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+#define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
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+#define FMC_BCR4_FACCEN_Pos (6U)
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+#define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
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+#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
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+#define FMC_BCR4_BURSTEN_Pos (8U)
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+#define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
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+#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
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+#define FMC_BCR4_WAITPOL_Pos (9U)
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+#define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
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+#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
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+#define FMC_BCR4_WRAPMOD_Pos (10U)
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+#define FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
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+#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
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+#define FMC_BCR4_WAITCFG_Pos (11U)
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+#define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
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+#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
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+#define FMC_BCR4_WREN_Pos (12U)
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+#define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
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+#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
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+#define FMC_BCR4_WAITEN_Pos (13U)
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+#define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
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+#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
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+#define FMC_BCR4_EXTMOD_Pos (14U)
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+#define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
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+#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
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+#define FMC_BCR4_ASYNCWAIT_Pos (15U)
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+#define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
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+#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
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+#define FMC_BCR4_CPSIZE_Pos (16U)
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+#define FMC_BCR4_CPSIZE_Msk (0x7UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
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+#define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
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+#define FMC_BCR4_CPSIZE_0 (0x1UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
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+#define FMC_BCR4_CPSIZE_1 (0x2UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
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+#define FMC_BCR4_CPSIZE_2 (0x4UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
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+#define FMC_BCR4_CBURSTRW_Pos (19U)
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+#define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
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+#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
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+
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+/****************** Bit definition for FMC_BTR1 register ******************/
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+#define FMC_BTR1_ADDSET_Pos (0U)
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+#define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
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+#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
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+#define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
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+#define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
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+#define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
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+#define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
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+#define FMC_BTR1_ADDHLD_Pos (4U)
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+#define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
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+#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
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+#define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
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+#define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
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+#define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
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+#define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
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+#define FMC_BTR1_DATAST_Pos (8U)
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+#define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
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+#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
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+#define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
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+#define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
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+#define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
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+#define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
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+#define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
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+#define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
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+#define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
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+#define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
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+#define FMC_BTR1_BUSTURN_Pos (16U)
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+#define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
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+#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
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+#define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
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+#define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
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+#define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
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+#define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
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+#define FMC_BTR1_CLKDIV_Pos (20U)
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+#define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
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+#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
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+#define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
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+#define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
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+#define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
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+#define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
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+#define FMC_BTR1_DATLAT_Pos (24U)
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+#define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
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+#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
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+#define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
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+#define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
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+#define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
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+#define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
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+#define FMC_BTR1_ACCMOD_Pos (28U)
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+#define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
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+#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
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+#define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
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+#define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
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+
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+/****************** Bit definition for FMC_BTR2 register *******************/
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+#define FMC_BTR2_ADDSET_Pos (0U)
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+#define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
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+#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
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+#define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
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+#define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
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+#define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
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+#define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
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+#define FMC_BTR2_ADDHLD_Pos (4U)
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+#define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
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+#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
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+#define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
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+#define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
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+#define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
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+#define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
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+#define FMC_BTR2_DATAST_Pos (8U)
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+#define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
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+#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
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+#define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
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+#define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
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+#define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
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+#define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
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+#define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
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+#define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
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+#define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
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+#define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
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+#define FMC_BTR2_BUSTURN_Pos (16U)
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+#define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
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+#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
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+#define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
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+#define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
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+#define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
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+#define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
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+#define FMC_BTR2_CLKDIV_Pos (20U)
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+#define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
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+#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
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+#define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
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+#define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
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+#define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
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+#define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
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+#define FMC_BTR2_DATLAT_Pos (24U)
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+#define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
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+#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
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+#define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
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+#define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
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+#define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
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+#define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
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+#define FMC_BTR2_ACCMOD_Pos (28U)
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+#define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
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+#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
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+#define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
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+#define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
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+
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+/******************* Bit definition for FMC_BTR3 register *******************/
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+#define FMC_BTR3_ADDSET_Pos (0U)
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+#define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
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+#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
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+#define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
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+#define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
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+#define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
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+#define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
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+#define FMC_BTR3_ADDHLD_Pos (4U)
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+#define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
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+#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
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+#define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
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+#define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
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+#define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
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+#define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
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+#define FMC_BTR3_DATAST_Pos (8U)
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+#define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
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+#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
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+#define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
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+#define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
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+#define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
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+#define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
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+#define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
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+#define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
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+#define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
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+#define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
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+#define FMC_BTR3_BUSTURN_Pos (16U)
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+#define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
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+#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
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+#define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
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+#define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
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+#define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
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+#define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
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+#define FMC_BTR3_CLKDIV_Pos (20U)
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+#define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
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+#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
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+#define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
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+#define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
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+#define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
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+#define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
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+#define FMC_BTR3_DATLAT_Pos (24U)
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+#define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
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+#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
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+#define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
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+#define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
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+#define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
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+#define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
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+#define FMC_BTR3_ACCMOD_Pos (28U)
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+#define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
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+#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
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+#define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
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+#define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
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+
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+/****************** Bit definition for FMC_BTR4 register *******************/
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+#define FMC_BTR4_ADDSET_Pos (0U)
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+#define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
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+#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
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+#define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
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+#define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
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+#define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
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+#define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
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+#define FMC_BTR4_ADDHLD_Pos (4U)
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+#define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
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+#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
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+#define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
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+#define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
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+#define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
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+#define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
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+#define FMC_BTR4_DATAST_Pos (8U)
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+#define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
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+#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
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+#define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
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+#define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
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+#define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
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+#define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
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+#define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
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+#define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
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+#define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
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+#define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
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+#define FMC_BTR4_BUSTURN_Pos (16U)
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+#define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
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+#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
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+#define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
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+#define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
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+#define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
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+#define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
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+#define FMC_BTR4_CLKDIV_Pos (20U)
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+#define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
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+#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
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+#define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
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+#define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
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+#define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
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+#define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
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+#define FMC_BTR4_DATLAT_Pos (24U)
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+#define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
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+#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
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+#define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
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+#define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
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+#define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
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+#define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
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+#define FMC_BTR4_ACCMOD_Pos (28U)
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+#define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
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+#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
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+#define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
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+#define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
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+
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+/****************** Bit definition for FMC_BWTR1 register ******************/
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+#define FMC_BWTR1_ADDSET_Pos (0U)
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+#define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
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+#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
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+#define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
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+#define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
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+#define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
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+#define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
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+#define FMC_BWTR1_ADDHLD_Pos (4U)
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+#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
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+#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
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+#define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
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+#define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
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+#define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
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+#define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
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+#define FMC_BWTR1_DATAST_Pos (8U)
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+#define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
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+#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
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+#define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
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+#define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
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+#define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
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+#define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
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+#define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
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+#define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
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+#define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
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+#define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
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+#define FMC_BWTR1_BUSTURN_Pos (16U)
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+#define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
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+#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
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+#define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
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+#define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
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+#define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
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+#define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
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+#define FMC_BWTR1_ACCMOD_Pos (28U)
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+#define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
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+#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
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+#define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
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+#define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
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+
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+/****************** Bit definition for FMC_BWTR2 register ******************/
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+#define FMC_BWTR2_ADDSET_Pos (0U)
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+#define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
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+#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
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+#define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
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+#define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
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+#define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
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+#define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
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+#define FMC_BWTR2_ADDHLD_Pos (4U)
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+#define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
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+#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
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+#define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
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+#define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
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+#define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
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+#define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
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+#define FMC_BWTR2_DATAST_Pos (8U)
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+#define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
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+#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
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+#define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
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+#define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
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+#define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
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+#define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
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+#define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
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+#define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
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+#define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
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+#define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
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+#define FMC_BWTR2_BUSTURN_Pos (16U)
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+#define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
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+#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
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+#define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
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+#define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
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+#define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
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+#define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
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+#define FMC_BWTR2_ACCMOD_Pos (28U)
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+#define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
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+#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
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+#define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
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+#define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
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+
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+/****************** Bit definition for FMC_BWTR3 register ******************/
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+#define FMC_BWTR3_ADDSET_Pos (0U)
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+#define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
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+#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
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+#define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
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+#define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
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+#define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
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+#define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
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+#define FMC_BWTR3_ADDHLD_Pos (4U)
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+#define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
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+#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
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+#define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
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+#define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
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+#define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
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+#define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
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+#define FMC_BWTR3_DATAST_Pos (8U)
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+#define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
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+#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
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+#define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
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+#define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
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+#define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
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+#define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
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+#define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
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+#define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
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+#define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
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+#define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
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+#define FMC_BWTR3_BUSTURN_Pos (16U)
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+#define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
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+#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
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+#define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
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+#define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
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+#define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
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+#define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
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+#define FMC_BWTR3_ACCMOD_Pos (28U)
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+#define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
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+#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
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+#define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
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+#define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
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+
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+/****************** Bit definition for FMC_BWTR4 register ******************/
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+#define FMC_BWTR4_ADDSET_Pos (0U)
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+#define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
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+#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
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+#define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
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+#define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
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+#define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
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+#define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
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+#define FMC_BWTR4_ADDHLD_Pos (4U)
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+#define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
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+#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
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+#define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
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+#define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
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+#define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
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+#define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
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+#define FMC_BWTR4_DATAST_Pos (8U)
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+#define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
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+#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
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+#define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
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+#define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
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+#define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
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+#define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
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+#define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
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+#define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
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+#define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
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+#define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
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+#define FMC_BWTR4_BUSTURN_Pos (16U)
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+#define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
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+#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
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+#define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
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+#define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
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+#define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
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+#define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
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+#define FMC_BWTR4_ACCMOD_Pos (28U)
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+#define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
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+#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
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+#define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
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+#define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
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+
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+/****************** Bit definition for FMC_PCR register *******************/
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+#define FMC_PCR_PWAITEN_Pos (1U)
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+#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
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+#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
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+#define FMC_PCR_PBKEN_Pos (2U)
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+#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
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+#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
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+#define FMC_PCR_PTYP_Pos (3U)
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+#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
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+#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
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+#define FMC_PCR_PWID_Pos (4U)
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+#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
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+#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
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+#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
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+#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
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+#define FMC_PCR_ECCEN_Pos (6U)
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+#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
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+#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
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+#define FMC_PCR_TCLR_Pos (9U)
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+#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
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+#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
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+#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
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+#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
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+#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
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+#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
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+#define FMC_PCR_TAR_Pos (13U)
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+#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
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+#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
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+#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
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+#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
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+#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
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+#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
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+#define FMC_PCR_ECCPS_Pos (17U)
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+#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
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+#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
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+#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
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+#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
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+#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
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+
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+/******************* Bit definition for FMC_SR register *******************/
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+#define FMC_SR_IRS_Pos (0U)
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+#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
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+#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
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+#define FMC_SR_ILS_Pos (1U)
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+#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
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+#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
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+#define FMC_SR_IFS_Pos (2U)
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+#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
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+#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
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+#define FMC_SR_IREN_Pos (3U)
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+#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
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+#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
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+#define FMC_SR_ILEN_Pos (4U)
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+#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
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+#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
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+#define FMC_SR_IFEN_Pos (5U)
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+#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
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+#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
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+#define FMC_SR_FEMPT_Pos (6U)
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+#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
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+#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
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+
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+/****************** Bit definition for FMC_PMEM register ******************/
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+#define FMC_PMEM_MEMSET3_Pos (0U)
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+#define FMC_PMEM_MEMSET3_Msk (0xFFUL << FMC_PMEM_MEMSET3_Pos) /*!< 0x000000FF */
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+#define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
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+#define FMC_PMEM_MEMSET3_0 (0x01UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000001 */
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+#define FMC_PMEM_MEMSET3_1 (0x02UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000002 */
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+#define FMC_PMEM_MEMSET3_2 (0x04UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000004 */
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+#define FMC_PMEM_MEMSET3_3 (0x08UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000008 */
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+#define FMC_PMEM_MEMSET3_4 (0x10UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000010 */
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+#define FMC_PMEM_MEMSET3_5 (0x20UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000020 */
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+#define FMC_PMEM_MEMSET3_6 (0x40UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000040 */
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+#define FMC_PMEM_MEMSET3_7 (0x80UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000080 */
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+#define FMC_PMEM_MEMWAIT3_Pos (8U)
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+#define FMC_PMEM_MEMWAIT3_Msk (0xFFUL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x0000FF00 */
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+#define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
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+#define FMC_PMEM_MEMWAIT3_0 (0x01UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000100 */
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+#define FMC_PMEM_MEMWAIT3_1 (0x02UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000200 */
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+#define FMC_PMEM_MEMWAIT3_2 (0x04UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000400 */
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+#define FMC_PMEM_MEMWAIT3_3 (0x08UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000800 */
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+#define FMC_PMEM_MEMWAIT3_4 (0x10UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00001000 */
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+#define FMC_PMEM_MEMWAIT3_5 (0x20UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00002000 */
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+#define FMC_PMEM_MEMWAIT3_6 (0x40UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00004000 */
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+#define FMC_PMEM_MEMWAIT3_7 (0x80UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00008000 */
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+#define FMC_PMEM_MEMHOLD3_Pos (16U)
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+#define FMC_PMEM_MEMHOLD3_Msk (0xFFUL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00FF0000 */
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+#define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
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+#define FMC_PMEM_MEMHOLD3_0 (0x01UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00010000 */
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+#define FMC_PMEM_MEMHOLD3_1 (0x02UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00020000 */
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+#define FMC_PMEM_MEMHOLD3_2 (0x04UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00040000 */
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+#define FMC_PMEM_MEMHOLD3_3 (0x08UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00080000 */
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+#define FMC_PMEM_MEMHOLD3_4 (0x10UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00100000 */
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+#define FMC_PMEM_MEMHOLD3_5 (0x20UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00200000 */
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+#define FMC_PMEM_MEMHOLD3_6 (0x40UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00400000 */
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+#define FMC_PMEM_MEMHOLD3_7 (0x80UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00800000 */
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+#define FMC_PMEM_MEMHIZ3_Pos (24U)
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+#define FMC_PMEM_MEMHIZ3_Msk (0xFFUL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0xFF000000 */
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+#define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
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+#define FMC_PMEM_MEMHIZ3_0 (0x01UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x01000000 */
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+#define FMC_PMEM_MEMHIZ3_1 (0x02UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x02000000 */
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+#define FMC_PMEM_MEMHIZ3_2 (0x04UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x04000000 */
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+#define FMC_PMEM_MEMHIZ3_3 (0x08UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x08000000 */
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+#define FMC_PMEM_MEMHIZ3_4 (0x10UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x10000000 */
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+#define FMC_PMEM_MEMHIZ3_5 (0x20UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x20000000 */
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+#define FMC_PMEM_MEMHIZ3_6 (0x40UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x40000000 */
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+#define FMC_PMEM_MEMHIZ3_7 (0x80UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x80000000 */
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+
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+/****************** Bit definition for FMC_PATT register ******************/
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+#define FMC_PATT_ATTSET3_Pos (0U)
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+#define FMC_PATT_ATTSET3_Msk (0xFFUL << FMC_PATT_ATTSET3_Pos) /*!< 0x000000FF */
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+#define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
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+#define FMC_PATT_ATTSET3_0 (0x01UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000001 */
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+#define FMC_PATT_ATTSET3_1 (0x02UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000002 */
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+#define FMC_PATT_ATTSET3_2 (0x04UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000004 */
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+#define FMC_PATT_ATTSET3_3 (0x08UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000008 */
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+#define FMC_PATT_ATTSET3_4 (0x10UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000010 */
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+#define FMC_PATT_ATTSET3_5 (0x20UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000020 */
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+#define FMC_PATT_ATTSET3_6 (0x40UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000040 */
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+#define FMC_PATT_ATTSET3_7 (0x80UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000080 */
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+#define FMC_PATT_ATTWAIT3_Pos (8U)
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+#define FMC_PATT_ATTWAIT3_Msk (0xFFUL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x0000FF00 */
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+#define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
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+#define FMC_PATT_ATTWAIT3_0 (0x01UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000100 */
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+#define FMC_PATT_ATTWAIT3_1 (0x02UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000200 */
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+#define FMC_PATT_ATTWAIT3_2 (0x04UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000400 */
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+#define FMC_PATT_ATTWAIT3_3 (0x08UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000800 */
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+#define FMC_PATT_ATTWAIT3_4 (0x10UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00001000 */
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+#define FMC_PATT_ATTWAIT3_5 (0x20UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00002000 */
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+#define FMC_PATT_ATTWAIT3_6 (0x40UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00004000 */
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+#define FMC_PATT_ATTWAIT3_7 (0x80UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00008000 */
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+#define FMC_PATT_ATTHOLD3_Pos (16U)
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+#define FMC_PATT_ATTHOLD3_Msk (0xFFUL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00FF0000 */
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+#define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
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+#define FMC_PATT_ATTHOLD3_0 (0x01UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00010000 */
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+#define FMC_PATT_ATTHOLD3_1 (0x02UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00020000 */
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+#define FMC_PATT_ATTHOLD3_2 (0x04UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00040000 */
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+#define FMC_PATT_ATTHOLD3_3 (0x08UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00080000 */
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+#define FMC_PATT_ATTHOLD3_4 (0x10UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00100000 */
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+#define FMC_PATT_ATTHOLD3_5 (0x20UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00200000 */
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+#define FMC_PATT_ATTHOLD3_6 (0x40UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00400000 */
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+#define FMC_PATT_ATTHOLD3_7 (0x80UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00800000 */
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+#define FMC_PATT_ATTHIZ3_Pos (24U)
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+#define FMC_PATT_ATTHIZ3_Msk (0xFFUL << FMC_PATT_ATTHIZ3_Pos) /*!< 0xFF000000 */
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+#define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
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+#define FMC_PATT_ATTHIZ3_0 (0x01UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x01000000 */
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+#define FMC_PATT_ATTHIZ3_1 (0x02UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x02000000 */
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+#define FMC_PATT_ATTHIZ3_2 (0x04UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x04000000 */
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+#define FMC_PATT_ATTHIZ3_3 (0x08UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x08000000 */
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+#define FMC_PATT_ATTHIZ3_4 (0x10UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x10000000 */
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+#define FMC_PATT_ATTHIZ3_5 (0x20UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x20000000 */
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+#define FMC_PATT_ATTHIZ3_6 (0x40UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x40000000 */
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+#define FMC_PATT_ATTHIZ3_7 (0x80UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x80000000 */
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+
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+/****************** Bit definition for FMC_ECCR register ******************/
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+#define FMC_ECCR_ECC3_Pos (0U)
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+#define FMC_ECCR_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC3_Pos) /*!< 0xFFFFFFFF */
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+#define FMC_ECCR_ECC3 FMC_ECCR_ECC3_Msk /*!<ECC result */
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+
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+/****************** Bit definition for FMC_SDCR1 register ******************/
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+#define FMC_SDCR1_NC_Pos (0U)
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+#define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
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+#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
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+#define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
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+#define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
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+#define FMC_SDCR1_NR_Pos (2U)
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+#define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
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+#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
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+#define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
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+#define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
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+#define FMC_SDCR1_MWID_Pos (4U)
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+#define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
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+#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
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+#define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
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+#define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
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+#define FMC_SDCR1_NB_Pos (6U)
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+#define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
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+#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
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+#define FMC_SDCR1_CAS_Pos (7U)
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+#define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
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+#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
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+#define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
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+#define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
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+#define FMC_SDCR1_WP_Pos (9U)
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+#define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
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+#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
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+#define FMC_SDCR1_SDCLK_Pos (10U)
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+#define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
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+#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
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+#define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
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+#define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
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+#define FMC_SDCR1_RBURST_Pos (12U)
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+#define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
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+#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
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+#define FMC_SDCR1_RPIPE_Pos (13U)
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+#define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
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+#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
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+#define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
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+#define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
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+
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+/****************** Bit definition for FMC_SDCR2 register ******************/
|
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+#define FMC_SDCR2_NC_Pos (0U)
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+#define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
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+#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
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+#define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
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+#define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
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+#define FMC_SDCR2_NR_Pos (2U)
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+#define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
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+#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
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+#define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
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+#define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
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+#define FMC_SDCR2_MWID_Pos (4U)
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+#define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
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+#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
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+#define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
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+#define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
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+#define FMC_SDCR2_NB_Pos (6U)
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+#define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
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+#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
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+#define FMC_SDCR2_CAS_Pos (7U)
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+#define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
|
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+#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
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+#define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
|
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+#define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
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+#define FMC_SDCR2_WP_Pos (9U)
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+#define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
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+#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
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+#define FMC_SDCR2_SDCLK_Pos (10U)
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+#define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
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+#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
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+#define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
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+#define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
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+#define FMC_SDCR2_RBURST_Pos (12U)
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+#define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
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+#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
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+#define FMC_SDCR2_RPIPE_Pos (13U)
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+#define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
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+#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
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+#define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
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+#define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
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+
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+/****************** Bit definition for FMC_SDTR1 register ******************/
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+#define FMC_SDTR1_TMRD_Pos (0U)
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+#define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
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+#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
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+#define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
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+#define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
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+#define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
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+#define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
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+#define FMC_SDTR1_TXSR_Pos (4U)
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+#define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
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+#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
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+#define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
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+#define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
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+#define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
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+#define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
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+#define FMC_SDTR1_TRAS_Pos (8U)
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+#define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
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+#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
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+#define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
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+#define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
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+#define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
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+#define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
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+#define FMC_SDTR1_TRC_Pos (12U)
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+#define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
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+#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
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+#define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
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+#define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
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+#define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
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+#define FMC_SDTR1_TWR_Pos (16U)
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+#define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
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+#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
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+#define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
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+#define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
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+#define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
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+#define FMC_SDTR1_TRP_Pos (20U)
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+#define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
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+#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
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+#define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
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+#define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
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+#define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
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+#define FMC_SDTR1_TRCD_Pos (24U)
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+#define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
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+#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
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+#define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
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+#define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
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+#define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
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+
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+/****************** Bit definition for FMC_SDTR2 register ******************/
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+#define FMC_SDTR2_TMRD_Pos (0U)
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+#define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
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+#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
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+#define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
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+#define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
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+#define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
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+#define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
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+#define FMC_SDTR2_TXSR_Pos (4U)
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+#define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
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+#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
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+#define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
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+#define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
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+#define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
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+#define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
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+#define FMC_SDTR2_TRAS_Pos (8U)
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+#define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
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+#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
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+#define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
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+#define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
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+#define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
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+#define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
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+#define FMC_SDTR2_TRC_Pos (12U)
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+#define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
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+#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
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+#define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
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+#define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
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+#define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
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+#define FMC_SDTR2_TWR_Pos (16U)
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+#define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
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+#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
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+#define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
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+#define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
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+#define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
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+#define FMC_SDTR2_TRP_Pos (20U)
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+#define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
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+#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
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+#define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
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+#define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
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+#define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
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+#define FMC_SDTR2_TRCD_Pos (24U)
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+#define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
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+#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
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+#define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
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+#define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
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+#define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
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+
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+/****************** Bit definition for FMC_SDCMR register ******************/
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+#define FMC_SDCMR_MODE_Pos (0U)
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+#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
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+#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
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+#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
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+#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
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+#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
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+#define FMC_SDCMR_CTB2_Pos (3U)
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+#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
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+#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
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+#define FMC_SDCMR_CTB1_Pos (4U)
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+#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
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+#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
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+#define FMC_SDCMR_NRFS_Pos (5U)
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+#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
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+#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
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+#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
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+#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
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+#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
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+#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
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+#define FMC_SDCMR_MRD_Pos (9U)
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+#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
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+#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
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+
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+/****************** Bit definition for FMC_SDRTR register ******************/
|
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+#define FMC_SDRTR_CRE_Pos (0U)
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+#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
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+#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
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+#define FMC_SDRTR_COUNT_Pos (1U)
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+#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
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+#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
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+#define FMC_SDRTR_REIE_Pos (14U)
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+#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
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+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
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+
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+/****************** Bit definition for FMC_SDSR register ******************/
|
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+#define FMC_SDSR_RE_Pos (0U)
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+#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
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+#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
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+#define FMC_SDSR_MODES1_Pos (1U)
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+#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
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+#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
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+#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
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+#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
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+#define FMC_SDSR_MODES2_Pos (3U)
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+#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
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+#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
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+#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
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+#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
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+#define FMC_SDSR_BUSY_Pos (5U)
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+#define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
|
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|
+#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
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|
+
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|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* General Purpose I/O */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/****************** Bits definition for GPIO_MODER register *****************/
|
|
|
+#define GPIO_MODER_MODER0_Pos (0U)
|
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|
+#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
|
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|
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
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|
|
+#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
|
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|
+#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
|
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|
+#define GPIO_MODER_MODER1_Pos (2U)
|
|
|
+#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
|
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|
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
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|
+#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
|
|
|
+#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
|
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|
+#define GPIO_MODER_MODER2_Pos (4U)
|
|
|
+#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
|
|
|
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
|
|
|
+#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
|
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+#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
|
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|
+#define GPIO_MODER_MODER3_Pos (6U)
|
|
|
+#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
|
|
|
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
|
|
|
+#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
|
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|
+#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
|
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|
+#define GPIO_MODER_MODER4_Pos (8U)
|
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|
+#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
|
|
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+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
|
|
|
+#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
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+#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
|
|
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+#define GPIO_MODER_MODER5_Pos (10U)
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+#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
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|
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+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
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+#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
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+#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
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+#define GPIO_MODER_MODER6_Pos (12U)
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+#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
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+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
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+#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
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+#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
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+#define GPIO_MODER_MODER7_Pos (14U)
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+#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
|
|
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+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
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+#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
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+#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
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+#define GPIO_MODER_MODER8_Pos (16U)
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+#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
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+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
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+#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
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+#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
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+#define GPIO_MODER_MODER9_Pos (18U)
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+#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
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+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
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+#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
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+#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
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+#define GPIO_MODER_MODER10_Pos (20U)
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+#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
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+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
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+#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
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+#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
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+#define GPIO_MODER_MODER11_Pos (22U)
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+#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
|
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+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
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+#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
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+#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
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+#define GPIO_MODER_MODER12_Pos (24U)
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+#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
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+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
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+#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
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+#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
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+#define GPIO_MODER_MODER13_Pos (26U)
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+#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
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+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
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+#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
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+#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
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+#define GPIO_MODER_MODER14_Pos (28U)
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+#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
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+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
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|
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+#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
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+#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
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|
+#define GPIO_MODER_MODER15_Pos (30U)
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+#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
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|
|
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
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+#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
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+#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
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+
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|
|
+/****************** Bits definition for GPIO_OTYPER register ****************/
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|
|
+#define GPIO_OTYPER_OT0_Pos (0U)
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|
+#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
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+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
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|
|
+#define GPIO_OTYPER_OT1_Pos (1U)
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+#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
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|
|
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
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|
|
+#define GPIO_OTYPER_OT2_Pos (2U)
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|
|
+#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
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+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
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|
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+#define GPIO_OTYPER_OT3_Pos (3U)
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+#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
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|
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+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
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|
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+#define GPIO_OTYPER_OT4_Pos (4U)
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+#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
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|
|
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
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+#define GPIO_OTYPER_OT5_Pos (5U)
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+#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
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|
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+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
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|
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+#define GPIO_OTYPER_OT6_Pos (6U)
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+#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
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|
|
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
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+#define GPIO_OTYPER_OT7_Pos (7U)
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+#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
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+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
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+#define GPIO_OTYPER_OT8_Pos (8U)
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+#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
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+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
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|
+#define GPIO_OTYPER_OT9_Pos (9U)
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+#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
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|
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
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+#define GPIO_OTYPER_OT10_Pos (10U)
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+#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
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+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
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+#define GPIO_OTYPER_OT11_Pos (11U)
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+#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
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+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
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+#define GPIO_OTYPER_OT12_Pos (12U)
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+#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
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+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
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+#define GPIO_OTYPER_OT13_Pos (13U)
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+#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
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+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
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+#define GPIO_OTYPER_OT14_Pos (14U)
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+#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
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+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
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+#define GPIO_OTYPER_OT15_Pos (15U)
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+#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
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+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
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+
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+/* Legacy defines */
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+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
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+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
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+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
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+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
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+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
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+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
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+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
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+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
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+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
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+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
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+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
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+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
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+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
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+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
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+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
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+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
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+
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|
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+/****************** Bits definition for GPIO_OSPEEDR register ***************/
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+#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
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+#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
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+#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
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+#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
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+#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
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+#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
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+#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
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+#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
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+#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
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+#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
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+#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
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+#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
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+#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
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+#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
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+#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
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+#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
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+#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
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+#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
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|
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+#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
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|
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+#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
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+#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
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+#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
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+#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
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+#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
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|
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+#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
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+#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
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+#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
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+#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
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|
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+#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
|
|
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+#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
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|
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+#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
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+#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
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+#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
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+#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
|
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+#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
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+#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
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+#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
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|
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+#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
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|
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+#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
|
|
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+#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
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|
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+#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
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|
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+#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
|
|
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+#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
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|
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+#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
|
|
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+#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
|
|
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+#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
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|
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+#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
|
|
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+#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
|
|
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+#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
|
|
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+#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
|
|
|
+#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
|
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+#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
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+#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
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+#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
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+#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
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+#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
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+#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
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+#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
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+
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+/* legacy defines */
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+#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
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+#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
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+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
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+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
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+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
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+#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
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+#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
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+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
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+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
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+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
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+#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
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+#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
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+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
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+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
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+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
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+#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
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+#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
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+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
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+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
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+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
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+#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
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+#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
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+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
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+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
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+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
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+#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
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+#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
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+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
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+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
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+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
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+#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
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+#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
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+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
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+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
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+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
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+#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
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+#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
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+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
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+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
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+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
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+#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
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+#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
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+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
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+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
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+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
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+#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
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+#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
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+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
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+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
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+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
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+#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
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+#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
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+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
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+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
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+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
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+#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
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+#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
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+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
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+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
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+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
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+#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
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+#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
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+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
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+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
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+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
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+#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
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+#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
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+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
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+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
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+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
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+#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
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+#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
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+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
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+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
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+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
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+#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
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+#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
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+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
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+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
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+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
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+
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+/****************** Bits definition for GPIO_PUPDR register *****************/
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+#define GPIO_PUPDR_PUPDR0_Pos (0U)
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+#define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
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+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
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+#define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
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+#define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
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+#define GPIO_PUPDR_PUPDR1_Pos (2U)
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+#define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
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+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
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+#define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
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+#define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
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+#define GPIO_PUPDR_PUPDR2_Pos (4U)
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+#define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
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+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
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+#define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
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+#define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
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+#define GPIO_PUPDR_PUPDR3_Pos (6U)
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+#define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
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+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
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+#define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
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+#define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
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+#define GPIO_PUPDR_PUPDR4_Pos (8U)
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+#define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
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+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
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+#define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
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+#define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
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+#define GPIO_PUPDR_PUPDR5_Pos (10U)
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+#define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
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+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
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+#define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
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+#define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
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+#define GPIO_PUPDR_PUPDR6_Pos (12U)
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+#define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
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+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
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+#define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
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+#define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
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+#define GPIO_PUPDR_PUPDR7_Pos (14U)
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+#define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
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+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
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+#define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
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+#define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
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+#define GPIO_PUPDR_PUPDR8_Pos (16U)
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+#define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
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+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
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+#define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
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+#define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
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+#define GPIO_PUPDR_PUPDR9_Pos (18U)
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+#define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
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+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
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+#define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
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+#define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
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+#define GPIO_PUPDR_PUPDR10_Pos (20U)
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+#define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
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+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
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+#define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
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+#define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
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+#define GPIO_PUPDR_PUPDR11_Pos (22U)
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+#define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
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+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
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+#define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
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+#define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
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+#define GPIO_PUPDR_PUPDR12_Pos (24U)
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+#define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
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+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
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+#define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
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+#define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
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+#define GPIO_PUPDR_PUPDR13_Pos (26U)
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+#define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
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+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
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+#define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
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+#define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
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+#define GPIO_PUPDR_PUPDR14_Pos (28U)
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+#define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
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+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
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+#define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
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+#define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
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+#define GPIO_PUPDR_PUPDR15_Pos (30U)
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+#define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
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+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
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+#define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
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+#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
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+
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|
|
+/****************** Bits definition for GPIO_IDR register *******************/
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+#define GPIO_IDR_ID0_Pos (0U)
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+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
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+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
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+#define GPIO_IDR_ID1_Pos (1U)
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+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
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+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
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+#define GPIO_IDR_ID2_Pos (2U)
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+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
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+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
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+#define GPIO_IDR_ID3_Pos (3U)
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+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
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+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
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+#define GPIO_IDR_ID4_Pos (4U)
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+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
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+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
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+#define GPIO_IDR_ID5_Pos (5U)
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+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
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+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
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+#define GPIO_IDR_ID6_Pos (6U)
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+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
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+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
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+#define GPIO_IDR_ID7_Pos (7U)
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+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
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+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
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+#define GPIO_IDR_ID8_Pos (8U)
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|
|
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
|
|
|
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
|
|
|
+#define GPIO_IDR_ID9_Pos (9U)
|
|
|
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
|
|
|
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
|
|
|
+#define GPIO_IDR_ID10_Pos (10U)
|
|
|
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
|
|
|
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
|
|
|
+#define GPIO_IDR_ID11_Pos (11U)
|
|
|
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
|
|
|
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
|
|
|
+#define GPIO_IDR_ID12_Pos (12U)
|
|
|
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
|
|
|
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
|
|
|
+#define GPIO_IDR_ID13_Pos (13U)
|
|
|
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
|
|
|
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
|
|
|
+#define GPIO_IDR_ID14_Pos (14U)
|
|
|
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
|
|
|
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
|
|
|
+#define GPIO_IDR_ID15_Pos (15U)
|
|
|
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
|
|
|
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
|
|
|
+
|
|
|
+/* Legacy defines */
|
|
|
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
|
|
|
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
|
|
|
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
|
|
|
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
|
|
|
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
|
|
|
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
|
|
|
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
|
|
|
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
|
|
|
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
|
|
|
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
|
|
|
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
|
|
|
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
|
|
|
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
|
|
|
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
|
|
|
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
|
|
|
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
|
|
|
+
|
|
|
+/****************** Bits definition for GPIO_ODR register *******************/
|
|
|
+#define GPIO_ODR_OD0_Pos (0U)
|
|
|
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
|
|
|
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
|
|
|
+#define GPIO_ODR_OD1_Pos (1U)
|
|
|
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
|
|
|
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
|
|
|
+#define GPIO_ODR_OD2_Pos (2U)
|
|
|
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
|
|
|
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
|
|
|
+#define GPIO_ODR_OD3_Pos (3U)
|
|
|
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
|
|
|
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
|
|
|
+#define GPIO_ODR_OD4_Pos (4U)
|
|
|
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
|
|
|
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
|
|
|
+#define GPIO_ODR_OD5_Pos (5U)
|
|
|
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
|
|
|
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
|
|
|
+#define GPIO_ODR_OD6_Pos (6U)
|
|
|
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
|
|
|
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
|
|
|
+#define GPIO_ODR_OD7_Pos (7U)
|
|
|
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
|
|
|
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
|
|
|
+#define GPIO_ODR_OD8_Pos (8U)
|
|
|
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
|
|
|
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
|
|
|
+#define GPIO_ODR_OD9_Pos (9U)
|
|
|
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
|
|
|
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
|
|
|
+#define GPIO_ODR_OD10_Pos (10U)
|
|
|
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
|
|
|
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
|
|
|
+#define GPIO_ODR_OD11_Pos (11U)
|
|
|
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
|
|
|
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
|
|
|
+#define GPIO_ODR_OD12_Pos (12U)
|
|
|
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
|
|
|
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
|
|
|
+#define GPIO_ODR_OD13_Pos (13U)
|
|
|
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
|
|
|
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
|
|
|
+#define GPIO_ODR_OD14_Pos (14U)
|
|
|
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
|
|
|
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
|
|
|
+#define GPIO_ODR_OD15_Pos (15U)
|
|
|
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
|
|
|
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
|
|
|
+
|
|
|
+/* Legacy defines */
|
|
|
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
|
|
|
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
|
|
|
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
|
|
|
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
|
|
|
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
|
|
|
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
|
|
|
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
|
|
|
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
|
|
|
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
|
|
|
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
|
|
|
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
|
|
|
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
|
|
|
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
|
|
|
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
|
|
|
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
|
|
|
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
|
|
|
+
|
|
|
+/****************** Bits definition for GPIO_BSRR register ******************/
|
|
|
+#define GPIO_BSRR_BS0_Pos (0U)
|
|
|
+#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
|
|
|
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
|
|
|
+#define GPIO_BSRR_BS1_Pos (1U)
|
|
|
+#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
|
|
|
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
|
|
|
+#define GPIO_BSRR_BS2_Pos (2U)
|
|
|
+#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
|
|
|
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
|
|
|
+#define GPIO_BSRR_BS3_Pos (3U)
|
|
|
+#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
|
|
|
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
|
|
|
+#define GPIO_BSRR_BS4_Pos (4U)
|
|
|
+#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
|
|
|
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
|
|
|
+#define GPIO_BSRR_BS5_Pos (5U)
|
|
|
+#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
|
|
|
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
|
|
|
+#define GPIO_BSRR_BS6_Pos (6U)
|
|
|
+#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
|
|
|
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
|
|
|
+#define GPIO_BSRR_BS7_Pos (7U)
|
|
|
+#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
|
|
|
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
|
|
|
+#define GPIO_BSRR_BS8_Pos (8U)
|
|
|
+#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
|
|
|
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
|
|
|
+#define GPIO_BSRR_BS9_Pos (9U)
|
|
|
+#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
|
|
|
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
|
|
|
+#define GPIO_BSRR_BS10_Pos (10U)
|
|
|
+#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
|
|
|
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
|
|
|
+#define GPIO_BSRR_BS11_Pos (11U)
|
|
|
+#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
|
|
|
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
|
|
|
+#define GPIO_BSRR_BS12_Pos (12U)
|
|
|
+#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
|
|
|
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
|
|
|
+#define GPIO_BSRR_BS13_Pos (13U)
|
|
|
+#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
|
|
|
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
|
|
|
+#define GPIO_BSRR_BS14_Pos (14U)
|
|
|
+#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
|
|
|
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
|
|
|
+#define GPIO_BSRR_BS15_Pos (15U)
|
|
|
+#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
|
|
|
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
|
|
|
+#define GPIO_BSRR_BR0_Pos (16U)
|
|
|
+#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
|
|
|
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
|
|
|
+#define GPIO_BSRR_BR1_Pos (17U)
|
|
|
+#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
|
|
|
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
|
|
|
+#define GPIO_BSRR_BR2_Pos (18U)
|
|
|
+#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
|
|
|
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
|
|
|
+#define GPIO_BSRR_BR3_Pos (19U)
|
|
|
+#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
|
|
|
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
|
|
|
+#define GPIO_BSRR_BR4_Pos (20U)
|
|
|
+#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
|
|
|
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
|
|
|
+#define GPIO_BSRR_BR5_Pos (21U)
|
|
|
+#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
|
|
|
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
|
|
|
+#define GPIO_BSRR_BR6_Pos (22U)
|
|
|
+#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
|
|
|
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
|
|
|
+#define GPIO_BSRR_BR7_Pos (23U)
|
|
|
+#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
|
|
|
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
|
|
|
+#define GPIO_BSRR_BR8_Pos (24U)
|
|
|
+#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
|
|
|
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
|
|
|
+#define GPIO_BSRR_BR9_Pos (25U)
|
|
|
+#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
|
|
|
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
|
|
|
+#define GPIO_BSRR_BR10_Pos (26U)
|
|
|
+#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
|
|
|
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
|
|
|
+#define GPIO_BSRR_BR11_Pos (27U)
|
|
|
+#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
|
|
|
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
|
|
|
+#define GPIO_BSRR_BR12_Pos (28U)
|
|
|
+#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
|
|
|
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
|
|
|
+#define GPIO_BSRR_BR13_Pos (29U)
|
|
|
+#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
|
|
|
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
|
|
|
+#define GPIO_BSRR_BR14_Pos (30U)
|
|
|
+#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
|
|
|
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
|
|
|
+#define GPIO_BSRR_BR15_Pos (31U)
|
|
|
+#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
|
|
|
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
|
|
|
+
|
|
|
+/* Legacy defines */
|
|
|
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
|
|
|
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
|
|
|
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
|
|
|
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
|
|
|
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
|
|
|
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
|
|
|
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
|
|
|
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
|
|
|
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
|
|
|
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
|
|
|
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
|
|
|
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
|
|
|
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
|
|
|
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
|
|
|
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
|
|
|
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
|
|
|
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
|
|
|
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
|
|
|
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
|
|
|
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
|
|
|
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
|
|
|
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
|
|
|
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
|
|
|
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
|
|
|
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
|
|
|
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
|
|
|
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
|
|
|
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
|
|
|
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
|
|
|
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
|
|
|
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
|
|
|
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
|
|
|
+
|
|
|
+/****************** Bit definition for GPIO_LCKR register *********************/
|
|
|
+#define GPIO_LCKR_LCK0_Pos (0U)
|
|
|
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
|
|
|
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
|
|
|
+#define GPIO_LCKR_LCK1_Pos (1U)
|
|
|
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
|
|
|
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
|
|
|
+#define GPIO_LCKR_LCK2_Pos (2U)
|
|
|
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
|
|
|
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
|
|
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+#define GPIO_LCKR_LCK3_Pos (3U)
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|
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+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
|
|
|
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
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|
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+#define GPIO_LCKR_LCK4_Pos (4U)
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|
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+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
|
|
|
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
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|
|
+#define GPIO_LCKR_LCK5_Pos (5U)
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|
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+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
|
|
|
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
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|
|
+#define GPIO_LCKR_LCK6_Pos (6U)
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|
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+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
|
|
|
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
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|
|
+#define GPIO_LCKR_LCK7_Pos (7U)
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+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
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|
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+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
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|
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+#define GPIO_LCKR_LCK8_Pos (8U)
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+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
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|
|
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
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|
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+#define GPIO_LCKR_LCK9_Pos (9U)
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+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
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|
|
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
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|
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+#define GPIO_LCKR_LCK10_Pos (10U)
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+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
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|
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+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
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|
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+#define GPIO_LCKR_LCK11_Pos (11U)
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+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
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|
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+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
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+#define GPIO_LCKR_LCK12_Pos (12U)
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+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
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|
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+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
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+#define GPIO_LCKR_LCK13_Pos (13U)
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+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
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+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
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+#define GPIO_LCKR_LCK14_Pos (14U)
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+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
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|
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+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
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|
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+#define GPIO_LCKR_LCK15_Pos (15U)
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+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
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|
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+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
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+#define GPIO_LCKR_LCKK_Pos (16U)
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+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
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+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
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+
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|
|
+/****************** Bit definition for GPIO_AFRL register *********************/
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+#define GPIO_AFRL_AFRL0_Pos (0U)
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+#define GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
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+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
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+#define GPIO_AFRL_AFRL0_0 (0x1UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000001 */
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+#define GPIO_AFRL_AFRL0_1 (0x2UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000002 */
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|
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+#define GPIO_AFRL_AFRL0_2 (0x4UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000004 */
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|
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+#define GPIO_AFRL_AFRL0_3 (0x8UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000008 */
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|
|
+#define GPIO_AFRL_AFRL1_Pos (4U)
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|
|
+#define GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
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|
|
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
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|
|
+#define GPIO_AFRL_AFRL1_0 (0x1UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000010 */
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|
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+#define GPIO_AFRL_AFRL1_1 (0x2UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000020 */
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|
|
+#define GPIO_AFRL_AFRL1_2 (0x4UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000040 */
|
|
|
+#define GPIO_AFRL_AFRL1_3 (0x8UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000080 */
|
|
|
+#define GPIO_AFRL_AFRL2_Pos (8U)
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|
|
+#define GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
|
|
|
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
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|
|
+#define GPIO_AFRL_AFRL2_0 (0x1UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000100 */
|
|
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+#define GPIO_AFRL_AFRL2_1 (0x2UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000200 */
|
|
|
+#define GPIO_AFRL_AFRL2_2 (0x4UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000400 */
|
|
|
+#define GPIO_AFRL_AFRL2_3 (0x8UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000800 */
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|
|
+#define GPIO_AFRL_AFRL3_Pos (12U)
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|
|
+#define GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
|
|
|
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
|
|
|
+#define GPIO_AFRL_AFRL3_0 (0x1UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00001000 */
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|
|
+#define GPIO_AFRL_AFRL3_1 (0x2UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00002000 */
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|
|
+#define GPIO_AFRL_AFRL3_2 (0x4UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00004000 */
|
|
|
+#define GPIO_AFRL_AFRL3_3 (0x8UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00008000 */
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|
|
+#define GPIO_AFRL_AFRL4_Pos (16U)
|
|
|
+#define GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
|
|
|
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
|
|
|
+#define GPIO_AFRL_AFRL4_0 (0x1UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00010000 */
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|
|
+#define GPIO_AFRL_AFRL4_1 (0x2UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00020000 */
|
|
|
+#define GPIO_AFRL_AFRL4_2 (0x4UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00040000 */
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|
|
+#define GPIO_AFRL_AFRL4_3 (0x8UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00080000 */
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|
|
+#define GPIO_AFRL_AFRL5_Pos (20U)
|
|
|
+#define GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
|
|
|
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
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|
|
+#define GPIO_AFRL_AFRL5_0 (0x1UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00100000 */
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|
|
+#define GPIO_AFRL_AFRL5_1 (0x2UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00200000 */
|
|
|
+#define GPIO_AFRL_AFRL5_2 (0x4UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00400000 */
|
|
|
+#define GPIO_AFRL_AFRL5_3 (0x8UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00800000 */
|
|
|
+#define GPIO_AFRL_AFRL6_Pos (24U)
|
|
|
+#define GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
|
|
|
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
|
|
|
+#define GPIO_AFRL_AFRL6_0 (0x1UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x01000000 */
|
|
|
+#define GPIO_AFRL_AFRL6_1 (0x2UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x02000000 */
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|
|
+#define GPIO_AFRL_AFRL6_2 (0x4UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x04000000 */
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|
|
+#define GPIO_AFRL_AFRL6_3 (0x8UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x08000000 */
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|
|
+#define GPIO_AFRL_AFRL7_Pos (28U)
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|
|
+#define GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
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|
|
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
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+#define GPIO_AFRL_AFRL7_0 (0x1UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x10000000 */
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+#define GPIO_AFRL_AFRL7_1 (0x2UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x20000000 */
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+#define GPIO_AFRL_AFRL7_2 (0x4UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x40000000 */
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|
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+#define GPIO_AFRL_AFRL7_3 (0x8UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x80000000 */
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|
|
+
|
|
|
+/****************** Bit definition for GPIO_AFRH register *********************/
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|
|
+#define GPIO_AFRH_AFRH0_Pos (0U)
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|
+#define GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
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|
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+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
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+#define GPIO_AFRH_AFRH0_0 (0x1UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000001 */
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+#define GPIO_AFRH_AFRH0_1 (0x2UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000002 */
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+#define GPIO_AFRH_AFRH0_2 (0x4UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000004 */
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|
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+#define GPIO_AFRH_AFRH0_3 (0x8UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000008 */
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+#define GPIO_AFRH_AFRH1_Pos (4U)
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+#define GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
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|
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+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
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+#define GPIO_AFRH_AFRH1_0 (0x1UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000010 */
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+#define GPIO_AFRH_AFRH1_1 (0x2UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000020 */
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|
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+#define GPIO_AFRH_AFRH1_2 (0x4UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000040 */
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|
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+#define GPIO_AFRH_AFRH1_3 (0x8UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000080 */
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|
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+#define GPIO_AFRH_AFRH2_Pos (8U)
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|
|
+#define GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
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|
|
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
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|
|
+#define GPIO_AFRH_AFRH2_0 (0x1UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000100 */
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|
|
+#define GPIO_AFRH_AFRH2_1 (0x2UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000200 */
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|
|
+#define GPIO_AFRH_AFRH2_2 (0x4UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000400 */
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|
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+#define GPIO_AFRH_AFRH2_3 (0x8UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000800 */
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|
|
+#define GPIO_AFRH_AFRH3_Pos (12U)
|
|
|
+#define GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
|
|
|
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
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|
|
+#define GPIO_AFRH_AFRH3_0 (0x1UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00001000 */
|
|
|
+#define GPIO_AFRH_AFRH3_1 (0x2UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00002000 */
|
|
|
+#define GPIO_AFRH_AFRH3_2 (0x4UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00004000 */
|
|
|
+#define GPIO_AFRH_AFRH3_3 (0x8UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00008000 */
|
|
|
+#define GPIO_AFRH_AFRH4_Pos (16U)
|
|
|
+#define GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
|
|
|
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
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|
|
+#define GPIO_AFRH_AFRH4_0 (0x1UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00010000 */
|
|
|
+#define GPIO_AFRH_AFRH4_1 (0x2UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00020000 */
|
|
|
+#define GPIO_AFRH_AFRH4_2 (0x4UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00040000 */
|
|
|
+#define GPIO_AFRH_AFRH4_3 (0x8UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00080000 */
|
|
|
+#define GPIO_AFRH_AFRH5_Pos (20U)
|
|
|
+#define GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
|
|
|
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
|
|
|
+#define GPIO_AFRH_AFRH5_0 (0x1UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00100000 */
|
|
|
+#define GPIO_AFRH_AFRH5_1 (0x2UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00200000 */
|
|
|
+#define GPIO_AFRH_AFRH5_2 (0x4UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00400000 */
|
|
|
+#define GPIO_AFRH_AFRH5_3 (0x8UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00800000 */
|
|
|
+#define GPIO_AFRH_AFRH6_Pos (24U)
|
|
|
+#define GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
|
|
|
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
|
|
|
+#define GPIO_AFRH_AFRH6_0 (0x1UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x01000000 */
|
|
|
+#define GPIO_AFRH_AFRH6_1 (0x2UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x02000000 */
|
|
|
+#define GPIO_AFRH_AFRH6_2 (0x4UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x04000000 */
|
|
|
+#define GPIO_AFRH_AFRH6_3 (0x8UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x08000000 */
|
|
|
+#define GPIO_AFRH_AFRH7_Pos (28U)
|
|
|
+#define GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
|
|
|
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
|
|
|
+#define GPIO_AFRH_AFRH7_0 (0x1UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x10000000 */
|
|
|
+#define GPIO_AFRH_AFRH7_1 (0x2UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x20000000 */
|
|
|
+#define GPIO_AFRH_AFRH7_2 (0x4UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x40000000 */
|
|
|
+#define GPIO_AFRH_AFRH7_3 (0x8UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x80000000 */
|
|
|
+
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Inter-integrated Circuit Interface (I2C) */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************* Bit definition for I2C_CR1 register *******************/
|
|
|
+#define I2C_CR1_PE_Pos (0U)
|
|
|
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
|
|
|
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
|
|
|
+#define I2C_CR1_TXIE_Pos (1U)
|
|
|
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
|
|
|
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
|
|
|
+#define I2C_CR1_RXIE_Pos (2U)
|
|
|
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
|
|
|
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
|
|
|
+#define I2C_CR1_ADDRIE_Pos (3U)
|
|
|
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
|
|
|
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
|
|
|
+#define I2C_CR1_NACKIE_Pos (4U)
|
|
|
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
|
|
|
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
|
|
|
+#define I2C_CR1_STOPIE_Pos (5U)
|
|
|
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
|
|
|
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
|
|
|
+#define I2C_CR1_TCIE_Pos (6U)
|
|
|
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
|
|
|
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
|
|
|
+#define I2C_CR1_ERRIE_Pos (7U)
|
|
|
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
|
|
|
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
|
|
|
+#define I2C_CR1_DNF_Pos (8U)
|
|
|
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
|
|
|
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
|
|
|
+#define I2C_CR1_ANFOFF_Pos (12U)
|
|
|
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
|
|
|
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
|
|
|
+#define I2C_CR1_TXDMAEN_Pos (14U)
|
|
|
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
|
|
|
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
|
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+#define I2C_CR1_RXDMAEN_Pos (15U)
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+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
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+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
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+#define I2C_CR1_SBC_Pos (16U)
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+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
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+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
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+#define I2C_CR1_NOSTRETCH_Pos (17U)
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+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
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+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
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+#define I2C_CR1_GCEN_Pos (19U)
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+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
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+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
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+#define I2C_CR1_SMBHEN_Pos (20U)
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+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
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+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
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+#define I2C_CR1_SMBDEN_Pos (21U)
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+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
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+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
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+#define I2C_CR1_ALERTEN_Pos (22U)
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+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
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+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
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+#define I2C_CR1_PECEN_Pos (23U)
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+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
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+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
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+
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+
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+/****************** Bit definition for I2C_CR2 register ********************/
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+#define I2C_CR2_SADD_Pos (0U)
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+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
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+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
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+#define I2C_CR2_RD_WRN_Pos (10U)
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+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
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+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
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+#define I2C_CR2_ADD10_Pos (11U)
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+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
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+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
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+#define I2C_CR2_HEAD10R_Pos (12U)
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+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
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+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
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+#define I2C_CR2_START_Pos (13U)
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+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
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+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
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+#define I2C_CR2_STOP_Pos (14U)
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+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
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+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
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+#define I2C_CR2_NACK_Pos (15U)
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+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
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+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
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+#define I2C_CR2_NBYTES_Pos (16U)
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+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
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+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
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+#define I2C_CR2_RELOAD_Pos (24U)
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+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
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+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
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+#define I2C_CR2_AUTOEND_Pos (25U)
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+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
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+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
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+#define I2C_CR2_PECBYTE_Pos (26U)
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+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
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+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
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+
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+/******************* Bit definition for I2C_OAR1 register ******************/
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+#define I2C_OAR1_OA1_Pos (0U)
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+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
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+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
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+#define I2C_OAR1_OA1MODE_Pos (10U)
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+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
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+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
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+#define I2C_OAR1_OA1EN_Pos (15U)
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+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
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+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
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+
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+/******************* Bit definition for I2C_OAR2 register ******************/
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+#define I2C_OAR2_OA2_Pos (1U)
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+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
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+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
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+#define I2C_OAR2_OA2MSK_Pos (8U)
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+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
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+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
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+#define I2C_OAR2_OA2NOMASK 0x00000000U /*!< No mask */
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+#define I2C_OAR2_OA2MASK01_Pos (8U)
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+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
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+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
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+#define I2C_OAR2_OA2MASK02_Pos (9U)
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+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
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+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
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+#define I2C_OAR2_OA2MASK03_Pos (8U)
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+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
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+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
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+#define I2C_OAR2_OA2MASK04_Pos (10U)
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+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
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+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
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+#define I2C_OAR2_OA2MASK05_Pos (8U)
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+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
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+#define I2C_OAR2_OA2MASK06_Pos (9U)
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+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
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+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
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+#define I2C_OAR2_OA2MASK07_Pos (8U)
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+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
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+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
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+#define I2C_OAR2_OA2EN_Pos (15U)
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+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
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+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
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+
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+/******************* Bit definition for I2C_TIMINGR register *******************/
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+#define I2C_TIMINGR_SCLL_Pos (0U)
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+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
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+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
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+#define I2C_TIMINGR_SCLH_Pos (8U)
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+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
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+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
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+#define I2C_TIMINGR_SDADEL_Pos (16U)
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+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
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+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
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+#define I2C_TIMINGR_SCLDEL_Pos (20U)
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+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
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+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
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+#define I2C_TIMINGR_PRESC_Pos (28U)
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+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
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+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
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+
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+/******************* Bit definition for I2C_TIMEOUTR register *******************/
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+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
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+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
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+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
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+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
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+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
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+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
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+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
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+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
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+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
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+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
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+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
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+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
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+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
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+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
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+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
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+
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+/****************** Bit definition for I2C_ISR register *********************/
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+#define I2C_ISR_TXE_Pos (0U)
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+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
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+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
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+#define I2C_ISR_TXIS_Pos (1U)
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+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
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+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
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+#define I2C_ISR_RXNE_Pos (2U)
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+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
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+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
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+#define I2C_ISR_ADDR_Pos (3U)
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+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
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+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
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+#define I2C_ISR_NACKF_Pos (4U)
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+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
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+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
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+#define I2C_ISR_STOPF_Pos (5U)
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+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
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+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
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+#define I2C_ISR_TC_Pos (6U)
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+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
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+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
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+#define I2C_ISR_TCR_Pos (7U)
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+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
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+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
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+#define I2C_ISR_BERR_Pos (8U)
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+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
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+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
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+#define I2C_ISR_ARLO_Pos (9U)
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+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
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+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
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+#define I2C_ISR_OVR_Pos (10U)
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+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
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+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
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+#define I2C_ISR_PECERR_Pos (11U)
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+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
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+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
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+#define I2C_ISR_TIMEOUT_Pos (12U)
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+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
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+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
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+#define I2C_ISR_ALERT_Pos (13U)
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+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
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+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
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+#define I2C_ISR_BUSY_Pos (15U)
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+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
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+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
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+#define I2C_ISR_DIR_Pos (16U)
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+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
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+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
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+#define I2C_ISR_ADDCODE_Pos (17U)
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+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
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+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
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+
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+/****************** Bit definition for I2C_ICR register *********************/
|
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+#define I2C_ICR_ADDRCF_Pos (3U)
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+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
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+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
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+#define I2C_ICR_NACKCF_Pos (4U)
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+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
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+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
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+#define I2C_ICR_STOPCF_Pos (5U)
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+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
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|
|
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
|
|
|
+#define I2C_ICR_BERRCF_Pos (8U)
|
|
|
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
|
|
|
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
|
|
|
+#define I2C_ICR_ARLOCF_Pos (9U)
|
|
|
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
|
|
|
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
|
|
|
+#define I2C_ICR_OVRCF_Pos (10U)
|
|
|
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
|
|
|
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
|
|
|
+#define I2C_ICR_PECCF_Pos (11U)
|
|
|
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
|
|
|
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
|
|
|
+#define I2C_ICR_TIMOUTCF_Pos (12U)
|
|
|
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
|
|
|
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
|
|
|
+#define I2C_ICR_ALERTCF_Pos (13U)
|
|
|
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
|
|
|
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
|
|
|
+
|
|
|
+/****************** Bit definition for I2C_PECR register *********************/
|
|
|
+#define I2C_PECR_PEC_Pos (0U)
|
|
|
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
|
|
|
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
|
|
|
+
|
|
|
+/****************** Bit definition for I2C_RXDR register *********************/
|
|
|
+#define I2C_RXDR_RXDATA_Pos (0U)
|
|
|
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
|
|
|
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
|
|
|
+
|
|
|
+/****************** Bit definition for I2C_TXDR register *********************/
|
|
|
+#define I2C_TXDR_TXDATA_Pos (0U)
|
|
|
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
|
|
|
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
|
|
|
+
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Independent WATCHDOG */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************* Bit definition for IWDG_KR register ********************/
|
|
|
+#define IWDG_KR_KEY_Pos (0U)
|
|
|
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
|
|
|
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
|
|
|
+
|
|
|
+/******************* Bit definition for IWDG_PR register ********************/
|
|
|
+#define IWDG_PR_PR_Pos (0U)
|
|
|
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
|
|
|
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
|
|
|
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x01 */
|
|
|
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x02 */
|
|
|
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x04 */
|
|
|
+
|
|
|
+/******************* Bit definition for IWDG_RLR register *******************/
|
|
|
+#define IWDG_RLR_RL_Pos (0U)
|
|
|
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
|
|
|
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
|
|
|
+
|
|
|
+/******************* Bit definition for IWDG_SR register ********************/
|
|
|
+#define IWDG_SR_PVU_Pos (0U)
|
|
|
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
|
|
|
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
|
|
|
+#define IWDG_SR_RVU_Pos (1U)
|
|
|
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
|
|
|
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
|
|
|
+#define IWDG_SR_WVU_Pos (2U)
|
|
|
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
|
|
|
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
|
|
|
+
|
|
|
+/******************* Bit definition for IWDG_KR register ********************/
|
|
|
+#define IWDG_WINR_WIN_Pos (0U)
|
|
|
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
|
|
|
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* LCD-TFT Display Controller (LTDC) */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_SSCR register *****************/
|
|
|
+
|
|
|
+#define LTDC_SSCR_VSH_Pos (0U)
|
|
|
+#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
|
|
|
+#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
|
|
|
+#define LTDC_SSCR_HSW_Pos (16U)
|
|
|
+#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
|
|
|
+#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_BPCR register *****************/
|
|
|
+
|
|
|
+#define LTDC_BPCR_AVBP_Pos (0U)
|
|
|
+#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
|
|
|
+#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
|
|
|
+#define LTDC_BPCR_AHBP_Pos (16U)
|
|
|
+#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
|
|
|
+#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_AWCR register *****************/
|
|
|
+
|
|
|
+#define LTDC_AWCR_AAH_Pos (0U)
|
|
|
+#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
|
|
|
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
|
|
|
+#define LTDC_AWCR_AAW_Pos (16U)
|
|
|
+#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
|
|
|
+#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_TWCR register *****************/
|
|
|
+
|
|
|
+#define LTDC_TWCR_TOTALH_Pos (0U)
|
|
|
+#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
|
|
|
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
|
|
|
+#define LTDC_TWCR_TOTALW_Pos (16U)
|
|
|
+#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
|
|
|
+#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_GCR register ******************/
|
|
|
+
|
|
|
+#define LTDC_GCR_LTDCEN_Pos (0U)
|
|
|
+#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
|
|
|
+#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
|
|
|
+#define LTDC_GCR_DBW_Pos (4U)
|
|
|
+#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
|
|
|
+#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
|
|
|
+#define LTDC_GCR_DGW_Pos (8U)
|
|
|
+#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
|
|
|
+#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
|
|
|
+#define LTDC_GCR_DRW_Pos (12U)
|
|
|
+#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
|
|
|
+#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
|
|
|
+#define LTDC_GCR_DEN_Pos (16U)
|
|
|
+#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
|
|
|
+#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
|
|
|
+#define LTDC_GCR_PCPOL_Pos (28U)
|
|
|
+#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
|
|
|
+#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
|
|
|
+#define LTDC_GCR_DEPOL_Pos (29U)
|
|
|
+#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
|
|
|
+#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
|
|
|
+#define LTDC_GCR_VSPOL_Pos (30U)
|
|
|
+#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
|
|
|
+#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
|
|
|
+#define LTDC_GCR_HSPOL_Pos (31U)
|
|
|
+#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
|
|
|
+#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
|
|
|
+
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_SRCR register *****************/
|
|
|
+
|
|
|
+#define LTDC_SRCR_IMR_Pos (0U)
|
|
|
+#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
|
|
|
+#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
|
|
|
+#define LTDC_SRCR_VBR_Pos (1U)
|
|
|
+#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
|
|
|
+#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_BCCR register *****************/
|
|
|
+
|
|
|
+#define LTDC_BCCR_BCBLUE_Pos (0U)
|
|
|
+#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
|
|
|
+#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
|
|
|
+#define LTDC_BCCR_BCGREEN_Pos (8U)
|
|
|
+#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
|
|
|
+#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
|
|
|
+#define LTDC_BCCR_BCRED_Pos (16U)
|
|
|
+#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
|
|
|
+#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_IER register ******************/
|
|
|
+
|
|
|
+#define LTDC_IER_LIE_Pos (0U)
|
|
|
+#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
|
|
|
+#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
|
|
|
+#define LTDC_IER_FUIE_Pos (1U)
|
|
|
+#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
|
|
|
+#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
|
|
|
+#define LTDC_IER_TERRIE_Pos (2U)
|
|
|
+#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
|
|
|
+#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
|
|
|
+#define LTDC_IER_RRIE_Pos (3U)
|
|
|
+#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
|
|
|
+#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_ISR register ******************/
|
|
|
+
|
|
|
+#define LTDC_ISR_LIF_Pos (0U)
|
|
|
+#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
|
|
|
+#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
|
|
|
+#define LTDC_ISR_FUIF_Pos (1U)
|
|
|
+#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
|
|
|
+#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
|
|
|
+#define LTDC_ISR_TERRIF_Pos (2U)
|
|
|
+#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
|
|
|
+#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
|
|
|
+#define LTDC_ISR_RRIF_Pos (3U)
|
|
|
+#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
|
|
|
+#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_ICR register ******************/
|
|
|
+
|
|
|
+#define LTDC_ICR_CLIF_Pos (0U)
|
|
|
+#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
|
|
|
+#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
|
|
|
+#define LTDC_ICR_CFUIF_Pos (1U)
|
|
|
+#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
|
|
|
+#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
|
|
|
+#define LTDC_ICR_CTERRIF_Pos (2U)
|
|
|
+#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
|
|
|
+#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
|
|
|
+#define LTDC_ICR_CRRIF_Pos (3U)
|
|
|
+#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
|
|
|
+#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_LIPCR register ****************/
|
|
|
+
|
|
|
+#define LTDC_LIPCR_LIPOS_Pos (0U)
|
|
|
+#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
|
|
|
+#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_CPSR register *****************/
|
|
|
+
|
|
|
+#define LTDC_CPSR_CYPOS_Pos (0U)
|
|
|
+#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
|
|
|
+#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
|
|
|
+#define LTDC_CPSR_CXPOS_Pos (16U)
|
|
|
+#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
|
|
|
+#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_CDSR register *****************/
|
|
|
+
|
|
|
+#define LTDC_CDSR_VDES_Pos (0U)
|
|
|
+#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
|
|
|
+#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
|
|
|
+#define LTDC_CDSR_HDES_Pos (1U)
|
|
|
+#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
|
|
|
+#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
|
|
|
+#define LTDC_CDSR_VSYNCS_Pos (2U)
|
|
|
+#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
|
|
|
+#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
|
|
|
+#define LTDC_CDSR_HSYNCS_Pos (3U)
|
|
|
+#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
|
|
|
+#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
|
|
|
+
|
|
|
+/******************** Bit definition for LTDC_LxCR register *****************/
|
|
|
+
|
|
|
+#define LTDC_LxCR_LEN_Pos (0U)
|
|
|
+#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
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+#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
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+#define LTDC_LxCR_COLKEN_Pos (1U)
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+#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
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+#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
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+#define LTDC_LxCR_CLUTEN_Pos (4U)
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+#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
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+#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
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+
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+/******************** Bit definition for LTDC_LxWHPCR register **************/
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+
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+#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
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+#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
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+#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
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+#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
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+#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
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+#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
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+
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+/******************** Bit definition for LTDC_LxWVPCR register **************/
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+
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+#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
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+#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
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+#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
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+#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
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+#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
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+#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
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+
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+/******************** Bit definition for LTDC_LxCKCR register ***************/
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+
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+#define LTDC_LxCKCR_CKBLUE_Pos (0U)
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+#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
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+#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
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+#define LTDC_LxCKCR_CKGREEN_Pos (8U)
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+#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
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+#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
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+#define LTDC_LxCKCR_CKRED_Pos (16U)
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+#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
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+#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
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+
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+/******************** Bit definition for LTDC_LxPFCR register ***************/
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+
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+#define LTDC_LxPFCR_PF_Pos (0U)
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+#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
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+#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
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+
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+/******************** Bit definition for LTDC_LxCACR register ***************/
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+
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+#define LTDC_LxCACR_CONSTA_Pos (0U)
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+#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
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+#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
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+
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+/******************** Bit definition for LTDC_LxDCCR register ***************/
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+
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+#define LTDC_LxDCCR_DCBLUE_Pos (0U)
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+#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
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+#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
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+#define LTDC_LxDCCR_DCGREEN_Pos (8U)
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+#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
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+#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
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+#define LTDC_LxDCCR_DCRED_Pos (16U)
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+#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
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+#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
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+#define LTDC_LxDCCR_DCALPHA_Pos (24U)
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+#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
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+#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
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+
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+/******************** Bit definition for LTDC_LxBFCR register ***************/
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+
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+#define LTDC_LxBFCR_BF2_Pos (0U)
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+#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
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+#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
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+#define LTDC_LxBFCR_BF1_Pos (8U)
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+#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
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+#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
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+
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+/******************** Bit definition for LTDC_LxCFBAR register **************/
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+
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+#define LTDC_LxCFBAR_CFBADD_Pos (0U)
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+#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
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+#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
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+
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+/******************** Bit definition for LTDC_LxCFBLR register **************/
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+
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+#define LTDC_LxCFBLR_CFBLL_Pos (0U)
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+#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
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+#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
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+#define LTDC_LxCFBLR_CFBP_Pos (16U)
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+#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
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+#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
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+
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+/******************** Bit definition for LTDC_LxCFBLNR register *************/
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+
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+#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
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+#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
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+#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
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+
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+/******************** Bit definition for LTDC_LxCLUTWR register *************/
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+
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+#define LTDC_LxCLUTWR_BLUE_Pos (0U)
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+#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
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+#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
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+#define LTDC_LxCLUTWR_GREEN_Pos (8U)
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+#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
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+#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
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+#define LTDC_LxCLUTWR_RED_Pos (16U)
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+#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
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+#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
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+#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
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+#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
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+#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
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+
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+/******************************************************************************/
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+/* */
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|
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+/* Power Control */
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+/* */
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+/******************************************************************************/
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+/******************** Bit definition for PWR_CR1 register ********************/
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+#define PWR_CR1_LPDS_Pos (0U)
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+#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
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+#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low-Power Deepsleep */
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+#define PWR_CR1_PDDS_Pos (1U)
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+#define PWR_CR1_PDDS_Msk (0x1UL << PWR_CR1_PDDS_Pos) /*!< 0x00000002 */
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+#define PWR_CR1_PDDS PWR_CR1_PDDS_Msk /*!< Power Down Deepsleep */
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+#define PWR_CR1_CSBF_Pos (3U)
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+#define PWR_CR1_CSBF_Msk (0x1UL << PWR_CR1_CSBF_Pos) /*!< 0x00000008 */
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+#define PWR_CR1_CSBF PWR_CR1_CSBF_Msk /*!< Clear Standby Flag */
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+#define PWR_CR1_PVDE_Pos (4U)
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+#define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos) /*!< 0x00000010 */
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+#define PWR_CR1_PVDE PWR_CR1_PVDE_Msk /*!< Power Voltage Detector Enable */
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+#define PWR_CR1_PLS_Pos (5U)
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+#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
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+#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
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+#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */
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+#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */
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+#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
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+
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|
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+/*!< PVD level configuration */
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+#define PWR_CR1_PLS_LEV0 0x00000000U /*!< PVD level 0 */
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+#define PWR_CR1_PLS_LEV1_Pos (5U)
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+#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
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+#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
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+#define PWR_CR1_PLS_LEV2_Pos (6U)
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+#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
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+#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
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+#define PWR_CR1_PLS_LEV3_Pos (5U)
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+#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
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+#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
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+#define PWR_CR1_PLS_LEV4_Pos (7U)
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+#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
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+#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
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+#define PWR_CR1_PLS_LEV5_Pos (5U)
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+#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
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+#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
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+#define PWR_CR1_PLS_LEV6_Pos (6U)
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+#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
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+#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
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+#define PWR_CR1_PLS_LEV7_Pos (5U)
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+#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
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+#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
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+#define PWR_CR1_DBP_Pos (8U)
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+#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
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+#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */
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+#define PWR_CR1_FPDS_Pos (9U)
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+#define PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos) /*!< 0x00000200 */
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+#define PWR_CR1_FPDS PWR_CR1_FPDS_Msk /*!< Flash power down in Stop mode */
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+#define PWR_CR1_LPUDS_Pos (10U)
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+#define PWR_CR1_LPUDS_Msk (0x1UL << PWR_CR1_LPUDS_Pos) /*!< 0x00000400 */
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+#define PWR_CR1_LPUDS PWR_CR1_LPUDS_Msk /*!< Low-power regulator in deepsleep under-drive mode */
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+#define PWR_CR1_MRUDS_Pos (11U)
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+#define PWR_CR1_MRUDS_Msk (0x1UL << PWR_CR1_MRUDS_Pos) /*!< 0x00000800 */
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+#define PWR_CR1_MRUDS PWR_CR1_MRUDS_Msk /*!< Main regulator in deepsleep under-drive mode */
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+#define PWR_CR1_ADCDC1_Pos (13U)
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+#define PWR_CR1_ADCDC1_Msk (0x1UL << PWR_CR1_ADCDC1_Pos) /*!< 0x00002000 */
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+#define PWR_CR1_ADCDC1 PWR_CR1_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
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+#define PWR_CR1_VOS_Pos (14U)
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+#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x0000C000 */
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+#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
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+#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00004000 */
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+#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00008000 */
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+#define PWR_CR1_ODEN_Pos (16U)
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+#define PWR_CR1_ODEN_Msk (0x1UL << PWR_CR1_ODEN_Pos) /*!< 0x00010000 */
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+#define PWR_CR1_ODEN PWR_CR1_ODEN_Msk /*!< Over Drive enable */
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+#define PWR_CR1_ODSWEN_Pos (17U)
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+#define PWR_CR1_ODSWEN_Msk (0x1UL << PWR_CR1_ODSWEN_Pos) /*!< 0x00020000 */
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+#define PWR_CR1_ODSWEN PWR_CR1_ODSWEN_Msk /*!< Over Drive switch enabled */
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+#define PWR_CR1_UDEN_Pos (18U)
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+#define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
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+#define PWR_CR1_UDEN PWR_CR1_UDEN_Msk /*!< Under Drive enable in stop mode */
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+#define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
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+#define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
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+
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|
|
+/******************* Bit definition for PWR_CSR1 register ********************/
|
|
|
+#define PWR_CSR1_WUIF_Pos (0U)
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|
|
+#define PWR_CSR1_WUIF_Msk (0x1UL << PWR_CSR1_WUIF_Pos) /*!< 0x00000001 */
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|
|
+#define PWR_CSR1_WUIF PWR_CSR1_WUIF_Msk /*!< Wake up internal Flag */
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+#define PWR_CSR1_SBF_Pos (1U)
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|
|
+#define PWR_CSR1_SBF_Msk (0x1UL << PWR_CSR1_SBF_Pos) /*!< 0x00000002 */
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|
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+#define PWR_CSR1_SBF PWR_CSR1_SBF_Msk /*!< Standby Flag */
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|
|
+#define PWR_CSR1_PVDO_Pos (2U)
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|
|
+#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000004 */
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|
|
+#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< PVD Output */
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+#define PWR_CSR1_BRR_Pos (3U)
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|
+#define PWR_CSR1_BRR_Msk (0x1UL << PWR_CSR1_BRR_Pos) /*!< 0x00000008 */
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|
+#define PWR_CSR1_BRR PWR_CSR1_BRR_Msk /*!< Backup regulator ready */
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+#define PWR_CSR1_EIWUP_Pos (8U)
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|
|
+#define PWR_CSR1_EIWUP_Msk (0x1UL << PWR_CSR1_EIWUP_Pos) /*!< 0x00000100 */
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|
+#define PWR_CSR1_EIWUP PWR_CSR1_EIWUP_Msk /*!< Enable internal wakeup */
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|
+#define PWR_CSR1_BRE_Pos (9U)
|
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+#define PWR_CSR1_BRE_Msk (0x1UL << PWR_CSR1_BRE_Pos) /*!< 0x00000200 */
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|
|
+#define PWR_CSR1_BRE PWR_CSR1_BRE_Msk /*!< Backup regulator enable */
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|
+#define PWR_CSR1_VOSRDY_Pos (14U)
|
|
|
+#define PWR_CSR1_VOSRDY_Msk (0x1UL << PWR_CSR1_VOSRDY_Pos) /*!< 0x00004000 */
|
|
|
+#define PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
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|
|
+#define PWR_CSR1_ODRDY_Pos (16U)
|
|
|
+#define PWR_CSR1_ODRDY_Msk (0x1UL << PWR_CSR1_ODRDY_Pos) /*!< 0x00010000 */
|
|
|
+#define PWR_CSR1_ODRDY PWR_CSR1_ODRDY_Msk /*!< Over Drive generator ready */
|
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|
+#define PWR_CSR1_ODSWRDY_Pos (17U)
|
|
|
+#define PWR_CSR1_ODSWRDY_Msk (0x1UL << PWR_CSR1_ODSWRDY_Pos) /*!< 0x00020000 */
|
|
|
+#define PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY_Msk /*!< Over Drive Switch ready */
|
|
|
+#define PWR_CSR1_UDRDY_Pos (18U)
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+#define PWR_CSR1_UDRDY_Msk (0x3UL << PWR_CSR1_UDRDY_Pos) /*!< 0x000C0000 */
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+#define PWR_CSR1_UDRDY PWR_CSR1_UDRDY_Msk /*!< Under Drive ready */
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+
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+
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+/******************** Bit definition for PWR_CR2 register ********************/
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+#define PWR_CR2_CWUPF1_Pos (0U)
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+#define PWR_CR2_CWUPF1_Msk (0x1UL << PWR_CR2_CWUPF1_Pos) /*!< 0x00000001 */
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+#define PWR_CR2_CWUPF1 PWR_CR2_CWUPF1_Msk /*!< Clear Wakeup Pin Flag for PA0 */
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+#define PWR_CR2_CWUPF2_Pos (1U)
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+#define PWR_CR2_CWUPF2_Msk (0x1UL << PWR_CR2_CWUPF2_Pos) /*!< 0x00000002 */
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+#define PWR_CR2_CWUPF2 PWR_CR2_CWUPF2_Msk /*!< Clear Wakeup Pin Flag for PA2 */
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+#define PWR_CR2_CWUPF3_Pos (2U)
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+#define PWR_CR2_CWUPF3_Msk (0x1UL << PWR_CR2_CWUPF3_Pos) /*!< 0x00000004 */
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+#define PWR_CR2_CWUPF3 PWR_CR2_CWUPF3_Msk /*!< Clear Wakeup Pin Flag for PC1 */
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+#define PWR_CR2_CWUPF4_Pos (3U)
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+#define PWR_CR2_CWUPF4_Msk (0x1UL << PWR_CR2_CWUPF4_Pos) /*!< 0x00000008 */
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+#define PWR_CR2_CWUPF4 PWR_CR2_CWUPF4_Msk /*!< Clear Wakeup Pin Flag for PC13 */
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+#define PWR_CR2_CWUPF5_Pos (4U)
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+#define PWR_CR2_CWUPF5_Msk (0x1UL << PWR_CR2_CWUPF5_Pos) /*!< 0x00000010 */
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+#define PWR_CR2_CWUPF5 PWR_CR2_CWUPF5_Msk /*!< Clear Wakeup Pin Flag for PI8 */
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+#define PWR_CR2_CWUPF6_Pos (5U)
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+#define PWR_CR2_CWUPF6_Msk (0x1UL << PWR_CR2_CWUPF6_Pos) /*!< 0x00000020 */
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+#define PWR_CR2_CWUPF6 PWR_CR2_CWUPF6_Msk /*!< Clear Wakeup Pin Flag for PI11 */
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+#define PWR_CR2_WUPP1_Pos (8U)
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+#define PWR_CR2_WUPP1_Msk (0x1UL << PWR_CR2_WUPP1_Pos) /*!< 0x00000100 */
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+#define PWR_CR2_WUPP1 PWR_CR2_WUPP1_Msk /*!< Wakeup Pin Polarity bit for PA0 */
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+#define PWR_CR2_WUPP2_Pos (9U)
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+#define PWR_CR2_WUPP2_Msk (0x1UL << PWR_CR2_WUPP2_Pos) /*!< 0x00000200 */
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+#define PWR_CR2_WUPP2 PWR_CR2_WUPP2_Msk /*!< Wakeup Pin Polarity bit for PA2 */
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+#define PWR_CR2_WUPP3_Pos (10U)
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+#define PWR_CR2_WUPP3_Msk (0x1UL << PWR_CR2_WUPP3_Pos) /*!< 0x00000400 */
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+#define PWR_CR2_WUPP3 PWR_CR2_WUPP3_Msk /*!< Wakeup Pin Polarity bit for PC1 */
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+#define PWR_CR2_WUPP4_Pos (11U)
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+#define PWR_CR2_WUPP4_Msk (0x1UL << PWR_CR2_WUPP4_Pos) /*!< 0x00000800 */
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+#define PWR_CR2_WUPP4 PWR_CR2_WUPP4_Msk /*!< Wakeup Pin Polarity bit for PC13 */
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+#define PWR_CR2_WUPP5_Pos (12U)
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+#define PWR_CR2_WUPP5_Msk (0x1UL << PWR_CR2_WUPP5_Pos) /*!< 0x00001000 */
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+#define PWR_CR2_WUPP5 PWR_CR2_WUPP5_Msk /*!< Wakeup Pin Polarity bit for PI8 */
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+#define PWR_CR2_WUPP6_Pos (13U)
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+#define PWR_CR2_WUPP6_Msk (0x1UL << PWR_CR2_WUPP6_Pos) /*!< 0x00002000 */
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+#define PWR_CR2_WUPP6 PWR_CR2_WUPP6_Msk /*!< Wakeup Pin Polarity bit for PI11 */
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+
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+/******************* Bit definition for PWR_CSR2 register ********************/
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+#define PWR_CSR2_WUPF1_Pos (0U)
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+#define PWR_CSR2_WUPF1_Msk (0x1UL << PWR_CSR2_WUPF1_Pos) /*!< 0x00000001 */
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+#define PWR_CSR2_WUPF1 PWR_CSR2_WUPF1_Msk /*!< Wakeup Pin Flag for PA0 */
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+#define PWR_CSR2_WUPF2_Pos (1U)
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+#define PWR_CSR2_WUPF2_Msk (0x1UL << PWR_CSR2_WUPF2_Pos) /*!< 0x00000002 */
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+#define PWR_CSR2_WUPF2 PWR_CSR2_WUPF2_Msk /*!< Wakeup Pin Flag for PA2 */
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+#define PWR_CSR2_WUPF3_Pos (2U)
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+#define PWR_CSR2_WUPF3_Msk (0x1UL << PWR_CSR2_WUPF3_Pos) /*!< 0x00000004 */
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+#define PWR_CSR2_WUPF3 PWR_CSR2_WUPF3_Msk /*!< Wakeup Pin Flag for PC1 */
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+#define PWR_CSR2_WUPF4_Pos (3U)
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+#define PWR_CSR2_WUPF4_Msk (0x1UL << PWR_CSR2_WUPF4_Pos) /*!< 0x00000008 */
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+#define PWR_CSR2_WUPF4 PWR_CSR2_WUPF4_Msk /*!< Wakeup Pin Flag for PC13 */
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+#define PWR_CSR2_WUPF5_Pos (4U)
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+#define PWR_CSR2_WUPF5_Msk (0x1UL << PWR_CSR2_WUPF5_Pos) /*!< 0x00000010 */
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+#define PWR_CSR2_WUPF5 PWR_CSR2_WUPF5_Msk /*!< Wakeup Pin Flag for PI8 */
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+#define PWR_CSR2_WUPF6_Pos (5U)
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+#define PWR_CSR2_WUPF6_Msk (0x1UL << PWR_CSR2_WUPF6_Pos) /*!< 0x00000020 */
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+#define PWR_CSR2_WUPF6 PWR_CSR2_WUPF6_Msk /*!< Wakeup Pin Flag for PI11 */
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+#define PWR_CSR2_EWUP1_Pos (8U)
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+#define PWR_CSR2_EWUP1_Msk (0x1UL << PWR_CSR2_EWUP1_Pos) /*!< 0x00000100 */
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+#define PWR_CSR2_EWUP1 PWR_CSR2_EWUP1_Msk /*!< Enable Wakeup Pin PA0 */
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+#define PWR_CSR2_EWUP2_Pos (9U)
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+#define PWR_CSR2_EWUP2_Msk (0x1UL << PWR_CSR2_EWUP2_Pos) /*!< 0x00000200 */
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+#define PWR_CSR2_EWUP2 PWR_CSR2_EWUP2_Msk /*!< Enable Wakeup Pin PA2 */
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+#define PWR_CSR2_EWUP3_Pos (10U)
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+#define PWR_CSR2_EWUP3_Msk (0x1UL << PWR_CSR2_EWUP3_Pos) /*!< 0x00000400 */
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+#define PWR_CSR2_EWUP3 PWR_CSR2_EWUP3_Msk /*!< Enable Wakeup Pin PC1 */
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+#define PWR_CSR2_EWUP4_Pos (11U)
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+#define PWR_CSR2_EWUP4_Msk (0x1UL << PWR_CSR2_EWUP4_Pos) /*!< 0x00000800 */
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+#define PWR_CSR2_EWUP4 PWR_CSR2_EWUP4_Msk /*!< Enable Wakeup Pin PC13 */
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+#define PWR_CSR2_EWUP5_Pos (12U)
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+#define PWR_CSR2_EWUP5_Msk (0x1UL << PWR_CSR2_EWUP5_Pos) /*!< 0x00001000 */
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+#define PWR_CSR2_EWUP5 PWR_CSR2_EWUP5_Msk /*!< Enable Wakeup Pin PI8 */
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+#define PWR_CSR2_EWUP6_Pos (13U)
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+#define PWR_CSR2_EWUP6_Msk (0x1UL << PWR_CSR2_EWUP6_Pos) /*!< 0x00002000 */
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+#define PWR_CSR2_EWUP6 PWR_CSR2_EWUP6_Msk /*!< Enable Wakeup Pin PI11 */
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+
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+/******************************************************************************/
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+/* */
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+/* QUADSPI */
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+/* */
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+/******************************************************************************/
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+/***************** Bit definition for QUADSPI_CR register *******************/
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+#define QUADSPI_CR_EN_Pos (0U)
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+#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
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+#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
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+#define QUADSPI_CR_ABORT_Pos (1U)
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+#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
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+#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
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+#define QUADSPI_CR_DMAEN_Pos (2U)
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+#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
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+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
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+#define QUADSPI_CR_TCEN_Pos (3U)
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+#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
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+#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
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+#define QUADSPI_CR_SSHIFT_Pos (4U)
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+#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
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+#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
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+#define QUADSPI_CR_DFM_Pos (6U)
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+#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
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+#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
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+#define QUADSPI_CR_FSEL_Pos (7U)
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+#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
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+#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
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+#define QUADSPI_CR_FTHRES_Pos (8U)
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+#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
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+#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
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+#define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
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+#define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
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+#define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
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+#define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
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+#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
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+#define QUADSPI_CR_TEIE_Pos (16U)
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+#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
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+#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
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+#define QUADSPI_CR_TCIE_Pos (17U)
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+#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
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+#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
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+#define QUADSPI_CR_FTIE_Pos (18U)
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+#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
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+#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
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+#define QUADSPI_CR_SMIE_Pos (19U)
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+#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
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+#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
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+#define QUADSPI_CR_TOIE_Pos (20U)
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+#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
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+#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
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+#define QUADSPI_CR_APMS_Pos (22U)
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+#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
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+#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
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+#define QUADSPI_CR_PMM_Pos (23U)
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+#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
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+#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
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+#define QUADSPI_CR_PRESCALER_Pos (24U)
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+#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
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+#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
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+#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
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+#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
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+#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
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+#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
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+#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
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+#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
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+#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
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+#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
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+
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+/***************** Bit definition for QUADSPI_DCR register ******************/
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+#define QUADSPI_DCR_CKMODE_Pos (0U)
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+#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
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+#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
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+#define QUADSPI_DCR_CSHT_Pos (8U)
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+#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
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+#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
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+#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
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+#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
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+#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
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+#define QUADSPI_DCR_FSIZE_Pos (16U)
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+#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
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+#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
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+#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
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+#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
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+#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
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+#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
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+#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
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+
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+/****************** Bit definition for QUADSPI_SR register *******************/
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+#define QUADSPI_SR_TEF_Pos (0U)
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+#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
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+#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
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+#define QUADSPI_SR_TCF_Pos (1U)
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+#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
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+#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
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+#define QUADSPI_SR_FTF_Pos (2U)
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+#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
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+#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
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+#define QUADSPI_SR_SMF_Pos (3U)
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+#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
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+#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
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+#define QUADSPI_SR_TOF_Pos (4U)
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+#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
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+#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
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+#define QUADSPI_SR_BUSY_Pos (5U)
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+#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
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+#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
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+#define QUADSPI_SR_FLEVEL_Pos (8U)
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+#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
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+#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
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+#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
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+#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
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+#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
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+#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
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+#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
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+#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
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+
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|
+/****************** Bit definition for QUADSPI_FCR register ******************/
|
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|
+#define QUADSPI_FCR_CTEF_Pos (0U)
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+#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
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+#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
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|
+#define QUADSPI_FCR_CTCF_Pos (1U)
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|
+#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
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|
+#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
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|
+#define QUADSPI_FCR_CSMF_Pos (3U)
|
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+#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
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+#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
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+#define QUADSPI_FCR_CTOF_Pos (4U)
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+#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
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+#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
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+
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+/****************** Bit definition for QUADSPI_DLR register ******************/
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+#define QUADSPI_DLR_DL_Pos (0U)
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+#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
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+#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
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+
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+/****************** Bit definition for QUADSPI_CCR register ******************/
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+#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
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+#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
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+#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
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+#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
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+#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
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+#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
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+#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
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+#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
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+#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
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+#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
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+#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
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+#define QUADSPI_CCR_IMODE_Pos (8U)
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+#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
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+#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
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+#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
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+#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
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+#define QUADSPI_CCR_ADMODE_Pos (10U)
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+#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
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+#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
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+#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
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+#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
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+#define QUADSPI_CCR_ADSIZE_Pos (12U)
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+#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
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+#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
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+#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
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+#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
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+#define QUADSPI_CCR_ABMODE_Pos (14U)
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+#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
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+#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
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+#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
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+#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
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+#define QUADSPI_CCR_ABSIZE_Pos (16U)
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+#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
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+#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
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+#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
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+#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
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+#define QUADSPI_CCR_DCYC_Pos (18U)
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+#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
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+#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
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+#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
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+#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
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+#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
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+#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
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+#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
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+#define QUADSPI_CCR_DMODE_Pos (24U)
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+#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
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+#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
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+#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
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+#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
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+#define QUADSPI_CCR_FMODE_Pos (26U)
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+#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
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+#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
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+#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
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+#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
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+#define QUADSPI_CCR_SIOO_Pos (28U)
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+#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
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+#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
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+#define QUADSPI_CCR_DHHC_Pos (30U)
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+#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
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+#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
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+#define QUADSPI_CCR_DDRM_Pos (31U)
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+#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
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+#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
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+/****************** Bit definition for QUADSPI_AR register *******************/
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+#define QUADSPI_AR_ADDRESS_Pos (0U)
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+#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
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+#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
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+
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+/****************** Bit definition for QUADSPI_ABR register ******************/
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+#define QUADSPI_ABR_ALTERNATE_Pos (0U)
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+#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
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+#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
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+
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+/****************** Bit definition for QUADSPI_DR register *******************/
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+#define QUADSPI_DR_DATA_Pos (0U)
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+#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
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+#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
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+
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+/****************** Bit definition for QUADSPI_PSMKR register ****************/
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+#define QUADSPI_PSMKR_MASK_Pos (0U)
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+#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
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+#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
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+
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+/****************** Bit definition for QUADSPI_PSMAR register ****************/
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+#define QUADSPI_PSMAR_MATCH_Pos (0U)
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+#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
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+#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
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+
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+/****************** Bit definition for QUADSPI_PIR register *****************/
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+#define QUADSPI_PIR_INTERVAL_Pos (0U)
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+#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
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+#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
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+
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+/****************** Bit definition for QUADSPI_LPTR register *****************/
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+#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
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+#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
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+#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
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+
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+/******************************************************************************/
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+/* */
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+/* Reset and Clock Control */
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+/* */
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+/******************************************************************************/
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+/******************** Bit definition for RCC_CR register ********************/
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+#define RCC_CR_HSION_Pos (0U)
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+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
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+#define RCC_CR_HSION RCC_CR_HSION_Msk
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+#define RCC_CR_HSIRDY_Pos (1U)
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+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
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+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
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+#define RCC_CR_HSITRIM_Pos (3U)
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+#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
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+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
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+#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
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+#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
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+#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
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+#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
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+#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
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+#define RCC_CR_HSICAL_Pos (8U)
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+#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
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+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
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+#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
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+#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
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+#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
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+#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
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+#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
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+#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
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+#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
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+#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
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+#define RCC_CR_HSEON_Pos (16U)
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+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
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+#define RCC_CR_HSEON RCC_CR_HSEON_Msk
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+#define RCC_CR_HSERDY_Pos (17U)
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+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
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+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
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+#define RCC_CR_HSEBYP_Pos (18U)
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+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
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+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
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+#define RCC_CR_CSSON_Pos (19U)
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+#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
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+#define RCC_CR_CSSON RCC_CR_CSSON_Msk
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+#define RCC_CR_PLLON_Pos (24U)
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+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
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+#define RCC_CR_PLLON RCC_CR_PLLON_Msk
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+#define RCC_CR_PLLRDY_Pos (25U)
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+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
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+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
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+#define RCC_CR_PLLI2SON_Pos (26U)
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+#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
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+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
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+#define RCC_CR_PLLI2SRDY_Pos (27U)
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+#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
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+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
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+#define RCC_CR_PLLSAION_Pos (28U)
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+#define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
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+#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
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+#define RCC_CR_PLLSAIRDY_Pos (29U)
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+#define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
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+#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
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+
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+/******************** Bit definition for RCC_PLLCFGR register ***************/
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+#define RCC_PLLCFGR_PLLM_Pos (0U)
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+#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
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+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
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+#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
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+#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
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+#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
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+#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
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+#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
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+#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
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+#define RCC_PLLCFGR_PLLN_Pos (6U)
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+#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
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+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
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+#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
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+#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
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+#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
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+#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
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+#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
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+#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
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+#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
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+#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
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+#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
|
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|
+#define RCC_PLLCFGR_PLLP_Pos (16U)
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|
+#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
|
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|
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
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+#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
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+#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
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|
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)
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|
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
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+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
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|
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
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+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
|
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+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
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|
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
|
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|
+#define RCC_PLLCFGR_PLLQ_Pos (24U)
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|
+#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
|
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|
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
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|
+#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
|
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|
+#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
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+#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
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+#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
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+
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+#define RCC_PLLCFGR_PLLR_Pos (28U)
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+#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
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+#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
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+#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
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+#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
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+#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
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+
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+/******************** Bit definition for RCC_CFGR register ******************/
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+/*!< SW configuration */
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+#define RCC_CFGR_SW_Pos (0U)
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+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
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+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
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+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
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+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
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+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
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+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
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+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
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+
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+/*!< SWS configuration */
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+#define RCC_CFGR_SWS_Pos (2U)
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+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
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+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
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+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
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+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
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+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
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+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
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+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
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+
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+/*!< HPRE configuration */
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+#define RCC_CFGR_HPRE_Pos (4U)
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+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
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+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
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+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
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+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
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+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
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+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
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+
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+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
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+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
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+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
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+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
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+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
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+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
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+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
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+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
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+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
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+
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+/*!< PPRE1 configuration */
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+#define RCC_CFGR_PPRE1_Pos (10U)
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+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
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+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
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+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
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+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
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+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
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+
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+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
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+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
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+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
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+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
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+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
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+
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+/*!< PPRE2 configuration */
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+#define RCC_CFGR_PPRE2_Pos (13U)
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+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
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+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
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+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
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+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
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+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
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+
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+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
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+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
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+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
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+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
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+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
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+
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+/*!< RTCPRE configuration */
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+#define RCC_CFGR_RTCPRE_Pos (16U)
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+#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
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+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
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+#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
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+#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
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+#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
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+#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
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+#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
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+
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+/*!< MCO1 configuration */
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+#define RCC_CFGR_MCO1_Pos (21U)
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+#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
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+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
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+#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
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+#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
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+
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+#define RCC_CFGR_I2SSRC_Pos (23U)
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+#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
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+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
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+
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+#define RCC_CFGR_MCO1PRE_Pos (24U)
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+#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
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+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
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+#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
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+#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
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+#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
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+
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+#define RCC_CFGR_MCO2PRE_Pos (27U)
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+#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
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+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
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+#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
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+#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
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+#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
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+
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+#define RCC_CFGR_MCO2_Pos (30U)
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+#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
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+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
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+#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
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+#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
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+
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+/******************** Bit definition for RCC_CIR register *******************/
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+#define RCC_CIR_LSIRDYF_Pos (0U)
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+#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
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+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
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+#define RCC_CIR_LSERDYF_Pos (1U)
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+#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
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+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
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+#define RCC_CIR_HSIRDYF_Pos (2U)
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+#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
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+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
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+#define RCC_CIR_HSERDYF_Pos (3U)
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+#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
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+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
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+#define RCC_CIR_PLLRDYF_Pos (4U)
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+#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
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+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
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+#define RCC_CIR_PLLI2SRDYF_Pos (5U)
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+#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
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+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
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+#define RCC_CIR_PLLSAIRDYF_Pos (6U)
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+#define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
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+#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
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+#define RCC_CIR_CSSF_Pos (7U)
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+#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
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+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
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+#define RCC_CIR_LSIRDYIE_Pos (8U)
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+#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
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+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
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+#define RCC_CIR_LSERDYIE_Pos (9U)
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+#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
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+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
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+#define RCC_CIR_HSIRDYIE_Pos (10U)
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+#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
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+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
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+#define RCC_CIR_HSERDYIE_Pos (11U)
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+#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
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+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
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+#define RCC_CIR_PLLRDYIE_Pos (12U)
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+#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
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+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
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+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
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+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
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+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
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+#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
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+#define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
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+#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
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+#define RCC_CIR_LSIRDYC_Pos (16U)
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+#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
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+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
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+#define RCC_CIR_LSERDYC_Pos (17U)
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+#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
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+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
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+#define RCC_CIR_HSIRDYC_Pos (18U)
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+#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
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+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
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+#define RCC_CIR_HSERDYC_Pos (19U)
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+#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
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+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
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+#define RCC_CIR_PLLRDYC_Pos (20U)
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+#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
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+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
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+#define RCC_CIR_PLLI2SRDYC_Pos (21U)
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+#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
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+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
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+#define RCC_CIR_PLLSAIRDYC_Pos (22U)
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+#define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
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+#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
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+#define RCC_CIR_CSSC_Pos (23U)
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+#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
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+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
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+
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+/******************** Bit definition for RCC_AHB1RSTR register **************/
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+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
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+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
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+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
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+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
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+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
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+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
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+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
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+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
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+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
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+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
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+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
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+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
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+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
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+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
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+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
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+#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
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+#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
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+#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
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+#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
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+#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
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+#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
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+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
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+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
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+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
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+#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
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+#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
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+#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
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|
+#define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
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+#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
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+#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
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+#define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
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+#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
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+#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
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+#define RCC_AHB1RSTR_CRCRST_Pos (12U)
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+#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
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+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
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+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
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+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
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+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
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+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
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+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
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+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
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+#define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
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+#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
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+#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
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+#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
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+#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
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+#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
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+#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
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+#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
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+#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
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+
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+/******************** Bit definition for RCC_AHB2RSTR register **************/
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+#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
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+#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
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+#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
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+#define RCC_AHB2RSTR_JPEGRST_Pos (1U)
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+#define RCC_AHB2RSTR_JPEGRST_Msk (0x1UL << RCC_AHB2RSTR_JPEGRST_Pos) /*!< 0x00000002 */
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+#define RCC_AHB2RSTR_JPEGRST RCC_AHB2RSTR_JPEGRST_Msk
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+#define RCC_AHB2RSTR_RNGRST_Pos (6U)
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+#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
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+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
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+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
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+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
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+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
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+
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+/******************** Bit definition for RCC_AHB3RSTR register **************/
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+
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+#define RCC_AHB3RSTR_FMCRST_Pos (0U)
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+#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
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+#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
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+#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
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+#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
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+#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
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+
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+/******************** Bit definition for RCC_APB1RSTR register **************/
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+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
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+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
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+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
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+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
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+#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
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+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
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+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
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+#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
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+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
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+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
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+#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
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+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
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+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
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+#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
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+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
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+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
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+#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
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+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
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+#define RCC_APB1RSTR_TIM12RST_Pos (6U)
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+#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
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+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
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+#define RCC_APB1RSTR_TIM13RST_Pos (7U)
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+#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
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+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
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+#define RCC_APB1RSTR_TIM14RST_Pos (8U)
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+#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
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+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
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+#define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
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+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
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+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
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+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
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+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
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+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
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+#define RCC_APB1RSTR_CAN3RST_Pos (13U)
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+#define RCC_APB1RSTR_CAN3RST_Msk (0x1UL << RCC_APB1RSTR_CAN3RST_Pos) /*!< 0x00002000 */
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+#define RCC_APB1RSTR_CAN3RST RCC_APB1RSTR_CAN3RST_Msk
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+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
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+#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
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+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
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+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
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+#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
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+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
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+#define RCC_APB1RSTR_SPDIFRXRST_Pos (16U)
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+#define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1RSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
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+#define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk
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+#define RCC_APB1RSTR_USART2RST_Pos (17U)
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+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
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+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
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+#define RCC_APB1RSTR_USART3RST_Pos (18U)
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+#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
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+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
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+#define RCC_APB1RSTR_UART4RST_Pos (19U)
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+#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
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+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
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+#define RCC_APB1RSTR_UART5RST_Pos (20U)
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+#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
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+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
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+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
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+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
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+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
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+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
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+#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
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+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
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+#define RCC_APB1RSTR_I2C3RST_Pos (23U)
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+#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
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+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
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+#define RCC_APB1RSTR_I2C4RST_Pos (24U)
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+#define RCC_APB1RSTR_I2C4RST_Msk (0x1UL << RCC_APB1RSTR_I2C4RST_Pos) /*!< 0x01000000 */
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+#define RCC_APB1RSTR_I2C4RST RCC_APB1RSTR_I2C4RST_Msk
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+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
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+#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
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+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
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+#define RCC_APB1RSTR_CAN2RST_Pos (26U)
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+#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
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+#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
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+#define RCC_APB1RSTR_CECRST_Pos (27U)
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+#define RCC_APB1RSTR_CECRST_Msk (0x1UL << RCC_APB1RSTR_CECRST_Pos) /*!< 0x08000000 */
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+#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk
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+#define RCC_APB1RSTR_PWRRST_Pos (28U)
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+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
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+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
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+#define RCC_APB1RSTR_DACRST_Pos (29U)
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+#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
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+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
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+#define RCC_APB1RSTR_UART7RST_Pos (30U)
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+#define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
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+#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
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+#define RCC_APB1RSTR_UART8RST_Pos (31U)
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+#define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
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+#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
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+
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+/******************** Bit definition for RCC_APB2RSTR register **************/
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+#define RCC_APB2RSTR_TIM1RST_Pos (0U)
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+#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
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+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
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+#define RCC_APB2RSTR_TIM8RST_Pos (1U)
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+#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
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+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
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+#define RCC_APB2RSTR_USART1RST_Pos (4U)
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+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
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+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
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+#define RCC_APB2RSTR_USART6RST_Pos (5U)
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+#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
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+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
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+#define RCC_APB2RSTR_SDMMC2RST_Pos (7U)
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+#define RCC_APB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */
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+#define RCC_APB2RSTR_SDMMC2RST RCC_APB2RSTR_SDMMC2RST_Msk
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+#define RCC_APB2RSTR_ADCRST_Pos (8U)
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+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
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+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
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+#define RCC_APB2RSTR_SDMMC1RST_Pos (11U)
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+#define RCC_APB2RSTR_SDMMC1RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000800 */
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+#define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
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+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
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+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
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+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
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+#define RCC_APB2RSTR_SPI4RST_Pos (13U)
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+#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
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+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
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+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
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+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
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+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
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+#define RCC_APB2RSTR_TIM9RST_Pos (16U)
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+#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
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+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
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+#define RCC_APB2RSTR_TIM10RST_Pos (17U)
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+#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
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+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
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+#define RCC_APB2RSTR_TIM11RST_Pos (18U)
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+#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
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+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
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+#define RCC_APB2RSTR_SPI5RST_Pos (20U)
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+#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
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+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
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+#define RCC_APB2RSTR_SPI6RST_Pos (21U)
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+#define RCC_APB2RSTR_SPI6RST_Msk (0x1UL << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
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+#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
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+#define RCC_APB2RSTR_SAI1RST_Pos (22U)
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+#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
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+#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
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+#define RCC_APB2RSTR_SAI2RST_Pos (23U)
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+#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
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+#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
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+#define RCC_APB2RSTR_LTDCRST_Pos (26U)
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+#define RCC_APB2RSTR_LTDCRST_Msk (0x1UL << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
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+#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
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+#define RCC_APB2RSTR_DSIRST_Pos (27U)
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+#define RCC_APB2RSTR_DSIRST_Msk (0x1UL << RCC_APB2RSTR_DSIRST_Pos) /*!< 0x08000000 */
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+#define RCC_APB2RSTR_DSIRST RCC_APB2RSTR_DSIRST_Msk
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+#define RCC_APB2RSTR_DFSDM1RST_Pos (29U)
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+#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x20000000 */
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+#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
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+#define RCC_APB2RSTR_MDIORST_Pos (30U)
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+#define RCC_APB2RSTR_MDIORST_Msk (0x1UL << RCC_APB2RSTR_MDIORST_Pos) /*!< 0x40000000 */
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+#define RCC_APB2RSTR_MDIORST RCC_APB2RSTR_MDIORST_Msk
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+
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+/******************** Bit definition for RCC_AHB1ENR register ***************/
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+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
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+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
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+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
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+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
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+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
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+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
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+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
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+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
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+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
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+#define RCC_AHB1ENR_GPIODEN_Pos (3U)
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+#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
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+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
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+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
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+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
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+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
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+#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
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+#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
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+#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
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+#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
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+#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
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+#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
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+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
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+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
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+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
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+#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
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+#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
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+#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
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+#define RCC_AHB1ENR_GPIOJEN_Pos (9U)
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+#define RCC_AHB1ENR_GPIOJEN_Msk (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
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+#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
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+#define RCC_AHB1ENR_GPIOKEN_Pos (10U)
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+#define RCC_AHB1ENR_GPIOKEN_Msk (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
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+#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
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+#define RCC_AHB1ENR_CRCEN_Pos (12U)
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+#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
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+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
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+#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
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+#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
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+#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
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+#define RCC_AHB1ENR_DTCMRAMEN_Pos (20U)
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+#define RCC_AHB1ENR_DTCMRAMEN_Msk (0x1UL << RCC_AHB1ENR_DTCMRAMEN_Pos) /*!< 0x00100000 */
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+#define RCC_AHB1ENR_DTCMRAMEN RCC_AHB1ENR_DTCMRAMEN_Msk
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+#define RCC_AHB1ENR_DMA1EN_Pos (21U)
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+#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
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+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
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+#define RCC_AHB1ENR_DMA2EN_Pos (22U)
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+#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
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+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
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+#define RCC_AHB1ENR_DMA2DEN_Pos (23U)
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+#define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
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+#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
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+#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
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+#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
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+#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
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+#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
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+#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
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+#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
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+#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
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+#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
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+#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
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+#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
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+#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
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+#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
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+#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
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+#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
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+#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
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+#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
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+#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
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+#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
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+
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+/******************** Bit definition for RCC_AHB2ENR register ***************/
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+#define RCC_AHB2ENR_DCMIEN_Pos (0U)
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+#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
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+#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
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+#define RCC_AHB2ENR_JPEGEN_Pos (1U)
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+#define RCC_AHB2ENR_JPEGEN_Msk (0x1UL << RCC_AHB2ENR_JPEGEN_Pos) /*!< 0x00000002 */
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+#define RCC_AHB2ENR_JPEGEN RCC_AHB2ENR_JPEGEN_Msk
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+#define RCC_AHB2ENR_RNGEN_Pos (6U)
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+#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
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+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
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+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
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+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
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+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
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+
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+/******************** Bit definition for RCC_AHB3ENR register ***************/
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+#define RCC_AHB3ENR_FMCEN_Pos (0U)
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+#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
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+#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
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+#define RCC_AHB3ENR_QSPIEN_Pos (1U)
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+#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
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+#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
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+
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+/******************** Bit definition for RCC_APB1ENR register ***************/
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+#define RCC_APB1ENR_TIM2EN_Pos (0U)
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+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
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+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
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+#define RCC_APB1ENR_TIM3EN_Pos (1U)
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+#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
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+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
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+#define RCC_APB1ENR_TIM4EN_Pos (2U)
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+#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
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+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
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+#define RCC_APB1ENR_TIM5EN_Pos (3U)
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+#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
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+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
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+#define RCC_APB1ENR_TIM6EN_Pos (4U)
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+#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
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+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
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+#define RCC_APB1ENR_TIM7EN_Pos (5U)
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+#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
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+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
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+#define RCC_APB1ENR_TIM12EN_Pos (6U)
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+#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
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+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
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+#define RCC_APB1ENR_TIM13EN_Pos (7U)
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+#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
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+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
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+#define RCC_APB1ENR_TIM14EN_Pos (8U)
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+#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
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+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
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+#define RCC_APB1ENR_LPTIM1EN_Pos (9U)
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+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
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+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
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+#define RCC_APB1ENR_RTCEN_Pos (10U)
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+#define RCC_APB1ENR_RTCEN_Msk (0x1UL << RCC_APB1ENR_RTCEN_Pos) /*!< 0x00000400 */
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+#define RCC_APB1ENR_RTCEN RCC_APB1ENR_RTCEN_Msk
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+#define RCC_APB1ENR_WWDGEN_Pos (11U)
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+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
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+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
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+#define RCC_APB1ENR_CAN3EN_Pos (13U)
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+#define RCC_APB1ENR_CAN3EN_Msk (0x1UL << RCC_APB1ENR_CAN3EN_Pos) /*!< 0x00002000 */
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+#define RCC_APB1ENR_CAN3EN RCC_APB1ENR_CAN3EN_Msk
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+#define RCC_APB1ENR_SPI2EN_Pos (14U)
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+#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
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+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
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+#define RCC_APB1ENR_SPI3EN_Pos (15U)
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+#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
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+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
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+#define RCC_APB1ENR_SPDIFRXEN_Pos (16U)
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+#define RCC_APB1ENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1ENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
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+#define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk
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+#define RCC_APB1ENR_USART2EN_Pos (17U)
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+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
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+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
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+#define RCC_APB1ENR_USART3EN_Pos (18U)
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+#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
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+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
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+#define RCC_APB1ENR_UART4EN_Pos (19U)
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+#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
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+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
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+#define RCC_APB1ENR_UART5EN_Pos (20U)
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+#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
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+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
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+#define RCC_APB1ENR_I2C1EN_Pos (21U)
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+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
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+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
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+#define RCC_APB1ENR_I2C2EN_Pos (22U)
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+#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
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+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
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+#define RCC_APB1ENR_I2C3EN_Pos (23U)
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+#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
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+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
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+#define RCC_APB1ENR_I2C4EN_Pos (24U)
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+#define RCC_APB1ENR_I2C4EN_Msk (0x1UL << RCC_APB1ENR_I2C4EN_Pos) /*!< 0x01000000 */
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+#define RCC_APB1ENR_I2C4EN RCC_APB1ENR_I2C4EN_Msk
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+#define RCC_APB1ENR_CAN1EN_Pos (25U)
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+#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
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+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
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+#define RCC_APB1ENR_CAN2EN_Pos (26U)
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+#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
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+#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
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+#define RCC_APB1ENR_CECEN_Pos (27U)
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+#define RCC_APB1ENR_CECEN_Msk (0x1UL << RCC_APB1ENR_CECEN_Pos) /*!< 0x08000000 */
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+#define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk
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+#define RCC_APB1ENR_PWREN_Pos (28U)
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+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
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+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
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+#define RCC_APB1ENR_DACEN_Pos (29U)
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+#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
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+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
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+#define RCC_APB1ENR_UART7EN_Pos (30U)
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+#define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
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+#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
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+#define RCC_APB1ENR_UART8EN_Pos (31U)
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+#define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
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+#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
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+
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+/******************** Bit definition for RCC_APB2ENR register ***************/
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+#define RCC_APB2ENR_TIM1EN_Pos (0U)
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+#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
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+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
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+#define RCC_APB2ENR_TIM8EN_Pos (1U)
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+#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
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+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
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+#define RCC_APB2ENR_USART1EN_Pos (4U)
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+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
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+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
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+#define RCC_APB2ENR_USART6EN_Pos (5U)
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+#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
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+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
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+#define RCC_APB2ENR_SDMMC2EN_Pos (7U)
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+#define RCC_APB2ENR_SDMMC2EN_Msk (0x1UL << RCC_APB2ENR_SDMMC2EN_Pos) /*!< 0x00000080 */
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+#define RCC_APB2ENR_SDMMC2EN RCC_APB2ENR_SDMMC2EN_Msk
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+#define RCC_APB2ENR_ADC1EN_Pos (8U)
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+#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
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+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
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+#define RCC_APB2ENR_ADC2EN_Pos (9U)
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+#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
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+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
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+#define RCC_APB2ENR_ADC3EN_Pos (10U)
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+#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
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+#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
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+#define RCC_APB2ENR_SDMMC1EN_Pos (11U)
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+#define RCC_APB2ENR_SDMMC1EN_Msk (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000800 */
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+#define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
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+#define RCC_APB2ENR_SPI1EN_Pos (12U)
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+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
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+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
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+#define RCC_APB2ENR_SPI4EN_Pos (13U)
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+#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
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+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
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+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
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+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
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+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
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+#define RCC_APB2ENR_TIM9EN_Pos (16U)
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+#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
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+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
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+#define RCC_APB2ENR_TIM10EN_Pos (17U)
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+#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
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+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
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+#define RCC_APB2ENR_TIM11EN_Pos (18U)
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+#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
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+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
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+#define RCC_APB2ENR_SPI5EN_Pos (20U)
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+#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
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+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
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+#define RCC_APB2ENR_SPI6EN_Pos (21U)
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+#define RCC_APB2ENR_SPI6EN_Msk (0x1UL << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
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+#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
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+#define RCC_APB2ENR_SAI1EN_Pos (22U)
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+#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
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+#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
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+#define RCC_APB2ENR_SAI2EN_Pos (23U)
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+#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
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+#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
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+#define RCC_APB2ENR_LTDCEN_Pos (26U)
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+#define RCC_APB2ENR_LTDCEN_Msk (0x1UL << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
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+#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
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+#define RCC_APB2ENR_DSIEN_Pos (27U)
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+#define RCC_APB2ENR_DSIEN_Msk (0x1UL << RCC_APB2ENR_DSIEN_Pos) /*!< 0x08000000 */
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+#define RCC_APB2ENR_DSIEN RCC_APB2ENR_DSIEN_Msk
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+#define RCC_APB2ENR_DFSDM1EN_Pos (29U)
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+#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x20000000 */
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+#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
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+#define RCC_APB2ENR_MDIOEN_Pos (30U)
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+#define RCC_APB2ENR_MDIOEN_Msk (0x1UL << RCC_APB2ENR_MDIOEN_Pos) /*!< 0x40000000 */
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+#define RCC_APB2ENR_MDIOEN RCC_APB2ENR_MDIOEN_Msk
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+
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+/******************** Bit definition for RCC_AHB1LPENR register *************/
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+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
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+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
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+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
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+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
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+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
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+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
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+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
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+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
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+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
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+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
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+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
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+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
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+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
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+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
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+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
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+#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
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+#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
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+#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
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+#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
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+#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
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+#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
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+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
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+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
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+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
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+#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
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+#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
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+#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
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+#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
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+#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
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+#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
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+#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
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+#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
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+#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
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+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
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+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
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+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
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+#define RCC_AHB1LPENR_AXILPEN_Pos (13U)
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+#define RCC_AHB1LPENR_AXILPEN_Msk (0x1UL << RCC_AHB1LPENR_AXILPEN_Pos) /*!< 0x00002000 */
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+#define RCC_AHB1LPENR_AXILPEN RCC_AHB1LPENR_AXILPEN_Msk
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+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
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+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
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+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
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+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
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+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
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+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
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+#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
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+#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
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+#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
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+#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
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+#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
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+#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
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+#define RCC_AHB1LPENR_DTCMLPEN_Pos (20U)
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+#define RCC_AHB1LPENR_DTCMLPEN_Msk (0x1UL << RCC_AHB1LPENR_DTCMLPEN_Pos) /*!< 0x00100000 */
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+#define RCC_AHB1LPENR_DTCMLPEN RCC_AHB1LPENR_DTCMLPEN_Msk
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+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
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+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
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+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
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+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
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+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
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+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
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+#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
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+#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
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+#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
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+#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
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+#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
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+#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
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+#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
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+#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
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+#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
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+#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
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+#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
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+#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
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+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
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+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
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+#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
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+#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
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+#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
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+#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
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+#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
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+#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
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+#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
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+
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+/******************** Bit definition for RCC_AHB2LPENR register *************/
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+#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
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+#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
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+#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
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+#define RCC_AHB2LPENR_JPEGLPEN_Pos (1U)
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+#define RCC_AHB2LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB2LPENR_JPEGLPEN_Pos) /*!< 0x00000002 */
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+#define RCC_AHB2LPENR_JPEGLPEN RCC_AHB2LPENR_JPEGLPEN_Msk
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+#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
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+#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
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+#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
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+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
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+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
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+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
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+
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+/******************** Bit definition for RCC_AHB3LPENR register *************/
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+#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
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+#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
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+#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
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+#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
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+#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
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+#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
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+/******************** Bit definition for RCC_APB1LPENR register *************/
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+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
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+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
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+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
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+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
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+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
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+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
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+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
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+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
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+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
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+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
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+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
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+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
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+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
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+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
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+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
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+#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
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+#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
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+#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
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+#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
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+#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
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+#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
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+#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
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+#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
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+#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
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+#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
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+#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
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+#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
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+#define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
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+#define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
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+#define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
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+#define RCC_APB1LPENR_RTCLPEN_Pos (10U)
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+#define RCC_APB1LPENR_RTCLPEN_Msk (0x1UL << RCC_APB1LPENR_RTCLPEN_Pos) /*!< 0x00000400 */
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+#define RCC_APB1LPENR_RTCLPEN RCC_APB1LPENR_RTCLPEN_Msk
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+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
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+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
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+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
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+#define RCC_APB1LPENR_CAN3LPEN_Pos (13U)
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+#define RCC_APB1LPENR_CAN3LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN3LPEN_Pos) /*!< 0x00002000 */
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+#define RCC_APB1LPENR_CAN3LPEN RCC_APB1LPENR_CAN3LPEN_Msk
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+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
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+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
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+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
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+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
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+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
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+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
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+#define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U)
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+#define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
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+#define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk
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+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
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+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
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+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
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+#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
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+#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
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+#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
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+#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
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+#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
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+#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
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+#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
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+#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
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+#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
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+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
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+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
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+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
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+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
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+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
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+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
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+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
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+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
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+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
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+#define RCC_APB1LPENR_I2C4LPEN_Pos (24U)
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+#define RCC_APB1LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C4LPEN_Pos) /*!< 0x01000000 */
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+#define RCC_APB1LPENR_I2C4LPEN RCC_APB1LPENR_I2C4LPEN_Msk
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+#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
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+#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
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+#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
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+#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
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+#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
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+#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
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+#define RCC_APB1LPENR_CECLPEN_Pos (27U)
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+#define RCC_APB1LPENR_CECLPEN_Msk (0x1UL << RCC_APB1LPENR_CECLPEN_Pos) /*!< 0x08000000 */
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+#define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk
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+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
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+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
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+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
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+#define RCC_APB1LPENR_DACLPEN_Pos (29U)
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+#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
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+#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
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+#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
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+#define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
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+#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
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+#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
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+#define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
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+#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
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+
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+/******************** Bit definition for RCC_APB2LPENR register *************/
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+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
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+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
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+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
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+#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
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+#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
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+#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
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+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
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+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
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+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
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+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
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+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
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+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
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+#define RCC_APB2LPENR_SDMMC2LPEN_Pos (7U)
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+#define RCC_APB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */
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+#define RCC_APB2LPENR_SDMMC2LPEN RCC_APB2LPENR_SDMMC2LPEN_Msk
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+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
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+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
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+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
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+#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
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+#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
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+#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
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+#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
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+#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
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+#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
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+#define RCC_APB2LPENR_SDMMC1LPEN_Pos (11U)
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+#define RCC_APB2LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC1LPEN_Pos) /*!< 0x00000800 */
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+#define RCC_APB2LPENR_SDMMC1LPEN RCC_APB2LPENR_SDMMC1LPEN_Msk
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+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
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+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
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+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
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+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
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+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
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+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
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+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
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+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
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+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
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+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
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+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
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+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
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+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
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+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
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+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
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+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
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+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
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+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
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+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
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+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
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+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
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+#define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
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+#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
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+#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
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+#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
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+#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
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+#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
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+#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
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+#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
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+#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
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+#define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
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+#define RCC_APB2LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
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+#define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
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+#define RCC_APB2LPENR_DSILPEN_Pos (27U)
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+#define RCC_APB2LPENR_DSILPEN_Msk (0x1UL << RCC_APB2LPENR_DSILPEN_Pos) /*!< 0x08000000 */
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+#define RCC_APB2LPENR_DSILPEN RCC_APB2LPENR_DSILPEN_Msk
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+#define RCC_APB2LPENR_DFSDM1LPEN_Pos (29U)
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+#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x20000000 */
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+#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
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+#define RCC_APB2LPENR_MDIOLPEN_Pos (30U)
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+#define RCC_APB2LPENR_MDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_MDIOLPEN_Pos) /*!< 0x40000000 */
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+#define RCC_APB2LPENR_MDIOLPEN RCC_APB2LPENR_MDIOLPEN_Msk
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+
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+/******************** Bit definition for RCC_BDCR register ******************/
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+#define RCC_BDCR_LSEON_Pos (0U)
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+#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
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+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
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+#define RCC_BDCR_LSERDY_Pos (1U)
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+#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
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+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
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+#define RCC_BDCR_LSEBYP_Pos (2U)
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+#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
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+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
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+#define RCC_BDCR_LSEDRV_Pos (3U)
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+#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
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+#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
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+#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
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+#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
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+#define RCC_BDCR_RTCSEL_Pos (8U)
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+#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
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+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
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+#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
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+#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
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+#define RCC_BDCR_RTCEN_Pos (15U)
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+#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
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+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
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+#define RCC_BDCR_BDRST_Pos (16U)
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+#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
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+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
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+
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+/******************** Bit definition for RCC_CSR register *******************/
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+#define RCC_CSR_LSION_Pos (0U)
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+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
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+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
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+#define RCC_CSR_LSIRDY_Pos (1U)
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+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
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+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
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+#define RCC_CSR_RMVF_Pos (24U)
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+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
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+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
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+#define RCC_CSR_BORRSTF_Pos (25U)
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+#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
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+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
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|
|
+#define RCC_CSR_PINRSTF_Pos (26U)
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+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
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+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
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|
+#define RCC_CSR_PORRSTF_Pos (27U)
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+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
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|
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
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+#define RCC_CSR_SFTRSTF_Pos (28U)
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+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
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|
|
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
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+#define RCC_CSR_IWDGRSTF_Pos (29U)
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+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
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+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
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+#define RCC_CSR_WWDGRSTF_Pos (30U)
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+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
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+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
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+#define RCC_CSR_LPWRRSTF_Pos (31U)
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+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
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+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
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+
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+/******************** Bit definition for RCC_SSCGR register *****************/
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+#define RCC_SSCGR_MODPER_Pos (0U)
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+#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
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+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
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+#define RCC_SSCGR_INCSTEP_Pos (13U)
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+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
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+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
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+#define RCC_SSCGR_SPREADSEL_Pos (30U)
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+#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
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+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
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+#define RCC_SSCGR_SSCGEN_Pos (31U)
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+#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
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+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
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+
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+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
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|
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
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+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
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+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
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+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
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+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
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+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
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+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
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+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
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+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
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+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
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+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
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+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
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+#define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U)
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+#define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00030000 */
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+#define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk
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+#define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00010000 */
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+#define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00020000 */
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+#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
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+#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
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+#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
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|
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
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+#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
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+#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
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+#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
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|
|
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
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+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
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+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
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+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
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+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
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+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
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+
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+/******************** Bit definition for RCC_PLLSAICFGR register ************/
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|
|
+#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
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|
+#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
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|
|
+#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
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|
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+#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
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+#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
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+#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
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+#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
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+#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
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+#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
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+#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
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+#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
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+#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
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|
+#define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
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|
+#define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
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|
|
+#define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
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|
+#define RCC_PLLSAICFGR_PLLSAIP_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
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+#define RCC_PLLSAICFGR_PLLSAIP_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
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+#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
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+#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
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+#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
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+#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
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+#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
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+#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
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+#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
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+#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
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+#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
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+#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
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+#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
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+#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
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+#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
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+
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|
+/******************** Bit definition for RCC_DCKCFGR1 register ***************/
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|
+#define RCC_DCKCFGR1_PLLI2SDIVQ_Pos (0U)
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+#define RCC_DCKCFGR1_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
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|
+#define RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ_Msk
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+#define RCC_DCKCFGR1_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
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+#define RCC_DCKCFGR1_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
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+#define RCC_DCKCFGR1_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
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+#define RCC_DCKCFGR1_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
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|
+#define RCC_DCKCFGR1_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
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+
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|
+#define RCC_DCKCFGR1_PLLSAIDIVQ_Pos (8U)
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+#define RCC_DCKCFGR1_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
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|
+#define RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ_Msk
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|
+#define RCC_DCKCFGR1_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
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|
+#define RCC_DCKCFGR1_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
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+#define RCC_DCKCFGR1_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
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+#define RCC_DCKCFGR1_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
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|
+#define RCC_DCKCFGR1_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
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|
+
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|
|
+#define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U)
|
|
|
+#define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
|
|
|
+#define RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR_Msk
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|
|
+#define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
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|
+#define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
|
|
|
+
|
|
|
+/*
|
|
|
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
|
|
+ */
|
|
|
+#define RCC_SAI1SEL_PLLSRC_SUPPORT
|
|
|
+#define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
|
|
|
+#define RCC_DCKCFGR1_SAI1SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00300000 */
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|
|
+#define RCC_DCKCFGR1_SAI1SEL RCC_DCKCFGR1_SAI1SEL_Msk
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|
|
+#define RCC_DCKCFGR1_SAI1SEL_0 (0x1UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00100000 */
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|
|
+#define RCC_DCKCFGR1_SAI1SEL_1 (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00200000 */
|
|
|
+
|
|
|
+/*
|
|
|
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
|
|
+ */
|
|
|
+#define RCC_SAI2SEL_PLLSRC_SUPPORT
|
|
|
+#define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
|
|
|
+#define RCC_DCKCFGR1_SAI2SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00C00000 */
|
|
|
+#define RCC_DCKCFGR1_SAI2SEL RCC_DCKCFGR1_SAI2SEL_Msk
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|
|
+#define RCC_DCKCFGR1_SAI2SEL_0 (0x1UL << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00400000 */
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|
|
+#define RCC_DCKCFGR1_SAI2SEL_1 (0x2UL << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00800000 */
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|
+
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|
|
+#define RCC_DCKCFGR1_TIMPRE_Pos (24U)
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|
|
+#define RCC_DCKCFGR1_TIMPRE_Msk (0x1UL << RCC_DCKCFGR1_TIMPRE_Pos) /*!< 0x01000000 */
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|
|
+#define RCC_DCKCFGR1_TIMPRE RCC_DCKCFGR1_TIMPRE_Msk
|
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|
+#define RCC_DCKCFGR1_DFSDM1SEL_Pos (25U)
|
|
|
+#define RCC_DCKCFGR1_DFSDM1SEL_Msk (0x1UL << RCC_DCKCFGR1_DFSDM1SEL_Pos) /*!< 0x02000000 */
|
|
|
+#define RCC_DCKCFGR1_DFSDM1SEL RCC_DCKCFGR1_DFSDM1SEL_Msk
|
|
|
+#define RCC_DCKCFGR1_ADFSDM1SEL_Pos (26U)
|
|
|
+#define RCC_DCKCFGR1_ADFSDM1SEL_Msk (0x1UL << RCC_DCKCFGR1_ADFSDM1SEL_Pos) /*!< 0x04000000 */
|
|
|
+#define RCC_DCKCFGR1_ADFSDM1SEL RCC_DCKCFGR1_ADFSDM1SEL_Msk
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/
|
|
|
+#define RCC_DCKCFGR2_USART1SEL_Pos (0U)
|
|
|
+#define RCC_DCKCFGR2_USART1SEL_Msk (0x3UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000003 */
|
|
|
+#define RCC_DCKCFGR2_USART1SEL RCC_DCKCFGR2_USART1SEL_Msk
|
|
|
+#define RCC_DCKCFGR2_USART1SEL_0 (0x1UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000001 */
|
|
|
+#define RCC_DCKCFGR2_USART1SEL_1 (0x2UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000002 */
|
|
|
+#define RCC_DCKCFGR2_USART2SEL_Pos (2U)
|
|
|
+#define RCC_DCKCFGR2_USART2SEL_Msk (0x3UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x0000000C */
|
|
|
+#define RCC_DCKCFGR2_USART2SEL RCC_DCKCFGR2_USART2SEL_Msk
|
|
|
+#define RCC_DCKCFGR2_USART2SEL_0 (0x1UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000004 */
|
|
|
+#define RCC_DCKCFGR2_USART2SEL_1 (0x2UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000008 */
|
|
|
+#define RCC_DCKCFGR2_USART3SEL_Pos (4U)
|
|
|
+#define RCC_DCKCFGR2_USART3SEL_Msk (0x3UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000030 */
|
|
|
+#define RCC_DCKCFGR2_USART3SEL RCC_DCKCFGR2_USART3SEL_Msk
|
|
|
+#define RCC_DCKCFGR2_USART3SEL_0 (0x1UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000010 */
|
|
|
+#define RCC_DCKCFGR2_USART3SEL_1 (0x2UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000020 */
|
|
|
+#define RCC_DCKCFGR2_UART4SEL_Pos (6U)
|
|
|
+#define RCC_DCKCFGR2_UART4SEL_Msk (0x3UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x000000C0 */
|
|
|
+#define RCC_DCKCFGR2_UART4SEL RCC_DCKCFGR2_UART4SEL_Msk
|
|
|
+#define RCC_DCKCFGR2_UART4SEL_0 (0x1UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000040 */
|
|
|
+#define RCC_DCKCFGR2_UART4SEL_1 (0x2UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000080 */
|
|
|
+#define RCC_DCKCFGR2_UART5SEL_Pos (8U)
|
|
|
+#define RCC_DCKCFGR2_UART5SEL_Msk (0x3UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000300 */
|
|
|
+#define RCC_DCKCFGR2_UART5SEL RCC_DCKCFGR2_UART5SEL_Msk
|
|
|
+#define RCC_DCKCFGR2_UART5SEL_0 (0x1UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000100 */
|
|
|
+#define RCC_DCKCFGR2_UART5SEL_1 (0x2UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000200 */
|
|
|
+#define RCC_DCKCFGR2_USART6SEL_Pos (10U)
|
|
|
+#define RCC_DCKCFGR2_USART6SEL_Msk (0x3UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000C00 */
|
|
|
+#define RCC_DCKCFGR2_USART6SEL RCC_DCKCFGR2_USART6SEL_Msk
|
|
|
+#define RCC_DCKCFGR2_USART6SEL_0 (0x1UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000400 */
|
|
|
+#define RCC_DCKCFGR2_USART6SEL_1 (0x2UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000800 */
|
|
|
+#define RCC_DCKCFGR2_UART7SEL_Pos (12U)
|
|
|
+#define RCC_DCKCFGR2_UART7SEL_Msk (0x3UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00003000 */
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|
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+#define RCC_DCKCFGR2_UART7SEL RCC_DCKCFGR2_UART7SEL_Msk
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+#define RCC_DCKCFGR2_UART7SEL_0 (0x1UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00001000 */
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+#define RCC_DCKCFGR2_UART7SEL_1 (0x2UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00002000 */
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+#define RCC_DCKCFGR2_UART8SEL_Pos (14U)
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+#define RCC_DCKCFGR2_UART8SEL_Msk (0x3UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x0000C000 */
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|
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+#define RCC_DCKCFGR2_UART8SEL RCC_DCKCFGR2_UART8SEL_Msk
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+#define RCC_DCKCFGR2_UART8SEL_0 (0x1UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00004000 */
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+#define RCC_DCKCFGR2_UART8SEL_1 (0x2UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00008000 */
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|
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+#define RCC_DCKCFGR2_I2C1SEL_Pos (16U)
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+#define RCC_DCKCFGR2_I2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00030000 */
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|
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+#define RCC_DCKCFGR2_I2C1SEL RCC_DCKCFGR2_I2C1SEL_Msk
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+#define RCC_DCKCFGR2_I2C1SEL_0 (0x1UL << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00010000 */
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+#define RCC_DCKCFGR2_I2C1SEL_1 (0x2UL << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00020000 */
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|
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+#define RCC_DCKCFGR2_I2C2SEL_Pos (18U)
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+#define RCC_DCKCFGR2_I2C2SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x000C0000 */
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+#define RCC_DCKCFGR2_I2C2SEL RCC_DCKCFGR2_I2C2SEL_Msk
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+#define RCC_DCKCFGR2_I2C2SEL_0 (0x1UL << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00040000 */
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+#define RCC_DCKCFGR2_I2C2SEL_1 (0x2UL << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00080000 */
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+#define RCC_DCKCFGR2_I2C3SEL_Pos (20U)
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+#define RCC_DCKCFGR2_I2C3SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00300000 */
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+#define RCC_DCKCFGR2_I2C3SEL RCC_DCKCFGR2_I2C3SEL_Msk
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+#define RCC_DCKCFGR2_I2C3SEL_0 (0x1UL << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00100000 */
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+#define RCC_DCKCFGR2_I2C3SEL_1 (0x2UL << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00200000 */
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+#define RCC_DCKCFGR2_I2C4SEL_Pos (22U)
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+#define RCC_DCKCFGR2_I2C4SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00C00000 */
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+#define RCC_DCKCFGR2_I2C4SEL RCC_DCKCFGR2_I2C4SEL_Msk
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+#define RCC_DCKCFGR2_I2C4SEL_0 (0x1UL << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00400000 */
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+#define RCC_DCKCFGR2_I2C4SEL_1 (0x2UL << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00800000 */
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+#define RCC_DCKCFGR2_LPTIM1SEL_Pos (24U)
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+#define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x03000000 */
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+#define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
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+#define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x01000000 */
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+#define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x02000000 */
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+#define RCC_DCKCFGR2_CECSEL_Pos (26U)
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+#define RCC_DCKCFGR2_CECSEL_Msk (0x1UL << RCC_DCKCFGR2_CECSEL_Pos) /*!< 0x04000000 */
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+#define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk
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+#define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
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+#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
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+#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
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+#define RCC_DCKCFGR2_SDMMC1SEL_Pos (28U)
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+#define RCC_DCKCFGR2_SDMMC1SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC1SEL_Pos) /*!< 0x10000000 */
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+#define RCC_DCKCFGR2_SDMMC1SEL RCC_DCKCFGR2_SDMMC1SEL_Msk
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+#define RCC_DCKCFGR2_SDMMC2SEL_Pos (29U)
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+#define RCC_DCKCFGR2_SDMMC2SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC2SEL_Pos) /*!< 0x20000000 */
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+#define RCC_DCKCFGR2_SDMMC2SEL RCC_DCKCFGR2_SDMMC2SEL_Msk
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+#define RCC_DCKCFGR2_DSISEL_Pos (30U)
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+#define RCC_DCKCFGR2_DSISEL_Msk (0x1UL << RCC_DCKCFGR2_DSISEL_Pos) /*!< 0x40000000 */
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+#define RCC_DCKCFGR2_DSISEL RCC_DCKCFGR2_DSISEL_Msk
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+
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+/******************************************************************************/
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|
+/* */
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|
+/* RNG */
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+/* */
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+/******************************************************************************/
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|
+/******************** Bits definition for RNG_CR register *******************/
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+#define RNG_CR_RNGEN_Pos (2U)
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+#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
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+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
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|
+#define RNG_CR_IE_Pos (3U)
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+#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
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+#define RNG_CR_IE RNG_CR_IE_Msk
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+
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|
|
+/******************** Bits definition for RNG_SR register *******************/
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+#define RNG_SR_DRDY_Pos (0U)
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+#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
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+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
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+#define RNG_SR_CECS_Pos (1U)
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+#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
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+#define RNG_SR_CECS RNG_SR_CECS_Msk
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|
+#define RNG_SR_SECS_Pos (2U)
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+#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
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|
+#define RNG_SR_SECS RNG_SR_SECS_Msk
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+#define RNG_SR_CEIS_Pos (5U)
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+#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
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|
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
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|
+#define RNG_SR_SEIS_Pos (6U)
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+#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
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+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
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+
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|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Real-Time Clock (RTC) */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************** Bits definition for RTC_TR register *******************/
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|
|
+#define RTC_TR_PM_Pos (22U)
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|
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
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|
+#define RTC_TR_PM RTC_TR_PM_Msk
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|
+#define RTC_TR_HT_Pos (20U)
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+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
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+#define RTC_TR_HT RTC_TR_HT_Msk
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+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
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+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
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|
+#define RTC_TR_HU_Pos (16U)
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|
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
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|
+#define RTC_TR_HU RTC_TR_HU_Msk
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|
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
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|
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
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+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
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+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
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+#define RTC_TR_MNT_Pos (12U)
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+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
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+#define RTC_TR_MNT RTC_TR_MNT_Msk
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+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
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+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
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+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
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+#define RTC_TR_MNU_Pos (8U)
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+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
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+#define RTC_TR_MNU RTC_TR_MNU_Msk
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+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
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+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
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+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
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+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
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+#define RTC_TR_ST_Pos (4U)
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+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
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|
+#define RTC_TR_ST RTC_TR_ST_Msk
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+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
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+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
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+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
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+#define RTC_TR_SU_Pos (0U)
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+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
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|
+#define RTC_TR_SU RTC_TR_SU_Msk
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+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
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+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
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+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
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|
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
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|
+
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|
|
+/******************** Bits definition for RTC_DR register *******************/
|
|
|
+#define RTC_DR_YT_Pos (20U)
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|
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
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|
+#define RTC_DR_YT RTC_DR_YT_Msk
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|
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
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|
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
|
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+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
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|
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
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|
+#define RTC_DR_YU_Pos (16U)
|
|
|
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
|
|
|
+#define RTC_DR_YU RTC_DR_YU_Msk
|
|
|
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
|
|
|
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
|
|
|
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
|
|
|
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
|
|
|
+#define RTC_DR_WDU_Pos (13U)
|
|
|
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
|
|
|
+#define RTC_DR_WDU RTC_DR_WDU_Msk
|
|
|
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
|
|
|
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
|
|
|
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
|
|
|
+#define RTC_DR_MT_Pos (12U)
|
|
|
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
|
|
|
+#define RTC_DR_MT RTC_DR_MT_Msk
|
|
|
+#define RTC_DR_MU_Pos (8U)
|
|
|
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
|
|
|
+#define RTC_DR_MU RTC_DR_MU_Msk
|
|
|
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
|
|
|
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
|
|
|
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
|
|
|
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
|
|
|
+#define RTC_DR_DT_Pos (4U)
|
|
|
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
|
|
|
+#define RTC_DR_DT RTC_DR_DT_Msk
|
|
|
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
|
|
|
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
|
|
|
+#define RTC_DR_DU_Pos (0U)
|
|
|
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
|
|
|
+#define RTC_DR_DU RTC_DR_DU_Msk
|
|
|
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
|
|
|
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
|
|
|
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
|
|
|
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_CR register *******************/
|
|
|
+#define RTC_CR_ITSE_Pos (24U)
|
|
|
+#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
|
|
|
+#define RTC_CR_ITSE RTC_CR_ITSE_Msk
|
|
|
+#define RTC_CR_COE_Pos (23U)
|
|
|
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
|
|
|
+#define RTC_CR_COE RTC_CR_COE_Msk
|
|
|
+#define RTC_CR_OSEL_Pos (21U)
|
|
|
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
|
|
|
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
|
|
|
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
|
|
|
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
|
|
|
+#define RTC_CR_POL_Pos (20U)
|
|
|
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
|
|
|
+#define RTC_CR_POL RTC_CR_POL_Msk
|
|
|
+#define RTC_CR_COSEL_Pos (19U)
|
|
|
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
|
|
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
|
|
+#define RTC_CR_BKP_Pos (18U)
|
|
|
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
|
|
+#define RTC_CR_BKP RTC_CR_BKP_Msk
|
|
|
+#define RTC_CR_SUB1H_Pos (17U)
|
|
|
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
|
|
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
|
|
+#define RTC_CR_ADD1H_Pos (16U)
|
|
|
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
|
|
|
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
|
|
|
+#define RTC_CR_TSIE_Pos (15U)
|
|
|
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
|
|
|
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
|
|
|
+#define RTC_CR_WUTIE_Pos (14U)
|
|
|
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
|
|
|
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
|
|
|
+#define RTC_CR_ALRBIE_Pos (13U)
|
|
|
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
|
|
|
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
|
|
|
+#define RTC_CR_ALRAIE_Pos (12U)
|
|
|
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
|
|
|
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
|
|
|
+#define RTC_CR_TSE_Pos (11U)
|
|
|
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
|
|
|
+#define RTC_CR_TSE RTC_CR_TSE_Msk
|
|
|
+#define RTC_CR_WUTE_Pos (10U)
|
|
|
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
|
|
|
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
|
|
|
+#define RTC_CR_ALRBE_Pos (9U)
|
|
|
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
|
|
|
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
|
|
|
+#define RTC_CR_ALRAE_Pos (8U)
|
|
|
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
|
|
|
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
|
|
|
+#define RTC_CR_FMT_Pos (6U)
|
|
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+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
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+#define RTC_CR_FMT RTC_CR_FMT_Msk
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+#define RTC_CR_BYPSHAD_Pos (5U)
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+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
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+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
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+#define RTC_CR_REFCKON_Pos (4U)
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+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
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+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
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+#define RTC_CR_TSEDGE_Pos (3U)
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+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
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+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
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+#define RTC_CR_WUCKSEL_Pos (0U)
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+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
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+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
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+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
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+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
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+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
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+
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+/* Legacy define */
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+#define RTC_CR_BCK RTC_CR_BKP
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+
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+/******************** Bits definition for RTC_ISR register ******************/
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+#define RTC_ISR_ITSF_Pos (17U)
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+#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
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+#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
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+#define RTC_ISR_RECALPF_Pos (16U)
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+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
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+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
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+#define RTC_ISR_TAMP3F_Pos (15U)
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+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
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+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
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+#define RTC_ISR_TAMP2F_Pos (14U)
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+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
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+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
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+#define RTC_ISR_TAMP1F_Pos (13U)
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+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
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+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
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+#define RTC_ISR_TSOVF_Pos (12U)
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+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
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+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
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+#define RTC_ISR_TSF_Pos (11U)
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+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
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+#define RTC_ISR_TSF RTC_ISR_TSF_Msk
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+#define RTC_ISR_WUTF_Pos (10U)
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+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
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+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
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+#define RTC_ISR_ALRBF_Pos (9U)
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+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
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+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
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+#define RTC_ISR_ALRAF_Pos (8U)
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+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
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+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
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+#define RTC_ISR_INIT_Pos (7U)
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+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
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+#define RTC_ISR_INIT RTC_ISR_INIT_Msk
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+#define RTC_ISR_INITF_Pos (6U)
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+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
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+#define RTC_ISR_INITF RTC_ISR_INITF_Msk
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+#define RTC_ISR_RSF_Pos (5U)
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+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
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+#define RTC_ISR_RSF RTC_ISR_RSF_Msk
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+#define RTC_ISR_INITS_Pos (4U)
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+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
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+#define RTC_ISR_INITS RTC_ISR_INITS_Msk
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+#define RTC_ISR_SHPF_Pos (3U)
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+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
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+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
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+#define RTC_ISR_WUTWF_Pos (2U)
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+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
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+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
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+#define RTC_ISR_ALRBWF_Pos (1U)
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+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
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+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
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+#define RTC_ISR_ALRAWF_Pos (0U)
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+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
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+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
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+
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+/******************** Bits definition for RTC_PRER register *****************/
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+#define RTC_PRER_PREDIV_A_Pos (16U)
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+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
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+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
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+#define RTC_PRER_PREDIV_S_Pos (0U)
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+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
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+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
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+
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+/******************** Bits definition for RTC_WUTR register *****************/
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+#define RTC_WUTR_WUT_Pos (0U)
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+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
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+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
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+
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+/******************** Bits definition for RTC_ALRMAR register ***************/
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+#define RTC_ALRMAR_MSK4_Pos (31U)
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+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
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+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
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+#define RTC_ALRMAR_WDSEL_Pos (30U)
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+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
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+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
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+#define RTC_ALRMAR_DT_Pos (28U)
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+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
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+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
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+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
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+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
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+#define RTC_ALRMAR_DU_Pos (24U)
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+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
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+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
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+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
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+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
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+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
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+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
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+#define RTC_ALRMAR_MSK3_Pos (23U)
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+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
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+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
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+#define RTC_ALRMAR_PM_Pos (22U)
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+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
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+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
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+#define RTC_ALRMAR_HT_Pos (20U)
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+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
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+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
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+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
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+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
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+#define RTC_ALRMAR_HU_Pos (16U)
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+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
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+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
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+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
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+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
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+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
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+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
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+#define RTC_ALRMAR_MSK2_Pos (15U)
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+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
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+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
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+#define RTC_ALRMAR_MNT_Pos (12U)
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+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
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+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
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+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
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+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
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+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
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+#define RTC_ALRMAR_MNU_Pos (8U)
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+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
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+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
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+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
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+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
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+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
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+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
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+#define RTC_ALRMAR_MSK1_Pos (7U)
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+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
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+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
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+#define RTC_ALRMAR_ST_Pos (4U)
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+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
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+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
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+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
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+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
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+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
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+#define RTC_ALRMAR_SU_Pos (0U)
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+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
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+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
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+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
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+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
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+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
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+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
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+
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+/******************** Bits definition for RTC_ALRMBR register ***************/
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+#define RTC_ALRMBR_MSK4_Pos (31U)
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+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
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+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
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+#define RTC_ALRMBR_WDSEL_Pos (30U)
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+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
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+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
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+#define RTC_ALRMBR_DT_Pos (28U)
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+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
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+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
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+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
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+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
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+#define RTC_ALRMBR_DU_Pos (24U)
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+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
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+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
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+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
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+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
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+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
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+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
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+#define RTC_ALRMBR_MSK3_Pos (23U)
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+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
|
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|
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
|
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+#define RTC_ALRMBR_PM_Pos (22U)
|
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+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
|
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|
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
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+#define RTC_ALRMBR_HT_Pos (20U)
|
|
|
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
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|
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
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+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
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+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
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|
+#define RTC_ALRMBR_HU_Pos (16U)
|
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+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
|
|
|
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
|
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|
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
|
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|
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
|
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+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
|
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|
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
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+#define RTC_ALRMBR_MSK2_Pos (15U)
|
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|
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
|
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|
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
|
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|
+#define RTC_ALRMBR_MNT_Pos (12U)
|
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|
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
|
|
|
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
|
|
|
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
|
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|
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
|
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|
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
|
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|
+#define RTC_ALRMBR_MNU_Pos (8U)
|
|
|
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
|
|
|
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
|
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|
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
|
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|
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
|
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|
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
|
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|
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
|
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|
+#define RTC_ALRMBR_MSK1_Pos (7U)
|
|
|
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
|
|
|
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
|
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|
+#define RTC_ALRMBR_ST_Pos (4U)
|
|
|
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
|
|
|
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
|
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|
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
|
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+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
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+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
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+#define RTC_ALRMBR_SU_Pos (0U)
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+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
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+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
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+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
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+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
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+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
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+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
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+
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+/******************** Bits definition for RTC_WPR register ******************/
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+#define RTC_WPR_KEY_Pos (0U)
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+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
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+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
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+
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+/******************** Bits definition for RTC_SSR register ******************/
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+#define RTC_SSR_SS_Pos (0U)
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+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
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+#define RTC_SSR_SS RTC_SSR_SS_Msk
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+
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+/******************** Bits definition for RTC_SHIFTR register ***************/
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+#define RTC_SHIFTR_SUBFS_Pos (0U)
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+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
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+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
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+#define RTC_SHIFTR_ADD1S_Pos (31U)
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+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
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+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
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+
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+/******************** Bits definition for RTC_TSTR register *****************/
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+#define RTC_TSTR_PM_Pos (22U)
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+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
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+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
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+#define RTC_TSTR_HT_Pos (20U)
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+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
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+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
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+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
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+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
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+#define RTC_TSTR_HU_Pos (16U)
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+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
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+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
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+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
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+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
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+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
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+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
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+#define RTC_TSTR_MNT_Pos (12U)
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+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
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+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
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+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
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+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
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+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
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+#define RTC_TSTR_MNU_Pos (8U)
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+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
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+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
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+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
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+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
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+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
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+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
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+#define RTC_TSTR_ST_Pos (4U)
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+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
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+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
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+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
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+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
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+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
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+#define RTC_TSTR_SU_Pos (0U)
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+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
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+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
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+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
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+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
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+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
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+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
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+
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+/******************** Bits definition for RTC_TSDR register *****************/
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+#define RTC_TSDR_WDU_Pos (13U)
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+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
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+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
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+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
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+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
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+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
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+#define RTC_TSDR_MT_Pos (12U)
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+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
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+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
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+#define RTC_TSDR_MU_Pos (8U)
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+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
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+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
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+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
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+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
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+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
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+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
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+#define RTC_TSDR_DT_Pos (4U)
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+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
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+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
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+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
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+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
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+#define RTC_TSDR_DU_Pos (0U)
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+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
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+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
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+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
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+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
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+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
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+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
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+
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+/******************** Bits definition for RTC_TSSSR register ****************/
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+#define RTC_TSSSR_SS_Pos (0U)
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+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
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+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
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+
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+/******************** Bits definition for RTC_CAL register *****************/
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+#define RTC_CALR_CALP_Pos (15U)
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+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
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+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
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+#define RTC_CALR_CALW8_Pos (14U)
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+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
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+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
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+#define RTC_CALR_CALW16_Pos (13U)
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+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
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+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
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+#define RTC_CALR_CALM_Pos (0U)
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+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
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+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
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+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
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+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
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+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
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+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
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+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
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+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
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+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
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+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
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+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
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+
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+/******************** Bits definition for RTC_TAMPCR register ****************/
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+#define RTC_TAMPCR_TAMP3MF_Pos (24U)
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+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
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+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
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+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
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+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
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+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
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+#define RTC_TAMPCR_TAMP3IE_Pos (22U)
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+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
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+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
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+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
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+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
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+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
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+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
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+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
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+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
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+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
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+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
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+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
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+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
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+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
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+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
|
|
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+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
|
|
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+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
|
|
|
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
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+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
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+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
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+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
|
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+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
|
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+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
|
|
|
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
|
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+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
|
|
|
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
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+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
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+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
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+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
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|
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+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
|
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+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
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+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
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+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
|
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+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
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+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
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+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
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+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
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+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
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+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
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+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
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+#define RTC_TAMPCR_TAMPTS_Pos (7U)
|
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+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
|
|
|
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
|
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+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
|
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+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
|
|
|
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
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+#define RTC_TAMPCR_TAMP3E_Pos (5U)
|
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+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
|
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+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
|
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+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
|
|
|
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
|
|
|
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
|
|
|
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
|
|
|
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
|
|
|
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
|
|
|
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
|
|
|
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
|
|
|
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
|
|
|
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
|
|
|
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
|
|
|
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
|
|
|
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
|
|
|
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
|
|
|
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
|
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+
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+
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|
|
+/******************** Bits definition for RTC_ALRMASSR register *************/
|
|
|
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
|
|
|
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
|
|
|
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
|
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|
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
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|
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
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|
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
|
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|
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
|
|
|
+#define RTC_ALRMASSR_SS_Pos (0U)
|
|
|
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
|
|
|
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
|
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+
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|
|
+/******************** Bits definition for RTC_ALRMBSSR register *************/
|
|
|
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
|
|
|
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
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|
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+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
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+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
|
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+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
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+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
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+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
|
|
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+#define RTC_ALRMBSSR_SS_Pos (0U)
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|
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+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
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|
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+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
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+
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|
|
+/******************** Bits definition for RTC_OR register ****************/
|
|
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+#define RTC_OR_TSINSEL_Pos (1U)
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+#define RTC_OR_TSINSEL_Msk (0x3UL << RTC_OR_TSINSEL_Pos) /*!< 0x00000006 */
|
|
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+#define RTC_OR_TSINSEL RTC_OR_TSINSEL_Msk
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+#define RTC_OR_TSINSEL_0 (0x1UL << RTC_OR_TSINSEL_Pos) /*!< 0x00000002 */
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+#define RTC_OR_TSINSEL_1 (0x2UL << RTC_OR_TSINSEL_Pos) /*!< 0x00000004 */
|
|
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+#define RTC_OR_ALARMOUTTYPE_Pos (3U)
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+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000008 */
|
|
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+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
|
|
|
+/* Legacy defines*/
|
|
|
+#define RTC_OR_ALARMTYPE RTC_OR_ALARMOUTTYPE
|
|
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+
|
|
|
+/******************** Bits definition for RTC_BKP0R register ****************/
|
|
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+#define RTC_BKP0R_Pos (0U)
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+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
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+#define RTC_BKP0R RTC_BKP0R_Msk
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+
|
|
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+/******************** Bits definition for RTC_BKP1R register ****************/
|
|
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+#define RTC_BKP1R_Pos (0U)
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+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
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|
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+#define RTC_BKP1R RTC_BKP1R_Msk
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+
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|
|
+/******************** Bits definition for RTC_BKP2R register ****************/
|
|
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+#define RTC_BKP2R_Pos (0U)
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+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
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+#define RTC_BKP2R RTC_BKP2R_Msk
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+
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|
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+/******************** Bits definition for RTC_BKP3R register ****************/
|
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+#define RTC_BKP3R_Pos (0U)
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+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
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+#define RTC_BKP3R RTC_BKP3R_Msk
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+
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|
|
+/******************** Bits definition for RTC_BKP4R register ****************/
|
|
|
+#define RTC_BKP4R_Pos (0U)
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+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
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+#define RTC_BKP4R RTC_BKP4R_Msk
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+
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|
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+/******************** Bits definition for RTC_BKP5R register ****************/
|
|
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+#define RTC_BKP5R_Pos (0U)
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+#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
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+#define RTC_BKP5R RTC_BKP5R_Msk
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+
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|
|
+/******************** Bits definition for RTC_BKP6R register ****************/
|
|
|
+#define RTC_BKP6R_Pos (0U)
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+#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
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+#define RTC_BKP6R RTC_BKP6R_Msk
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+
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|
|
+/******************** Bits definition for RTC_BKP7R register ****************/
|
|
|
+#define RTC_BKP7R_Pos (0U)
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+#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
|
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+#define RTC_BKP7R RTC_BKP7R_Msk
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+
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|
|
+/******************** Bits definition for RTC_BKP8R register ****************/
|
|
|
+#define RTC_BKP8R_Pos (0U)
|
|
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+#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
|
|
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+#define RTC_BKP8R RTC_BKP8R_Msk
|
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+
|
|
|
+/******************** Bits definition for RTC_BKP9R register ****************/
|
|
|
+#define RTC_BKP9R_Pos (0U)
|
|
|
+#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP9R RTC_BKP9R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP10R register ***************/
|
|
|
+#define RTC_BKP10R_Pos (0U)
|
|
|
+#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP10R RTC_BKP10R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP11R register ***************/
|
|
|
+#define RTC_BKP11R_Pos (0U)
|
|
|
+#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP11R RTC_BKP11R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP12R register ***************/
|
|
|
+#define RTC_BKP12R_Pos (0U)
|
|
|
+#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP12R RTC_BKP12R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP13R register ***************/
|
|
|
+#define RTC_BKP13R_Pos (0U)
|
|
|
+#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP13R RTC_BKP13R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP14R register ***************/
|
|
|
+#define RTC_BKP14R_Pos (0U)
|
|
|
+#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP14R RTC_BKP14R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP15R register ***************/
|
|
|
+#define RTC_BKP15R_Pos (0U)
|
|
|
+#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP15R RTC_BKP15R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP16R register ***************/
|
|
|
+#define RTC_BKP16R_Pos (0U)
|
|
|
+#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP16R RTC_BKP16R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP17R register ***************/
|
|
|
+#define RTC_BKP17R_Pos (0U)
|
|
|
+#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP17R RTC_BKP17R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP18R register ***************/
|
|
|
+#define RTC_BKP18R_Pos (0U)
|
|
|
+#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP18R RTC_BKP18R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP19R register ***************/
|
|
|
+#define RTC_BKP19R_Pos (0U)
|
|
|
+#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP19R RTC_BKP19R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP20R register ***************/
|
|
|
+#define RTC_BKP20R_Pos (0U)
|
|
|
+#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP20R RTC_BKP20R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP21R register ***************/
|
|
|
+#define RTC_BKP21R_Pos (0U)
|
|
|
+#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP21R RTC_BKP21R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP22R register ***************/
|
|
|
+#define RTC_BKP22R_Pos (0U)
|
|
|
+#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP22R RTC_BKP22R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP23R register ***************/
|
|
|
+#define RTC_BKP23R_Pos (0U)
|
|
|
+#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP23R RTC_BKP23R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP24R register ***************/
|
|
|
+#define RTC_BKP24R_Pos (0U)
|
|
|
+#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP24R RTC_BKP24R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP25R register ***************/
|
|
|
+#define RTC_BKP25R_Pos (0U)
|
|
|
+#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP25R RTC_BKP25R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP26R register ***************/
|
|
|
+#define RTC_BKP26R_Pos (0U)
|
|
|
+#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP26R RTC_BKP26R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP27R register ***************/
|
|
|
+#define RTC_BKP27R_Pos (0U)
|
|
|
+#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP27R RTC_BKP27R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP28R register ***************/
|
|
|
+#define RTC_BKP28R_Pos (0U)
|
|
|
+#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP28R RTC_BKP28R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP29R register ***************/
|
|
|
+#define RTC_BKP29R_Pos (0U)
|
|
|
+#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP29R RTC_BKP29R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP30R register ***************/
|
|
|
+#define RTC_BKP30R_Pos (0U)
|
|
|
+#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP30R RTC_BKP30R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_BKP31R register ***************/
|
|
|
+#define RTC_BKP31R_Pos (0U)
|
|
|
+#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define RTC_BKP31R RTC_BKP31R_Msk
|
|
|
+
|
|
|
+/******************** Number of backup registers ******************************/
|
|
|
+#define RTC_BKP_NUMBER 0x00000020U
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Serial Audio Interface */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************** Bit definition for SAI_GCR register *******************/
|
|
|
+#define SAI_GCR_SYNCIN_Pos (0U)
|
|
|
+#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
|
|
|
+#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
|
|
|
+#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
|
|
|
+#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
|
|
|
+
|
|
|
+#define SAI_GCR_SYNCOUT_Pos (4U)
|
|
|
+#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
|
|
|
+#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
|
|
|
+#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
|
|
|
+#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
|
|
|
+
|
|
|
+/******************* Bit definition for SAI_xCR1 register *******************/
|
|
|
+#define SAI_xCR1_MODE_Pos (0U)
|
|
|
+#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
|
|
|
+#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
|
|
|
+#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
|
|
|
+#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
|
|
|
+
|
|
|
+#define SAI_xCR1_PRTCFG_Pos (2U)
|
|
|
+#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
|
|
|
+#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
|
|
|
+#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
|
|
|
+#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
|
|
|
+
|
|
|
+#define SAI_xCR1_DS_Pos (5U)
|
|
|
+#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
|
|
|
+#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
|
|
|
+#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
|
|
|
+#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
|
|
|
+#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
|
|
|
+
|
|
|
+#define SAI_xCR1_LSBFIRST_Pos (8U)
|
|
|
+#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
|
|
|
+#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
|
|
|
+#define SAI_xCR1_CKSTR_Pos (9U)
|
|
|
+#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
|
|
|
+#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
|
|
|
+
|
|
|
+#define SAI_xCR1_SYNCEN_Pos (10U)
|
|
|
+#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
|
|
|
+#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
|
|
|
+#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
|
|
|
+#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
|
|
|
+
|
|
|
+#define SAI_xCR1_MONO_Pos (12U)
|
|
|
+#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
|
|
|
+#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
|
|
|
+#define SAI_xCR1_OUTDRIV_Pos (13U)
|
|
|
+#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
|
|
|
+#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
|
|
|
+#define SAI_xCR1_SAIEN_Pos (16U)
|
|
|
+#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
|
|
|
+#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
|
|
|
+#define SAI_xCR1_DMAEN_Pos (17U)
|
|
|
+#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
|
|
|
+#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
|
|
|
+#define SAI_xCR1_NODIV_Pos (19U)
|
|
|
+#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
|
|
|
+#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
|
|
|
+
|
|
|
+#define SAI_xCR1_MCKDIV_Pos (20U)
|
|
|
+#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
|
|
|
+#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
|
|
|
+#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
|
|
|
+#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
|
|
|
+#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
|
|
|
+#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
|
|
|
+
|
|
|
+/******************* Bit definition for SAI_xCR2 register *******************/
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+#define SAI_xCR2_FTH_Pos (0U)
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+#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
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+#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
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+#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
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+#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
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+#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
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+
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+#define SAI_xCR2_FFLUSH_Pos (3U)
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+#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
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+#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
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+#define SAI_xCR2_TRIS_Pos (4U)
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+#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
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+#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
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+#define SAI_xCR2_MUTE_Pos (5U)
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+#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
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+#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
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+#define SAI_xCR2_MUTEVAL_Pos (6U)
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+#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
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+#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
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+
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+#define SAI_xCR2_MUTECNT_Pos (7U)
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+#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
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+#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
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+#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
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+#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
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+#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
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+#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
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+#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
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+#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
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+
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+#define SAI_xCR2_CPL_Pos (13U)
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+#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
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+#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
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+
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+#define SAI_xCR2_COMP_Pos (14U)
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+#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
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+#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
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+#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
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+#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
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+
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+/****************** Bit definition for SAI_xFRCR register *******************/
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+#define SAI_xFRCR_FRL_Pos (0U)
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+#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
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+#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
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+#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
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+#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
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+#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
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+#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
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+#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
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+#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
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+#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
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+#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
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+
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+#define SAI_xFRCR_FSALL_Pos (8U)
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+#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
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+#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
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+#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
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+#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
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+#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
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+#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
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+#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
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+#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
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+#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
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+
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+#define SAI_xFRCR_FSDEF_Pos (16U)
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+#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
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+#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
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+#define SAI_xFRCR_FSPOL_Pos (17U)
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+#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
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+#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
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+#define SAI_xFRCR_FSOFF_Pos (18U)
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+#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
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+#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
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+
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+/* Legacy define */
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+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
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+
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+/****************** Bit definition for SAI_xSLOTR register *******************/
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+#define SAI_xSLOTR_FBOFF_Pos (0U)
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+#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
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+#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
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+#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
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+#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
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+#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
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+#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
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+#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
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+
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+#define SAI_xSLOTR_SLOTSZ_Pos (6U)
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+#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
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+#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
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+#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
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+#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
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+
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+#define SAI_xSLOTR_NBSLOT_Pos (8U)
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+#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
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+#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
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+#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
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+#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
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+#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
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+#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
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+
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+#define SAI_xSLOTR_SLOTEN_Pos (16U)
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+#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
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+#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
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+
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+/******************* Bit definition for SAI_xIMR register *******************/
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+#define SAI_xIMR_OVRUDRIE_Pos (0U)
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+#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
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+#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
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+#define SAI_xIMR_MUTEDETIE_Pos (1U)
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+#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
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+#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
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+#define SAI_xIMR_WCKCFGIE_Pos (2U)
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+#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
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+#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
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+#define SAI_xIMR_FREQIE_Pos (3U)
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+#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
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+#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
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+#define SAI_xIMR_CNRDYIE_Pos (4U)
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+#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
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+#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
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+#define SAI_xIMR_AFSDETIE_Pos (5U)
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+#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
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+#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
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+#define SAI_xIMR_LFSDETIE_Pos (6U)
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+#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
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+#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
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+
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+/******************** Bit definition for SAI_xSR register *******************/
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+#define SAI_xSR_OVRUDR_Pos (0U)
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+#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
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+#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
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+#define SAI_xSR_MUTEDET_Pos (1U)
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+#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
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+#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
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+#define SAI_xSR_WCKCFG_Pos (2U)
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+#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
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+#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
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+#define SAI_xSR_FREQ_Pos (3U)
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+#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
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+#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
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+#define SAI_xSR_CNRDY_Pos (4U)
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+#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
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+#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
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+#define SAI_xSR_AFSDET_Pos (5U)
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+#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
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+#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
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+#define SAI_xSR_LFSDET_Pos (6U)
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+#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
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+#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
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+
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+#define SAI_xSR_FLVL_Pos (16U)
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+#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
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+#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
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+#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
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+#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
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+#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
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+
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+/****************** Bit definition for SAI_xCLRFR register ******************/
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+#define SAI_xCLRFR_COVRUDR_Pos (0U)
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+#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
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+#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
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+#define SAI_xCLRFR_CMUTEDET_Pos (1U)
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+#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
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+#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
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+#define SAI_xCLRFR_CWCKCFG_Pos (2U)
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+#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
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+#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
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+#define SAI_xCLRFR_CFREQ_Pos (3U)
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+#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
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+#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
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+#define SAI_xCLRFR_CCNRDY_Pos (4U)
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+#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
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+#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
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+#define SAI_xCLRFR_CAFSDET_Pos (5U)
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+#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
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+#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
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+#define SAI_xCLRFR_CLFSDET_Pos (6U)
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+#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
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+#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
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+
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+/****************** Bit definition for SAI_xDR register *********************/
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+#define SAI_xDR_DATA_Pos (0U)
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+#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
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+#define SAI_xDR_DATA SAI_xDR_DATA_Msk
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+
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+/******************************************************************************/
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+/* */
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+/* SPDIF-RX Interface */
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+/* */
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+/******************************************************************************/
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+/******************** Bit definition for SPDIF_CR register *******************/
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+#define SPDIFRX_CR_SPDIFEN_Pos (0U)
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+#define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
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+#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
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+#define SPDIFRX_CR_RXDMAEN_Pos (2U)
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+#define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
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+#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
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+#define SPDIFRX_CR_RXSTEO_Pos (3U)
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+#define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
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+#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
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+#define SPDIFRX_CR_DRFMT_Pos (4U)
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+#define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
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+#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
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+#define SPDIFRX_CR_PMSK_Pos (6U)
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+#define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
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+#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
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+#define SPDIFRX_CR_VMSK_Pos (7U)
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+#define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
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+#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
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+#define SPDIFRX_CR_CUMSK_Pos (8U)
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+#define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
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+#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
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+#define SPDIFRX_CR_PTMSK_Pos (9U)
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+#define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
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+#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
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+#define SPDIFRX_CR_CBDMAEN_Pos (10U)
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+#define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
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+#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
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+#define SPDIFRX_CR_CHSEL_Pos (11U)
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+#define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
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+#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
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+#define SPDIFRX_CR_NBTR_Pos (12U)
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+#define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
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+#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
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+#define SPDIFRX_CR_WFA_Pos (14U)
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+#define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
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+#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
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+#define SPDIFRX_CR_INSEL_Pos (16U)
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+#define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
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+#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
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+
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+/******************* Bit definition for SPDIFRX_IMR register *******************/
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+#define SPDIFRX_IMR_RXNEIE_Pos (0U)
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+#define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
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+#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
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+#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
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+#define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
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+#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
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+#define SPDIFRX_IMR_PERRIE_Pos (2U)
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+#define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
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+#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
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+#define SPDIFRX_IMR_OVRIE_Pos (3U)
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+#define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
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+#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
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+#define SPDIFRX_IMR_SBLKIE_Pos (4U)
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+#define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
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+#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
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+#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
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+#define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
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+#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
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+#define SPDIFRX_IMR_IFEIE_Pos (6U)
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+#define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
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+#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
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+
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+/******************* Bit definition for SPDIFRX_SR register *******************/
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+#define SPDIFRX_SR_RXNE_Pos (0U)
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+#define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
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+#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
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+#define SPDIFRX_SR_CSRNE_Pos (1U)
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+#define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
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+#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
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+#define SPDIFRX_SR_PERR_Pos (2U)
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+#define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
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+#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
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+#define SPDIFRX_SR_OVR_Pos (3U)
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+#define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
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+#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
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+#define SPDIFRX_SR_SBD_Pos (4U)
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+#define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
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+#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
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+#define SPDIFRX_SR_SYNCD_Pos (5U)
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+#define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
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+#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
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+#define SPDIFRX_SR_FERR_Pos (6U)
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+#define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
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+#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
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+#define SPDIFRX_SR_SERR_Pos (7U)
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+#define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
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+#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
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+#define SPDIFRX_SR_TERR_Pos (8U)
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+#define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
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+#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
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+#define SPDIFRX_SR_WIDTH5_Pos (16U)
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+#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
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+#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
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+
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+/******************* Bit definition for SPDIFRX_IFCR register *******************/
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+#define SPDIFRX_IFCR_PERRCF_Pos (2U)
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+#define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
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+#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
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+#define SPDIFRX_IFCR_OVRCF_Pos (3U)
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+#define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
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+#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
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+#define SPDIFRX_IFCR_SBDCF_Pos (4U)
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+#define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
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+#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
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+#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
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+#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
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+#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
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+
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+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
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+#define SPDIFRX_DR0_DR_Pos (0U)
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+#define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
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+#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
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+#define SPDIFRX_DR0_PE_Pos (24U)
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+#define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
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+#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
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+#define SPDIFRX_DR0_V_Pos (25U)
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+#define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
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+#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
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+#define SPDIFRX_DR0_U_Pos (26U)
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+#define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
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+#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
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+#define SPDIFRX_DR0_C_Pos (27U)
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+#define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
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+#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
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+#define SPDIFRX_DR0_PT_Pos (28U)
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+#define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
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+#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
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+
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+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
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+#define SPDIFRX_DR1_DR_Pos (8U)
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+#define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
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+#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
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+#define SPDIFRX_DR1_PT_Pos (4U)
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+#define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
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+#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
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+#define SPDIFRX_DR1_C_Pos (3U)
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+#define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
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+#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
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+#define SPDIFRX_DR1_U_Pos (2U)
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+#define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
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+#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
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+#define SPDIFRX_DR1_V_Pos (1U)
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+#define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
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+#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
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+#define SPDIFRX_DR1_PE_Pos (0U)
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+#define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
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+#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
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+
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+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
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+#define SPDIFRX_DR1_DRNL1_Pos (16U)
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+#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
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+#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
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+#define SPDIFRX_DR1_DRNL2_Pos (0U)
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+#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
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+#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
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+
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+/******************* Bit definition for SPDIFRX_CSR register *******************/
|
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+#define SPDIFRX_CSR_USR_Pos (0U)
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+#define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
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+#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
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+#define SPDIFRX_CSR_CS_Pos (16U)
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+#define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
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+#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
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+#define SPDIFRX_CSR_SOB_Pos (24U)
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+#define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
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+#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
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+
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|
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+/******************* Bit definition for SPDIFRX_DIR register *******************/
|
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+#define SPDIFRX_DIR_THI_Pos (0U)
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+#define SPDIFRX_DIR_THI_Msk (0x13FFUL << SPDIFRX_DIR_THI_Pos) /*!< 0x000013FF */
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+#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
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+#define SPDIFRX_DIR_TLO_Pos (16U)
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+#define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
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+#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
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+
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+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* SD host Interface */
|
|
|
+/* */
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|
+/******************************************************************************/
|
|
|
+/****************** Bit definition for SDMMC_POWER register ******************/
|
|
|
+#define SDMMC_POWER_PWRCTRL_Pos (0U)
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+#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
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+#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
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+#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x01 */
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+#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x02 */
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|
+
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|
|
+/****************** Bit definition for SDMMC_CLKCR register ******************/
|
|
|
+#define SDMMC_CLKCR_CLKDIV_Pos (0U)
|
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+#define SDMMC_CLKCR_CLKDIV_Msk (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
|
|
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+#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
|
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+#define SDMMC_CLKCR_CLKEN_Pos (8U)
|
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+#define SDMMC_CLKCR_CLKEN_Msk (0x1UL << SDMMC_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
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+#define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk /*!<Clock enable bit */
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+#define SDMMC_CLKCR_PWRSAV_Pos (9U)
|
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|
+#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
|
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|
+#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
|
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+#define SDMMC_CLKCR_BYPASS_Pos (10U)
|
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|
+#define SDMMC_CLKCR_BYPASS_Msk (0x1UL << SDMMC_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
|
|
|
+#define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
|
|
|
+
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|
|
+#define SDMMC_CLKCR_WIDBUS_Pos (11U)
|
|
|
+#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
|
|
|
+#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
|
|
|
+#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
|
|
|
+#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
|
|
|
+
|
|
|
+#define SDMMC_CLKCR_NEGEDGE_Pos (13U)
|
|
|
+#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
|
|
|
+#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
|
|
|
+#define SDMMC_CLKCR_HWFC_EN_Pos (14U)
|
|
|
+#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
|
|
|
+#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
|
|
|
+
|
|
|
+/******************* Bit definition for SDMMC_ARG register *******************/
|
|
|
+#define SDMMC_ARG_CMDARG_Pos (0U)
|
|
|
+#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
|
|
|
+
|
|
|
+/******************* Bit definition for SDMMC_CMD register *******************/
|
|
|
+#define SDMMC_CMD_CMDINDEX_Pos (0U)
|
|
|
+#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
|
|
|
+#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
|
|
|
+
|
|
|
+#define SDMMC_CMD_WAITRESP_Pos (6U)
|
|
|
+#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
|
|
|
+#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
|
|
|
+#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0040 */
|
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+#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0080 */
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+
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+#define SDMMC_CMD_WAITINT_Pos (8U)
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+#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000100 */
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+#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
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+#define SDMMC_CMD_WAITPEND_Pos (9U)
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+#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000200 */
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+#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
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+#define SDMMC_CMD_CPSMEN_Pos (10U)
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+#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00000400 */
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+#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
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+#define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
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+#define SDMMC_CMD_SDIOSUSPEND_Msk (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
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+#define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
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+
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+/***************** Bit definition for SDMMC_RESPCMD register *****************/
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+#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
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+#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
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+#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
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+
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+/****************** Bit definition for SDMMC_RESP0 register ******************/
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+#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
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+#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
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+#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
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+
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+/****************** Bit definition for SDMMC_RESP1 register ******************/
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+#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
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+#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
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+#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
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+
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+/****************** Bit definition for SDMMC_RESP2 register ******************/
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+#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
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+#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
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+#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
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+
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+/****************** Bit definition for SDMMC_RESP3 register ******************/
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+#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
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+#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
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+#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
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+
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+/****************** Bit definition for SDMMC_RESP4 register ******************/
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+#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
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+#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
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+#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
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+
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+/****************** Bit definition for SDMMC_DTIMER register *****************/
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+#define SDMMC_DTIMER_DATATIME_Pos (0U)
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+#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
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+#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
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+
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+/****************** Bit definition for SDMMC_DLEN register *******************/
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+#define SDMMC_DLEN_DATALENGTH_Pos (0U)
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+#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
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+#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
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+
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+/****************** Bit definition for SDMMC_DCTRL register ******************/
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+#define SDMMC_DCTRL_DTEN_Pos (0U)
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+#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
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+#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
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+#define SDMMC_DCTRL_DTDIR_Pos (1U)
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+#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
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+#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
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+#define SDMMC_DCTRL_DTMODE_Pos (2U)
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+#define SDMMC_DCTRL_DTMODE_Msk (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
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+#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
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+#define SDMMC_DCTRL_DMAEN_Pos (3U)
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+#define SDMMC_DCTRL_DMAEN_Msk (0x1UL << SDMMC_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
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+#define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
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+
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+#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
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+#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
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+#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
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+#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
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+#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
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+#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
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+#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
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+
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|
|
+#define SDMMC_DCTRL_RWSTART_Pos (8U)
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+#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
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+#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
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+#define SDMMC_DCTRL_RWSTOP_Pos (9U)
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+#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
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+#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
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+#define SDMMC_DCTRL_RWMOD_Pos (10U)
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+#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
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+#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
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+#define SDMMC_DCTRL_SDIOEN_Pos (11U)
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+#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
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+#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
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+
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+/****************** Bit definition for SDMMC_DCOUNT register *****************/
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+#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
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+#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
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+#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
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+
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+/****************** Bit definition for SDMMC_STA registe ********************/
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+#define SDMMC_STA_CCRCFAIL_Pos (0U)
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+#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
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+#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
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+#define SDMMC_STA_DCRCFAIL_Pos (1U)
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+#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
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+#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
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+#define SDMMC_STA_CTIMEOUT_Pos (2U)
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+#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
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+#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
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+#define SDMMC_STA_DTIMEOUT_Pos (3U)
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+#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
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+#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
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+#define SDMMC_STA_TXUNDERR_Pos (4U)
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+#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
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+#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
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+#define SDMMC_STA_RXOVERR_Pos (5U)
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+#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
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+#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
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+#define SDMMC_STA_CMDREND_Pos (6U)
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+#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
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+#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
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+#define SDMMC_STA_CMDSENT_Pos (7U)
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+#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
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+#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
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+#define SDMMC_STA_DATAEND_Pos (8U)
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+#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
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+#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
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+#define SDMMC_STA_DBCKEND_Pos (10U)
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+#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
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+#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
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+#define SDMMC_STA_CMDACT_Pos (11U)
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+#define SDMMC_STA_CMDACT_Msk (0x1UL << SDMMC_STA_CMDACT_Pos) /*!< 0x00000800 */
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+#define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk /*!<Command transfer in progress */
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+#define SDMMC_STA_TXACT_Pos (12U)
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+#define SDMMC_STA_TXACT_Msk (0x1UL << SDMMC_STA_TXACT_Pos) /*!< 0x00001000 */
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+#define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk /*!<Data transmit in progress */
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+#define SDMMC_STA_RXACT_Pos (13U)
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+#define SDMMC_STA_RXACT_Msk (0x1UL << SDMMC_STA_RXACT_Pos) /*!< 0x00002000 */
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+#define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk /*!<Data receive in progress */
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+#define SDMMC_STA_TXFIFOHE_Pos (14U)
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+#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
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+#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
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+#define SDMMC_STA_RXFIFOHF_Pos (15U)
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+#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
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+#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
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+#define SDMMC_STA_TXFIFOF_Pos (16U)
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+#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
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+#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
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+#define SDMMC_STA_RXFIFOF_Pos (17U)
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+#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
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+#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
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+#define SDMMC_STA_TXFIFOE_Pos (18U)
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+#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
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+#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
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+#define SDMMC_STA_RXFIFOE_Pos (19U)
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+#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
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+#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
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+#define SDMMC_STA_TXDAVL_Pos (20U)
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+#define SDMMC_STA_TXDAVL_Msk (0x1UL << SDMMC_STA_TXDAVL_Pos) /*!< 0x00100000 */
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+#define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
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+#define SDMMC_STA_RXDAVL_Pos (21U)
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+#define SDMMC_STA_RXDAVL_Msk (0x1UL << SDMMC_STA_RXDAVL_Pos) /*!< 0x00200000 */
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+#define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
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+#define SDMMC_STA_SDIOIT_Pos (22U)
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+#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
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+#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDMMC interrupt received */
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+
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+/******************* Bit definition for SDMMC_ICR register *******************/
|
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+#define SDMMC_ICR_CCRCFAILC_Pos (0U)
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+#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
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+#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
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+#define SDMMC_ICR_DCRCFAILC_Pos (1U)
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+#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
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+#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
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+#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
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+#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
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+#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
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+#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
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+#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
|
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+#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
|
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+#define SDMMC_ICR_TXUNDERRC_Pos (4U)
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+#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
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|
|
+#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
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|
+#define SDMMC_ICR_RXOVERRC_Pos (5U)
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+#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
|
|
|
+#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
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|
+#define SDMMC_ICR_CMDRENDC_Pos (6U)
|
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|
+#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
|
|
|
+#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
|
|
|
+#define SDMMC_ICR_CMDSENTC_Pos (7U)
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|
|
+#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
|
|
|
+#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
|
|
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+#define SDMMC_ICR_DATAENDC_Pos (8U)
|
|
|
+#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
|
|
|
+#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
|
|
|
+#define SDMMC_ICR_DBCKENDC_Pos (10U)
|
|
|
+#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
|
|
|
+#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
|
|
|
+#define SDMMC_ICR_SDIOITC_Pos (22U)
|
|
|
+#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
|
|
|
+#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDMMCIT flag clear bit */
|
|
|
+
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|
|
+/****************** Bit definition for SDMMC_MASK register *******************/
|
|
|
+#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
|
|
|
+#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
|
|
|
+#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
|
|
|
+#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
|
|
|
+#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
|
|
|
+#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
|
|
|
+#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
|
|
|
+#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
|
|
|
+#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
|
|
|
+#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
|
|
|
+#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
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+#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
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+#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
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+#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
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+#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
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+#define SDMMC_MASK_RXOVERRIE_Pos (5U)
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+#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
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+#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
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+#define SDMMC_MASK_CMDRENDIE_Pos (6U)
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+#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
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+#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
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+#define SDMMC_MASK_CMDSENTIE_Pos (7U)
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+#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
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+#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
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+#define SDMMC_MASK_DATAENDIE_Pos (8U)
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+#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
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+#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
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+#define SDMMC_MASK_DBCKENDIE_Pos (10U)
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+#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
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+#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
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+#define SDMMC_MASK_CMDACTIE_Pos (11U)
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+#define SDMMC_MASK_CMDACTIE_Msk (0x1UL << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
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+#define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
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+#define SDMMC_MASK_TXACTIE_Pos (12U)
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+#define SDMMC_MASK_TXACTIE_Msk (0x1UL << SDMMC_MASK_TXACTIE_Pos) /*!< 0x00001000 */
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+#define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
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+#define SDMMC_MASK_RXACTIE_Pos (13U)
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+#define SDMMC_MASK_RXACTIE_Msk (0x1UL << SDMMC_MASK_RXACTIE_Pos) /*!< 0x00002000 */
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+#define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
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+#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
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+#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
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+#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
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+#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
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+#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
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+#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
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+#define SDMMC_MASK_TXFIFOFIE_Pos (16U)
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+#define SDMMC_MASK_TXFIFOFIE_Msk (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
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+#define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
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+#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
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+#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
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+#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
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+#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
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+#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
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+#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
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+#define SDMMC_MASK_RXFIFOEIE_Pos (19U)
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+#define SDMMC_MASK_RXFIFOEIE_Msk (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
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+#define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
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+#define SDMMC_MASK_TXDAVLIE_Pos (20U)
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+#define SDMMC_MASK_TXDAVLIE_Msk (0x1UL << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
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+#define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
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+#define SDMMC_MASK_RXDAVLIE_Pos (21U)
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+#define SDMMC_MASK_RXDAVLIE_Msk (0x1UL << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
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+#define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
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+#define SDMMC_MASK_SDIOITIE_Pos (22U)
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+#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
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+#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
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+
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+/***************** Bit definition for SDMMC_FIFOCNT register *****************/
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+#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
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+#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
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+#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
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+
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+/****************** Bit definition for SDMMC_FIFO register *******************/
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+#define SDMMC_FIFO_FIFODATA_Pos (0U)
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+#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
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+#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
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+
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+/******************************************************************************/
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+/* */
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+/* Serial Peripheral Interface (SPI) */
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+/* */
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+/******************************************************************************/
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+/******************* Bit definition for SPI_CR1 register ********************/
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+#define SPI_CR1_CPHA_Pos (0U)
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+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
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+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
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+#define SPI_CR1_CPOL_Pos (1U)
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+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
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+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
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+#define SPI_CR1_MSTR_Pos (2U)
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+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
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+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
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+#define SPI_CR1_BR_Pos (3U)
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+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
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+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
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+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
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+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
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+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
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+#define SPI_CR1_SPE_Pos (6U)
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+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
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+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
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+#define SPI_CR1_LSBFIRST_Pos (7U)
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+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
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+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
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+#define SPI_CR1_SSI_Pos (8U)
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+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
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+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
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+#define SPI_CR1_SSM_Pos (9U)
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+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
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+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
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+#define SPI_CR1_RXONLY_Pos (10U)
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+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
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+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
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+#define SPI_CR1_CRCL_Pos (11U)
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+#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
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+#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
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+#define SPI_CR1_CRCNEXT_Pos (12U)
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+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
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+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
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+#define SPI_CR1_CRCEN_Pos (13U)
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+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
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+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
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+#define SPI_CR1_BIDIOE_Pos (14U)
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+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
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+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
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+#define SPI_CR1_BIDIMODE_Pos (15U)
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+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
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+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
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+
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+/******************* Bit definition for SPI_CR2 register ********************/
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+#define SPI_CR2_RXDMAEN_Pos (0U)
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+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
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+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
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+#define SPI_CR2_TXDMAEN_Pos (1U)
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+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
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+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
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+#define SPI_CR2_SSOE_Pos (2U)
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+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
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+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
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+#define SPI_CR2_NSSP_Pos (3U)
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+#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
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+#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
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+#define SPI_CR2_FRF_Pos (4U)
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+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
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+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
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+#define SPI_CR2_ERRIE_Pos (5U)
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+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
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+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
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+#define SPI_CR2_RXNEIE_Pos (6U)
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+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
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+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
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+#define SPI_CR2_TXEIE_Pos (7U)
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+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
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+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
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+#define SPI_CR2_DS_Pos (8U)
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+#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
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+#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
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+#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
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+#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
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+#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
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+#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
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+#define SPI_CR2_FRXTH_Pos (12U)
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+#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
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|
+#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
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+#define SPI_CR2_LDMARX_Pos (13U)
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|
+#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
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+#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
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+#define SPI_CR2_LDMATX_Pos (14U)
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+#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
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+#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
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+
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+/******************** Bit definition for SPI_SR register ********************/
|
|
|
+#define SPI_SR_RXNE_Pos (0U)
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+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
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+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
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+#define SPI_SR_TXE_Pos (1U)
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+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
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+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
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+#define SPI_SR_CHSIDE_Pos (2U)
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+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
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+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
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+#define SPI_SR_UDR_Pos (3U)
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+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
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+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
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+#define SPI_SR_CRCERR_Pos (4U)
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+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
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+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
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+#define SPI_SR_MODF_Pos (5U)
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+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
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+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
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|
+#define SPI_SR_OVR_Pos (6U)
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+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
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+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
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|
+#define SPI_SR_BSY_Pos (7U)
|
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+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
|
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|
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
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+#define SPI_SR_FRE_Pos (8U)
|
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+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
|
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|
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
|
|
|
+#define SPI_SR_FRLVL_Pos (9U)
|
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|
+#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
|
|
|
+#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
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|
+#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
|
|
|
+#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
|
|
|
+#define SPI_SR_FTLVL_Pos (11U)
|
|
|
+#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
|
|
|
+#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
|
|
|
+#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
|
|
|
+#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
|
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|
+
|
|
|
+/******************** Bit definition for SPI_DR register ********************/
|
|
|
+#define SPI_DR_DR_Pos (0U)
|
|
|
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
|
|
|
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
|
|
|
+
|
|
|
+/******************* Bit definition for SPI_CRCPR register ******************/
|
|
|
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
|
|
|
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
|
|
|
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
|
|
|
+
|
|
|
+/****************** Bit definition for SPI_RXCRCR register ******************/
|
|
|
+#define SPI_RXCRCR_RXCRC_Pos (0U)
|
|
|
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
|
|
|
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
|
|
|
+
|
|
|
+/****************** Bit definition for SPI_TXCRCR register ******************/
|
|
|
+#define SPI_TXCRCR_TXCRC_Pos (0U)
|
|
|
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
|
|
|
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
|
|
|
+
|
|
|
+/****************** Bit definition for SPI_I2SCFGR register *****************/
|
|
|
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
|
|
|
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
|
|
|
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
|
|
|
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
|
|
|
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
|
|
|
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
|
|
|
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
|
|
|
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
|
|
|
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
|
|
|
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
|
|
|
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
|
|
|
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
|
|
|
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
|
|
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+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
|
|
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+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
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|
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+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
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|
|
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
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+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
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|
|
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
|
|
|
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
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|
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+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
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+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
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|
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+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
|
|
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+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
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|
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+#define SPI_I2SCFGR_I2SE_Pos (10U)
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|
|
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
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+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
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|
|
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
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+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
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|
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+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
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|
|
+#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
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+#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
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|
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+#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
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+
|
|
|
+/****************** Bit definition for SPI_I2SPR register *******************/
|
|
|
+#define SPI_I2SPR_I2SDIV_Pos (0U)
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+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
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|
|
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
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|
|
+#define SPI_I2SPR_ODD_Pos (8U)
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|
|
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
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|
|
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
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|
|
+#define SPI_I2SPR_MCKOE_Pos (9U)
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|
|
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
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|
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+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
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|
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+
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|
|
+
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|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* SYSCFG */
|
|
|
+/* */
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|
|
+/******************************************************************************/
|
|
|
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
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|
|
+#define SYSCFG_MEMRMP_MEM_BOOT_Pos (0U)
|
|
|
+#define SYSCFG_MEMRMP_MEM_BOOT_Msk (0x1UL << SYSCFG_MEMRMP_MEM_BOOT_Pos) /*!< 0x00000001 */
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|
|
+#define SYSCFG_MEMRMP_MEM_BOOT SYSCFG_MEMRMP_MEM_BOOT_Msk /*!< Boot information after Reset */
|
|
|
+
|
|
|
+#define SYSCFG_MEMRMP_SWP_FB_Pos (8U)
|
|
|
+#define SYSCFG_MEMRMP_SWP_FB_Msk (0x1UL << SYSCFG_MEMRMP_SWP_FB_Pos) /*!< 0x00000100 */
|
|
|
+#define SYSCFG_MEMRMP_SWP_FB SYSCFG_MEMRMP_SWP_FB_Msk /*!< User Flash Bank swap */
|
|
|
+
|
|
|
+#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
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|
|
+#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
|
|
|
+#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC Memory Mapping swapping */
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|
|
+#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
|
|
|
+#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */
|
|
|
+
|
|
|
+/****************** Bit definition for SYSCFG_PMC register ******************/
|
|
|
+#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
|
|
|
+#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
|
|
|
+#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
|
|
|
+#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
|
|
|
+#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
|
|
|
+#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
|
|
|
+#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
|
|
|
+#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
|
|
|
+#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
|
|
|
+#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
|
|
|
+#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
|
|
|
+#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
|
|
|
+#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
|
|
|
+#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
|
|
|
+#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
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|
|
+#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
|
|
|
+#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
|
|
|
+#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
|
|
|
+#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
|
|
|
+#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
|
|
|
+#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
|
|
|
+#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
|
|
|
+#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
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|
|
+#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */
|
|
|
+
|
|
|
+#define SYSCFG_PMC_ADCxDC2_Pos (16U)
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|
|
+#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
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|
|
+#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
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|
|
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)
|
|
|
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
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|
|
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
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|
|
+#define SYSCFG_PMC_ADC2DC2_Pos (17U)
|
|
|
+#define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
|
|
|
+#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
|
|
|
+#define SYSCFG_PMC_ADC3DC2_Pos (18U)
|
|
|
+#define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
|
|
|
+#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
|
|
|
+
|
|
|
+#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
|
|
|
+#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
|
|
|
+#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
|
|
|
+
|
|
|
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
|
|
|
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
|
|
|
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
|
|
|
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
|
|
|
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
|
|
|
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
|
|
|
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
|
|
|
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
|
|
|
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
|
|
|
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
|
|
|
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
|
|
|
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
|
|
|
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
|
|
|
+/**
|
|
|
+ * @brief EXTI0 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief EXTI1 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief EXTI2 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief EXTI3 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
|
|
|
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
|
|
|
+
|
|
|
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
|
|
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
|
|
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
|
|
|
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
|
|
|
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
|
|
|
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
|
|
|
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
|
|
|
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
|
|
|
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
|
|
|
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
|
|
|
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
|
|
|
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
|
|
|
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
|
|
|
+/**
|
|
|
+ * @brief EXTI4 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief EXTI5 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief EXTI6 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief EXTI7 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
|
|
|
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
|
|
|
+
|
|
|
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
|
|
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
|
|
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
|
|
|
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
|
|
|
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
|
|
|
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
|
|
|
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
|
|
|
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
|
|
|
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
|
|
|
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
|
|
|
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
|
|
|
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
|
|
|
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief EXTI8 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief EXTI9 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief EXTI10 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief EXTI11 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
|
|
|
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
|
|
|
+
|
|
|
+
|
|
|
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
|
|
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
|
|
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
|
|
|
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
|
|
|
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
|
|
|
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
|
|
|
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
|
|
|
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
|
|
|
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
|
|
|
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
|
|
|
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
|
|
|
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
|
|
|
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
|
|
|
+/**
|
|
|
+ * @brief EXTI12 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief EXTI13 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /*!<PI[13] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /*!<PJ[13] pin */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief EXTI14 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief EXTI15 configuration
|
|
|
+ */
|
|
|
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
|
|
|
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
|
|
|
+
|
|
|
+/****************** Bit definition for SYSCFG_CBR register ******************/
|
|
|
+#define SYSCFG_CBR_CLL_Pos (0U)
|
|
|
+#define SYSCFG_CBR_CLL_Msk (0x1UL << SYSCFG_CBR_CLL_Pos) /*!< 0x00000001 */
|
|
|
+#define SYSCFG_CBR_CLL SYSCFG_CBR_CLL_Msk /*!<Core Lockup Lock */
|
|
|
+#define SYSCFG_CBR_PVDL_Pos (2U)
|
|
|
+#define SYSCFG_CBR_PVDL_Msk (0x1UL << SYSCFG_CBR_PVDL_Pos) /*!< 0x00000004 */
|
|
|
+#define SYSCFG_CBR_PVDL SYSCFG_CBR_PVDL_Msk /*!<PVD Lock */
|
|
|
+
|
|
|
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
|
|
|
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
|
|
|
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
|
|
|
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell power-down */
|
|
|
+#define SYSCFG_CMPCR_READY_Pos (8U)
|
|
|
+#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
|
|
|
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell ready flag */
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* TIM */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/*
|
|
|
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
|
|
+ */
|
|
|
+#define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature available on specific devices */
|
|
|
+/******************* Bit definition for TIM_CR1 register ********************/
|
|
|
+#define TIM_CR1_CEN_Pos (0U)
|
|
|
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
|
|
|
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
|
|
|
+#define TIM_CR1_UDIS_Pos (1U)
|
|
|
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
|
|
|
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
|
|
|
+#define TIM_CR1_URS_Pos (2U)
|
|
|
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
|
|
|
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
|
|
|
+#define TIM_CR1_OPM_Pos (3U)
|
|
|
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
|
|
|
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
|
|
|
+#define TIM_CR1_DIR_Pos (4U)
|
|
|
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
|
|
|
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
|
|
|
+
|
|
|
+#define TIM_CR1_CMS_Pos (5U)
|
|
|
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
|
|
|
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
|
|
|
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x0020 */
|
|
|
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x0040 */
|
|
|
+
|
|
|
+#define TIM_CR1_ARPE_Pos (7U)
|
|
|
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
|
|
|
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
|
|
|
+
|
|
|
+#define TIM_CR1_CKD_Pos (8U)
|
|
|
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
|
|
|
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
|
|
|
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x0100 */
|
|
|
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x0200 */
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+#define TIM_CR1_UIFREMAP_Pos (11U)
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+#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
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+#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<UIF status bit */
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+
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+/******************* Bit definition for TIM_CR2 register ********************/
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+#define TIM_CR2_CCPC_Pos (0U)
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+#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
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+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
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+#define TIM_CR2_CCUS_Pos (2U)
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+#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
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+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
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+#define TIM_CR2_CCDS_Pos (3U)
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+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
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+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
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+
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+#define TIM_CR2_OIS5_Pos (16U)
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+#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
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+#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
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+#define TIM_CR2_OIS6_Pos (18U)
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+#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
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+#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
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+
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+#define TIM_CR2_MMS_Pos (4U)
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+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
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+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
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+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x0010 */
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+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x0020 */
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+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x0040 */
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+
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+#define TIM_CR2_MMS2_Pos (20U)
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+#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
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+#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
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+#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
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+#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
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+#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
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+#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
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+
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+#define TIM_CR2_TI1S_Pos (7U)
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+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
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+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
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+#define TIM_CR2_OIS1_Pos (8U)
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+#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
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+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
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+#define TIM_CR2_OIS1N_Pos (9U)
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+#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
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+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
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+#define TIM_CR2_OIS2_Pos (10U)
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+#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
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+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
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+#define TIM_CR2_OIS2N_Pos (11U)
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+#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
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+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
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+#define TIM_CR2_OIS3_Pos (12U)
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+#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
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+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
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+#define TIM_CR2_OIS3N_Pos (13U)
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+#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
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+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
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+#define TIM_CR2_OIS4_Pos (14U)
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+#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
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+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
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+
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+/******************* Bit definition for TIM_SMCR register *******************/
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+#define TIM_SMCR_SMS_Pos (0U)
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+#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
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+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
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+#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
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+#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
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+#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
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+#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
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+
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+#define TIM_SMCR_TS_Pos (4U)
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+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
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+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
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+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */
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+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */
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+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */
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+
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+#define TIM_SMCR_MSM_Pos (7U)
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+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
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+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
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+
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+#define TIM_SMCR_ETF_Pos (8U)
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+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
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+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
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+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
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+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
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+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
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+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
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+
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+#define TIM_SMCR_ETPS_Pos (12U)
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+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
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+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
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+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
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+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
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+
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+#define TIM_SMCR_ECE_Pos (14U)
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+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
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+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
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+#define TIM_SMCR_ETP_Pos (15U)
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+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
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+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
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+
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+/******************* Bit definition for TIM_DIER register *******************/
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+#define TIM_DIER_UIE_Pos (0U)
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+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
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+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
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+#define TIM_DIER_CC1IE_Pos (1U)
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+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
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+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
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+#define TIM_DIER_CC2IE_Pos (2U)
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+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
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+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
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+#define TIM_DIER_CC3IE_Pos (3U)
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+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
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+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
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+#define TIM_DIER_CC4IE_Pos (4U)
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+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
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+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
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+#define TIM_DIER_COMIE_Pos (5U)
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+#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
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+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
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+#define TIM_DIER_TIE_Pos (6U)
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+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
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+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
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+#define TIM_DIER_BIE_Pos (7U)
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+#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
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+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
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+#define TIM_DIER_UDE_Pos (8U)
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+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
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+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
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+#define TIM_DIER_CC1DE_Pos (9U)
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+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
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+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
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+#define TIM_DIER_CC2DE_Pos (10U)
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+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
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+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
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+#define TIM_DIER_CC3DE_Pos (11U)
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+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
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+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
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+#define TIM_DIER_CC4DE_Pos (12U)
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+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
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+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
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+#define TIM_DIER_COMDE_Pos (13U)
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+#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
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+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
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+#define TIM_DIER_TDE_Pos (14U)
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+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
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+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
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+
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|
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+/******************** Bit definition for TIM_SR register ********************/
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+#define TIM_SR_UIF_Pos (0U)
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+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
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+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
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+#define TIM_SR_CC1IF_Pos (1U)
|
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+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
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+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
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+#define TIM_SR_CC2IF_Pos (2U)
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+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
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+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
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+#define TIM_SR_CC3IF_Pos (3U)
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+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
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+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
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+#define TIM_SR_CC4IF_Pos (4U)
|
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+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
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+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
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+#define TIM_SR_COMIF_Pos (5U)
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+#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
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+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
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+#define TIM_SR_TIF_Pos (6U)
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+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
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+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
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+#define TIM_SR_BIF_Pos (7U)
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+#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
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+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
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+#define TIM_SR_B2IF_Pos (8U)
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+#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
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+#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
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+#define TIM_SR_CC1OF_Pos (9U)
|
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+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
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+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
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+#define TIM_SR_CC2OF_Pos (10U)
|
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+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
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+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
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+#define TIM_SR_CC3OF_Pos (11U)
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+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
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+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
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+#define TIM_SR_CC4OF_Pos (12U)
|
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+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
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+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
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+#define TIM_SR_SBIF_Pos (13U)
|
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+#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
|
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+#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
|
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|
+#define TIM_SR_CC5IF_Pos (16U)
|
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+#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
|
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|
+#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
|
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|
+#define TIM_SR_CC6IF_Pos (17U)
|
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+#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
|
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|
+#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
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+
|
|
|
+/******************* Bit definition for TIM_EGR register ********************/
|
|
|
+#define TIM_EGR_UG_Pos (0U)
|
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+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
|
|
|
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
|
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|
+#define TIM_EGR_CC1G_Pos (1U)
|
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|
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
|
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|
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
|
|
|
+#define TIM_EGR_CC2G_Pos (2U)
|
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|
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
|
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|
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
|
|
|
+#define TIM_EGR_CC3G_Pos (3U)
|
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+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
|
|
|
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
|
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|
+#define TIM_EGR_CC4G_Pos (4U)
|
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|
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
|
|
|
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
|
|
|
+#define TIM_EGR_COMG_Pos (5U)
|
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|
+#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
|
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|
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
|
|
|
+#define TIM_EGR_TG_Pos (6U)
|
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|
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
|
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|
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
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+#define TIM_EGR_BG_Pos (7U)
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+#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
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+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
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+#define TIM_EGR_B2G_Pos (8U)
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+#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
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+#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break2 Generation */
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+
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+/****************** Bit definition for TIM_CCMR1 register *******************/
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+#define TIM_CCMR1_CC1S_Pos (0U)
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+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
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+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
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+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
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+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
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+
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+#define TIM_CCMR1_OC1FE_Pos (2U)
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+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
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+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
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+#define TIM_CCMR1_OC1PE_Pos (3U)
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+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
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+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
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+
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+#define TIM_CCMR1_OC1M_Pos (4U)
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+#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
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+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
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+#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
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+#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
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+#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
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+#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
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+
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+#define TIM_CCMR1_OC1CE_Pos (7U)
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+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
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+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
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+
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+#define TIM_CCMR1_CC2S_Pos (8U)
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+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
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+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
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+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
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+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
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+
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+#define TIM_CCMR1_OC2FE_Pos (10U)
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+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
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+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
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+#define TIM_CCMR1_OC2PE_Pos (11U)
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+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
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+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
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+
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+#define TIM_CCMR1_OC2M_Pos (12U)
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+#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
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+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
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+#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
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+#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
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+#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
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+#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
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+
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+#define TIM_CCMR1_OC2CE_Pos (15U)
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+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
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+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
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+
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+/*----------------------------------------------------------------------------*/
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+
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+#define TIM_CCMR1_IC1PSC_Pos (2U)
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+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
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+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
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+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
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+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
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+
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+#define TIM_CCMR1_IC1F_Pos (4U)
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+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
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+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
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+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
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+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
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+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
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+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
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+
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+#define TIM_CCMR1_IC2PSC_Pos (10U)
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+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
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+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
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+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
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+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
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+
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+#define TIM_CCMR1_IC2F_Pos (12U)
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+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
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+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
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+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
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+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
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+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
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+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
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+
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+/****************** Bit definition for TIM_CCMR2 register *******************/
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+#define TIM_CCMR2_CC3S_Pos (0U)
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+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
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+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
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+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
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+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
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+
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+#define TIM_CCMR2_OC3FE_Pos (2U)
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+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
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+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
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+#define TIM_CCMR2_OC3PE_Pos (3U)
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+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
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+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
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+
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+#define TIM_CCMR2_OC3M_Pos (4U)
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+#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
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+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
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+#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
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+#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
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+#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
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+#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
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+
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+
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+
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+#define TIM_CCMR2_OC3CE_Pos (7U)
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+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
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+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
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+
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+#define TIM_CCMR2_CC4S_Pos (8U)
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+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
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+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
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+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
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+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
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+
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+#define TIM_CCMR2_OC4FE_Pos (10U)
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+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
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+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
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+#define TIM_CCMR2_OC4PE_Pos (11U)
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+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
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+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
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+
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+#define TIM_CCMR2_OC4M_Pos (12U)
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+#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
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+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
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+#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
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+#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
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+#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
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+#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
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+
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+#define TIM_CCMR2_OC4CE_Pos (15U)
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+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
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+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
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+
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+/*----------------------------------------------------------------------------*/
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+
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+#define TIM_CCMR2_IC3PSC_Pos (2U)
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+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
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+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
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+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
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+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
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+
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+#define TIM_CCMR2_IC3F_Pos (4U)
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+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
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+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
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+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
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+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
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+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
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+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
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+
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+#define TIM_CCMR2_IC4PSC_Pos (10U)
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+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
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+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
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+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
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+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
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+
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+#define TIM_CCMR2_IC4F_Pos (12U)
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+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
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+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
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+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
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+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
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+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
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+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
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+
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+/******************* Bit definition for TIM_CCER register *******************/
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+#define TIM_CCER_CC1E_Pos (0U)
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+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
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+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
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+#define TIM_CCER_CC1P_Pos (1U)
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+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
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+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
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+#define TIM_CCER_CC1NE_Pos (2U)
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+#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
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+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
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+#define TIM_CCER_CC1NP_Pos (3U)
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+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
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+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
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+#define TIM_CCER_CC2E_Pos (4U)
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+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
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+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
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+#define TIM_CCER_CC2P_Pos (5U)
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+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
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+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
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+#define TIM_CCER_CC2NE_Pos (6U)
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+#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
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+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
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+#define TIM_CCER_CC2NP_Pos (7U)
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+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
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+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
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+#define TIM_CCER_CC3E_Pos (8U)
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+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
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+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
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+#define TIM_CCER_CC3P_Pos (9U)
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+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
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+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
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+#define TIM_CCER_CC3NE_Pos (10U)
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+#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
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+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
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+#define TIM_CCER_CC3NP_Pos (11U)
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+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
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+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
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+#define TIM_CCER_CC4E_Pos (12U)
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+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
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+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
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+#define TIM_CCER_CC4P_Pos (13U)
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+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
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+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
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+#define TIM_CCER_CC4NP_Pos (15U)
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+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
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+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
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+#define TIM_CCER_CC5E_Pos (16U)
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+#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
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+#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
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+#define TIM_CCER_CC5P_Pos (17U)
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+#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
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+#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
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+#define TIM_CCER_CC6E_Pos (20U)
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+#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
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+#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
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+#define TIM_CCER_CC6P_Pos (21U)
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+#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
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+#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
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+
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+
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+/******************* Bit definition for TIM_CNT register ********************/
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+#define TIM_CNT_CNT_Pos (0U)
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+#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
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+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
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+#define TIM_CNT_UIFCPY_Pos (31U)
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+#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
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+#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
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+
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+/******************* Bit definition for TIM_PSC register ********************/
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+#define TIM_PSC_PSC_Pos (0U)
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+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
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+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
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+
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+/******************* Bit definition for TIM_ARR register ********************/
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+#define TIM_ARR_ARR_Pos (0U)
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+#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
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+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
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+
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+/******************* Bit definition for TIM_RCR register ********************/
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+#define TIM_RCR_REP_Pos (0U)
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+#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
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+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
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+
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+/******************* Bit definition for TIM_CCR1 register *******************/
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+#define TIM_CCR1_CCR1_Pos (0U)
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+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
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+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
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+
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+/******************* Bit definition for TIM_CCR2 register *******************/
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+#define TIM_CCR2_CCR2_Pos (0U)
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+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
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+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
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+
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+/******************* Bit definition for TIM_CCR3 register *******************/
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+#define TIM_CCR3_CCR3_Pos (0U)
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+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
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+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
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+
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+/******************* Bit definition for TIM_CCR4 register *******************/
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+#define TIM_CCR4_CCR4_Pos (0U)
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+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
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+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
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+
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+/******************* Bit definition for TIM_BDTR register *******************/
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+#define TIM_BDTR_DTG_Pos (0U)
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+#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
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+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
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+#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
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+#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
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+#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
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+#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
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+#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
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+#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
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+#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
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+#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
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+
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|
|
+#define TIM_BDTR_LOCK_Pos (8U)
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+#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
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+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
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+#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
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+#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
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+
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|
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+#define TIM_BDTR_OSSI_Pos (10U)
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+#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
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|
|
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
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|
+#define TIM_BDTR_OSSR_Pos (11U)
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|
+#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
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+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
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|
+#define TIM_BDTR_BKE_Pos (12U)
|
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|
+#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
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|
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
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|
+#define TIM_BDTR_BKP_Pos (13U)
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|
+#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
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+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
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|
+#define TIM_BDTR_AOE_Pos (14U)
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|
+#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
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+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
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+#define TIM_BDTR_MOE_Pos (15U)
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|
+#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
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+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
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|
+#define TIM_BDTR_BKF_Pos (16U)
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+#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
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+#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
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+#define TIM_BDTR_BK2F_Pos (20U)
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+#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
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+#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
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+#define TIM_BDTR_BK2E_Pos (24U)
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+#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
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+#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
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+#define TIM_BDTR_BK2P_Pos (25U)
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+#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
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+#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
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+
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+/******************* Bit definition for TIM_DCR register ********************/
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+#define TIM_DCR_DBA_Pos (0U)
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+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
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+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
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+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x0001 */
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+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x0002 */
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+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x0004 */
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+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x0008 */
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+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x0010 */
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+
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|
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+#define TIM_DCR_DBL_Pos (8U)
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+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
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+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
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+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x0100 */
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+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x0200 */
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+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x0400 */
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+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x0800 */
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+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x1000 */
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+
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+/******************* Bit definition for TIM_DMAR register *******************/
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+#define TIM_DMAR_DMAB_Pos (0U)
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+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
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+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
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+
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|
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+/******************* Bit definition for TIM_OR regiter *********************/
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+#define TIM_OR_TI4_RMP_Pos (6U)
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+#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
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+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
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+#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
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+#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
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+#define TIM_OR_ITR1_RMP_Pos (10U)
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+#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
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+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
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+#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
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+#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
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+
|
|
|
+/******************* Bit definition for TIM2_OR register *******************/
|
|
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+#define TIM2_OR_ITR1_RMP_Pos (10U)
|
|
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+#define TIM2_OR_ITR1_RMP_Msk (0x3UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
|
|
|
+#define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
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+#define TIM2_OR_ITR1_RMP_0 (0x1UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000400 */
|
|
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+#define TIM2_OR_ITR1_RMP_1 (0x2UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000800 */
|
|
|
+
|
|
|
+/******************* Bit definition for TIM5_OR register *******************/
|
|
|
+#define TIM5_OR_TI4_RMP_Pos (6U)
|
|
|
+#define TIM5_OR_TI4_RMP_Msk (0x3UL << TIM5_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
|
|
+#define TIM5_OR_TI4_RMP TIM5_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input Capture 4 remap) */
|
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+#define TIM5_OR_TI4_RMP_0 (0x1UL << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000040 */
|
|
|
+#define TIM5_OR_TI4_RMP_1 (0x2UL << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000080 */
|
|
|
+
|
|
|
+/******************* Bit definition for TIM11_OR register *******************/
|
|
|
+#define TIM11_OR_TI1_RMP_Pos (0U)
|
|
|
+#define TIM11_OR_TI1_RMP_Msk (0x3UL << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000003 */
|
|
|
+#define TIM11_OR_TI1_RMP TIM11_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
|
|
|
+#define TIM11_OR_TI1_RMP_0 (0x1UL << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000001 */
|
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|
+#define TIM11_OR_TI1_RMP_1 (0x2UL << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000002 */
|
|
|
+
|
|
|
+/****************** Bit definition for TIM_CCMR3 register *******************/
|
|
|
+#define TIM_CCMR3_OC5FE_Pos (2U)
|
|
|
+#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
|
|
|
+#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
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|
|
+#define TIM_CCMR3_OC5PE_Pos (3U)
|
|
|
+#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
|
|
|
+#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
|
|
+
|
|
|
+#define TIM_CCMR3_OC5M_Pos (4U)
|
|
|
+#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
|
|
+#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
|
|
+#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
|
|
+#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
|
|
+#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
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|
+#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
|
|
|
+
|
|
|
+#define TIM_CCMR3_OC5CE_Pos (7U)
|
|
|
+#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
|
|
|
+#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
|
|
|
+
|
|
|
+#define TIM_CCMR3_OC6FE_Pos (10U)
|
|
|
+#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
|
|
|
+#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
|
|
|
+#define TIM_CCMR3_OC6PE_Pos (11U)
|
|
|
+#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
|
|
|
+#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
|
|
+
|
|
|
+#define TIM_CCMR3_OC6M_Pos (12U)
|
|
|
+#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
|
|
+#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
|
|
+#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
|
|
+#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
|
|
+#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
|
|
+#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
|
|
+
|
|
|
+#define TIM_CCMR3_OC6CE_Pos (15U)
|
|
|
+#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
|
|
+#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
|
|
|
+
|
|
|
+/******************* Bit definition for TIM_CCR5 register *******************/
|
|
|
+#define TIM_CCR5_CCR5_Pos (0U)
|
|
|
+#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
|
|
+#define TIM_CCR5_GC5C1_Pos (29U)
|
|
|
+#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
|
|
+#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
|
|
|
+#define TIM_CCR5_GC5C2_Pos (30U)
|
|
|
+#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
|
|
|
+#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
|
|
|
+#define TIM_CCR5_GC5C3_Pos (31U)
|
|
|
+#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
|
|
|
+#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
|
|
|
+
|
|
|
+/******************* Bit definition for TIM_CCR6 register *******************/
|
|
|
+#define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /*!<Capture/Compare 6 Value */
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|
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+
|
|
|
+/******************* Bit definition for TIM1_AF1 register *******************/
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|
|
+#define TIM1_AF1_BKINE_Pos (0U)
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|
|
+#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
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|
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+#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
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|
|
+#define TIM1_AF1_BKDF1BKE_Pos (8U)
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|
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+#define TIM1_AF1_BKDF1BKE_Msk (0x1UL << TIM1_AF1_BKDF1BKE_Pos) /*!< 0x00000100 */
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|
|
+#define TIM1_AF1_BKDF1BKE TIM1_AF1_BKDF1BKE_Msk /*!<BRK DFSDM1_BREAK enable */
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|
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+#define TIM1_AF1_BKINP_Pos (9U)
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+#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
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|
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+#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
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|
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+
|
|
|
+/******************* Bit definition for TIM1_AF2 register *******************/
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+#define TIM1_AF2_BK2INE_Pos (0U)
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+#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
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+#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
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|
|
+#define TIM1_AF2_BK2DF1BKE_Pos (8U)
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+#define TIM1_AF2_BK2DF1BKE_Msk (0x1UL << TIM1_AF2_BK2DF1BKE_Pos) /*!< 0x00000100 */
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|
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+#define TIM1_AF2_BK2DF1BKE TIM1_AF2_BK2DF1BKE_Msk /*!<BRK2 DFSDM1_BREAK enable */
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+#define TIM1_AF2_BK2INP_Pos (9U)
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+#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
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+#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK BKIN input polarity */
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+
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+/******************* Bit definition for TIM8_AF1 register *******************/
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+#define TIM8_AF1_BKINE_Pos (0U)
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+#define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
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+#define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BRK BKIN input enable */
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+#define TIM8_AF1_BKDF1BKE_Pos (8U)
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+#define TIM8_AF1_BKDF1BKE_Msk (0x1UL << TIM8_AF1_BKDF1BKE_Pos) /*!< 0x00000100 */
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+#define TIM8_AF1_BKDF1BKE TIM8_AF1_BKDF1BKE_Msk /*!<BRK DFSDM1_BREAK enable */
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+#define TIM8_AF1_BKINP_Pos (9U)
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+#define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
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+#define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
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+
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+/******************* Bit definition for TIM8_AF2 register *******************/
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+#define TIM8_AF2_BK2INE_Pos (0U)
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+#define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
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+#define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
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+#define TIM8_AF2_BK2DF1BKE_Pos (8U)
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+#define TIM8_AF2_BK2DF1BKE_Msk (0x1UL << TIM8_AF2_BK2DF1BKE_Pos) /*!< 0x00000100 */
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+#define TIM8_AF2_BK2DF1BKE TIM8_AF2_BK2DF1BKE_Msk /*!<BRK2 DFSDM1_BREAK enable */
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+#define TIM8_AF2_BK2INP_Pos (9U)
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+#define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
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+#define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRK BKIN input polarity */
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+
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+
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+/******************************************************************************/
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|
+/* */
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|
|
+/* Low Power Timer (LPTIM) */
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+/* */
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+/******************************************************************************/
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+/****************** Bit definition for LPTIM_ISR register *******************/
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+#define LPTIM_ISR_CMPM_Pos (0U)
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+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
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+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
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+#define LPTIM_ISR_ARRM_Pos (1U)
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+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
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+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
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+#define LPTIM_ISR_EXTTRIG_Pos (2U)
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+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
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+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
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+#define LPTIM_ISR_CMPOK_Pos (3U)
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+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
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+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
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+#define LPTIM_ISR_ARROK_Pos (4U)
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+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
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+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
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+#define LPTIM_ISR_UP_Pos (5U)
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+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
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+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
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|
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+#define LPTIM_ISR_DOWN_Pos (6U)
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+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
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+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
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+
|
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|
+/****************** Bit definition for LPTIM_ICR register *******************/
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+#define LPTIM_ICR_CMPMCF_Pos (0U)
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+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
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+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
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|
|
+#define LPTIM_ICR_ARRMCF_Pos (1U)
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+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
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|
|
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
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|
|
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
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|
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
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|
|
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
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|
|
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
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+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
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|
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
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+#define LPTIM_ICR_ARROKCF_Pos (4U)
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|
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
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|
|
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
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|
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+#define LPTIM_ICR_UPCF_Pos (5U)
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|
|
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
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|
|
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
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+#define LPTIM_ICR_DOWNCF_Pos (6U)
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|
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
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|
|
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
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+
|
|
|
+/****************** Bit definition for LPTIM_IER register *******************/
|
|
|
+#define LPTIM_IER_CMPMIE_Pos (0U)
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|
|
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
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|
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
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+#define LPTIM_IER_ARRMIE_Pos (1U)
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+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
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+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
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+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
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+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
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+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
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+#define LPTIM_IER_CMPOKIE_Pos (3U)
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|
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
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|
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
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+#define LPTIM_IER_ARROKIE_Pos (4U)
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+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
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+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
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|
+#define LPTIM_IER_UPIE_Pos (5U)
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|
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
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|
|
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
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|
+#define LPTIM_IER_DOWNIE_Pos (6U)
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|
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
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|
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
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+
|
|
|
+/****************** Bit definition for LPTIM_CFGR register*******************/
|
|
|
+#define LPTIM_CFGR_CKSEL_Pos (0U)
|
|
|
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
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|
|
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
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|
|
+
|
|
|
+#define LPTIM_CFGR_CKPOL_Pos (1U)
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|
|
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
|
|
|
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
|
|
|
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
|
|
|
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
|
|
|
+
|
|
|
+#define LPTIM_CFGR_CKFLT_Pos (3U)
|
|
|
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
|
|
|
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
|
|
|
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
|
|
|
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
|
|
|
+
|
|
|
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
|
|
|
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
|
|
|
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
|
|
|
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
|
|
|
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
|
|
|
+
|
|
|
+#define LPTIM_CFGR_PRESC_Pos (9U)
|
|
|
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
|
|
|
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
|
|
|
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
|
|
|
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
|
|
|
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
|
|
|
+
|
|
|
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
|
|
|
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
|
|
|
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
|
|
|
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
|
|
|
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
|
|
|
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
|
|
|
+
|
|
|
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
|
|
|
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
|
|
|
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
|
|
|
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
|
|
|
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
|
|
|
+
|
|
|
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
|
|
|
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
|
|
|
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
|
|
|
+#define LPTIM_CFGR_WAVE_Pos (20U)
|
|
|
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
|
|
|
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
|
|
|
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
|
|
|
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
|
|
|
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
|
|
|
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
|
|
|
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
|
|
|
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
|
|
|
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
|
|
|
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
|
|
|
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
|
|
|
+#define LPTIM_CFGR_ENC_Pos (24U)
|
|
|
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
|
|
|
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
|
|
|
+
|
|
|
+/****************** Bit definition for LPTIM_CR register ********************/
|
|
|
+#define LPTIM_CR_ENABLE_Pos (0U)
|
|
|
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
|
|
|
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
|
|
|
+#define LPTIM_CR_SNGSTRT_Pos (1U)
|
|
|
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
|
|
|
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
|
|
|
+#define LPTIM_CR_CNTSTRT_Pos (2U)
|
|
|
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
|
|
|
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
|
|
|
+
|
|
|
+/****************** Bit definition for LPTIM_CMP register *******************/
|
|
|
+#define LPTIM_CMP_CMP_Pos (0U)
|
|
|
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
|
|
|
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
|
|
|
+
|
|
|
+/****************** Bit definition for LPTIM_ARR register *******************/
|
|
|
+#define LPTIM_ARR_ARR_Pos (0U)
|
|
|
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
|
|
|
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
|
|
|
+
|
|
|
+/****************** Bit definition for LPTIM_CNT register *******************/
|
|
|
+#define LPTIM_CNT_CNT_Pos (0U)
|
|
|
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
|
|
|
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/****************** Bit definition for USART_CR1 register *******************/
|
|
|
+#define USART_CR1_UE_Pos (0U)
|
|
|
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
|
|
|
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
|
|
|
+#define USART_CR1_UESM_Pos (1U)
|
|
|
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
|
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+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable In Stop Mode */
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+#define USART_CR1_RE_Pos (2U)
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+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
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+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
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+#define USART_CR1_TE_Pos (3U)
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+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
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+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
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+#define USART_CR1_IDLEIE_Pos (4U)
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+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
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+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
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+#define USART_CR1_RXNEIE_Pos (5U)
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+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
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+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
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+#define USART_CR1_TCIE_Pos (6U)
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+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
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+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
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+#define USART_CR1_TXEIE_Pos (7U)
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+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
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+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
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+#define USART_CR1_PEIE_Pos (8U)
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+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
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+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
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+#define USART_CR1_PS_Pos (9U)
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+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
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+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
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+#define USART_CR1_PCE_Pos (10U)
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+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
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+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
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+#define USART_CR1_WAKE_Pos (11U)
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+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
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+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
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+#define USART_CR1_M_Pos (12U)
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+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
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+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
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+#define USART_CR1_M0 (0x00001UL << USART_CR1_M_Pos) /*!< 0x00001000 */
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+#define USART_CR1_MME_Pos (13U)
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+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
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+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
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+#define USART_CR1_CMIE_Pos (14U)
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+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
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+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
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+#define USART_CR1_OVER8_Pos (15U)
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+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
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+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
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+#define USART_CR1_DEDT_Pos (16U)
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+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
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+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
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+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
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+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
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+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
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+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
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+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
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+#define USART_CR1_DEAT_Pos (21U)
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+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
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+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
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+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
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+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
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+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
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+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
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+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
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+#define USART_CR1_RTOIE_Pos (26U)
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+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
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+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
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+#define USART_CR1_EOBIE_Pos (27U)
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+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
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+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
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+#define USART_CR1_M1 0x10000000U /*!< Word length - Bit 1 */
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+
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+/* Legacy defines */
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+#define USART_CR1_M_0 USART_CR1_M0 /*!< Word length - Bit 0 */
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+#define USART_CR1_M_1 USART_CR1_M1 /*!< Word length - Bit 1 */
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+
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+/****************** Bit definition for USART_CR2 register *******************/
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+#define USART_CR2_ADDM7_Pos (4U)
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+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
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+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
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+#define USART_CR2_LBDL_Pos (5U)
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+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
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+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
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+#define USART_CR2_LBDIE_Pos (6U)
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+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
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+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
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+#define USART_CR2_LBCL_Pos (8U)
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+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
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+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
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+#define USART_CR2_CPHA_Pos (9U)
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+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
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+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
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+#define USART_CR2_CPOL_Pos (10U)
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+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
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+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
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+#define USART_CR2_CLKEN_Pos (11U)
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+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
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+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
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+#define USART_CR2_STOP_Pos (12U)
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+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
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+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
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+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
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+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
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+#define USART_CR2_LINEN_Pos (14U)
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+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
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+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
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+#define USART_CR2_SWAP_Pos (15U)
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+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
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+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
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+#define USART_CR2_RXINV_Pos (16U)
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+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
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+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
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+#define USART_CR2_TXINV_Pos (17U)
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+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
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+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
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+#define USART_CR2_DATAINV_Pos (18U)
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+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
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+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
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+#define USART_CR2_MSBFIRST_Pos (19U)
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+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
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+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
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+#define USART_CR2_ABREN_Pos (20U)
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+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
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+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable */
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+#define USART_CR2_ABRMODE_Pos (21U)
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+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
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+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
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+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
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+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
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+#define USART_CR2_RTOEN_Pos (23U)
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+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
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+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
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+#define USART_CR2_ADD_Pos (24U)
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+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
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+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
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+
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+/****************** Bit definition for USART_CR3 register *******************/
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+#define USART_CR3_EIE_Pos (0U)
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+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
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+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
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+#define USART_CR3_IREN_Pos (1U)
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+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
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+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
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+#define USART_CR3_IRLP_Pos (2U)
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+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
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+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
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+#define USART_CR3_HDSEL_Pos (3U)
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+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
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+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
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+#define USART_CR3_NACK_Pos (4U)
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+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
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+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
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+#define USART_CR3_SCEN_Pos (5U)
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+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
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+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
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+#define USART_CR3_DMAR_Pos (6U)
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+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
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+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
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+#define USART_CR3_DMAT_Pos (7U)
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+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
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+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
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+#define USART_CR3_RTSE_Pos (8U)
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+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
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+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
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+#define USART_CR3_CTSE_Pos (9U)
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+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
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+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
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+#define USART_CR3_CTSIE_Pos (10U)
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+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
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+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
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+#define USART_CR3_ONEBIT_Pos (11U)
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+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
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+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
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+#define USART_CR3_OVRDIS_Pos (12U)
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+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
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+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
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+#define USART_CR3_DDRE_Pos (13U)
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+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
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+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
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+#define USART_CR3_DEM_Pos (14U)
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+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
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+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
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+#define USART_CR3_DEP_Pos (15U)
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+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
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+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
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+#define USART_CR3_SCARCNT_Pos (17U)
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+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
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+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
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+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
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+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
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+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
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+#define USART_CR3_WUS_Pos (20U)
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+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
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+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
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+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
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+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
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+#define USART_CR3_WUFIE_Pos (22U)
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+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
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+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
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+#define USART_CR3_UCESM_Pos (23U)
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+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
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+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< USART Clock enable in Stop mode */
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+
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+/****************** Bit definition for USART_BRR register *******************/
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+#define USART_BRR_DIV_FRACTION_Pos (0U)
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+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
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+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
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+#define USART_BRR_DIV_MANTISSA_Pos (4U)
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+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
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+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
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+
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+/****************** Bit definition for USART_GTPR register ******************/
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+#define USART_GTPR_PSC_Pos (0U)
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+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
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+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
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+#define USART_GTPR_GT_Pos (8U)
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+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
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+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
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+
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+
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+/******************* Bit definition for USART_RTOR register *****************/
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+#define USART_RTOR_RTO_Pos (0U)
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+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
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+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
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+#define USART_RTOR_BLEN_Pos (24U)
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+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
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+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
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+
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+/******************* Bit definition for USART_RQR register ******************/
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+#define USART_RQR_ABRRQ_Pos (0U)
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+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
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+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
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+#define USART_RQR_SBKRQ_Pos (1U)
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+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
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+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
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+#define USART_RQR_MMRQ_Pos (2U)
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+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
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+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
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+#define USART_RQR_RXFRQ_Pos (3U)
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+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
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+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
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+#define USART_RQR_TXFRQ_Pos (4U)
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+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
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+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
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+
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+/******************* Bit definition for USART_ISR register ******************/
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+#define USART_ISR_PE_Pos (0U)
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+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
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+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
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+#define USART_ISR_FE_Pos (1U)
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+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
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+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
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+#define USART_ISR_NE_Pos (2U)
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+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
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+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
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+#define USART_ISR_ORE_Pos (3U)
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+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
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+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
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+#define USART_ISR_IDLE_Pos (4U)
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+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
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+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
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+#define USART_ISR_RXNE_Pos (5U)
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+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
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+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
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+#define USART_ISR_TC_Pos (6U)
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+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
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+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
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+#define USART_ISR_TXE_Pos (7U)
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+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
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+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
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+#define USART_ISR_LBDF_Pos (8U)
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+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
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+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
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+#define USART_ISR_CTSIF_Pos (9U)
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+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
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+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
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+#define USART_ISR_CTS_Pos (10U)
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+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
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+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
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+#define USART_ISR_RTOF_Pos (11U)
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+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
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+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
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+#define USART_ISR_EOBF_Pos (12U)
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+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
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+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
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+#define USART_ISR_ABRE_Pos (14U)
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+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
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+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
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+#define USART_ISR_ABRF_Pos (15U)
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+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
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+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
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+#define USART_ISR_BUSY_Pos (16U)
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+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
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+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
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+#define USART_ISR_CMF_Pos (17U)
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+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
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+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
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+#define USART_ISR_SBKF_Pos (18U)
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+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
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+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
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+#define USART_ISR_RWU_Pos (19U)
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+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
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+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
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+#define USART_ISR_WUF_Pos (20U)
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|
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
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+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
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+#define USART_ISR_TEACK_Pos (21U)
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+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
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+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
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+#define USART_ISR_REACK_Pos (22U)
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+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
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+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
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+
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|
|
+/******************* Bit definition for USART_ICR register ******************/
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+#define USART_ICR_PECF_Pos (0U)
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+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
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+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
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+#define USART_ICR_FECF_Pos (1U)
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+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
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+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
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+#define USART_ICR_NCF_Pos (2U)
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+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
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+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
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+#define USART_ICR_ORECF_Pos (3U)
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+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
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+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
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+#define USART_ICR_IDLECF_Pos (4U)
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+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
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+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
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+#define USART_ICR_TCCF_Pos (6U)
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+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
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+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
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+#define USART_ICR_LBDCF_Pos (8U)
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+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
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+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
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+#define USART_ICR_CTSCF_Pos (9U)
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+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
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+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
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+#define USART_ICR_RTOCF_Pos (11U)
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+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
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|
|
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
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|
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+#define USART_ICR_EOBCF_Pos (12U)
|
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+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
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|
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+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
|
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+#define USART_ICR_CMCF_Pos (17U)
|
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+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
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|
|
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
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|
|
+#define USART_ICR_WUCF_Pos (20U)
|
|
|
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
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|
|
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
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|
|
+
|
|
|
+/******************* Bit definition for USART_RDR register ******************/
|
|
|
+#define USART_RDR_RDR_Pos (0U)
|
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+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
|
|
|
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
|
|
|
+
|
|
|
+/******************* Bit definition for USART_TDR register ******************/
|
|
|
+#define USART_TDR_TDR_Pos (0U)
|
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|
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
|
|
|
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Window WATCHDOG */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************* Bit definition for WWDG_CR register ********************/
|
|
|
+#define WWDG_CR_T_Pos (0U)
|
|
|
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
|
|
|
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
|
|
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+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x01 */
|
|
|
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x02 */
|
|
|
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x04 */
|
|
|
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x08 */
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|
|
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x10 */
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|
|
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x20 */
|
|
|
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x40 */
|
|
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+
|
|
|
+
|
|
|
+#define WWDG_CR_WDGA_Pos (7U)
|
|
|
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
|
|
|
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
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|
|
+
|
|
|
+/******************* Bit definition for WWDG_CFR register *******************/
|
|
|
+#define WWDG_CFR_W_Pos (0U)
|
|
|
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
|
|
|
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
|
|
|
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x0001 */
|
|
|
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x0002 */
|
|
|
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x0004 */
|
|
|
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x0008 */
|
|
|
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x0010 */
|
|
|
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x0020 */
|
|
|
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x0040 */
|
|
|
+
|
|
|
+
|
|
|
+#define WWDG_CFR_WDGTB_Pos (7U)
|
|
|
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
|
|
|
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
|
|
|
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
|
|
|
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
|
|
|
+
|
|
|
+
|
|
|
+#define WWDG_CFR_EWI_Pos (9U)
|
|
|
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
|
|
|
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
|
|
|
+
|
|
|
+/******************* Bit definition for WWDG_SR register ********************/
|
|
|
+#define WWDG_SR_EWIF_Pos (0U)
|
|
|
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
|
|
|
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* DBG */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************** Bit definition for DBGMCU_IDCODE register *************/
|
|
|
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
|
|
|
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
|
|
|
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
|
|
|
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
|
|
|
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
|
|
|
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
|
|
|
+
|
|
|
+/******************** Bit definition for DBGMCU_CR register *****************/
|
|
|
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
|
|
|
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
|
|
|
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
|
|
|
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
|
|
|
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
|
|
|
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
|
|
|
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
|
|
|
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
|
|
|
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
|
|
|
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
|
|
|
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
|
|
|
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
|
|
|
+
|
|
|
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
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+#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
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+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
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+#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
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+#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
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+
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+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
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+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
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+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
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+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
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+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
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+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
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+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
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+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
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+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
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+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
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+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
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+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
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+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
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+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
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+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
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+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
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+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
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+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
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+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
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+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U)
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+#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
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+#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
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+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
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+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
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+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
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+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
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+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
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+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos (13U)
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+#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos) /*!< 0x00002000 */
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+#define DBGMCU_APB1_FZ_DBG_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
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+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
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+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
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+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
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+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
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+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
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+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
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+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
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+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
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+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
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+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
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|
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+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
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+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
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+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
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+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
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+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
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+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
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+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
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+
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+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
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+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
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+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
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+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
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+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
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+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
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+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
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+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
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+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
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+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
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+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
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+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
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+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
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+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
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+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
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+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
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+
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+/******************************************************************************/
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+/* */
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|
+/* Ethernet MAC Registers bits definitions */
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+/* */
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|
+/******************************************************************************/
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|
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+/* Bit definition for Ethernet MAC Control Register register */
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+#define ETH_MACCR_WD_Pos (23U)
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+#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
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+#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
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+#define ETH_MACCR_JD_Pos (22U)
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+#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
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+#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
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+#define ETH_MACCR_IFG_Pos (17U)
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|
+#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
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|
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+#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
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+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
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+#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
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+#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
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+#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
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+#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
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+#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
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+#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
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+#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
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+#define ETH_MACCR_CSD_Pos (16U)
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|
+#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
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|
+#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
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|
|
+#define ETH_MACCR_FES_Pos (14U)
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|
|
+#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
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|
|
+#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
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|
|
+#define ETH_MACCR_ROD_Pos (13U)
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|
|
+#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
|
|
|
+#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
|
|
|
+#define ETH_MACCR_LM_Pos (12U)
|
|
|
+#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
|
|
|
+#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
|
|
|
+#define ETH_MACCR_DM_Pos (11U)
|
|
|
+#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
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|
|
+#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
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|
+#define ETH_MACCR_IPCO_Pos (10U)
|
|
|
+#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
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|
|
+#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
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|
|
+#define ETH_MACCR_RD_Pos (9U)
|
|
|
+#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
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|
+#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
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|
+#define ETH_MACCR_APCS_Pos (7U)
|
|
|
+#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
|
|
|
+#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
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|
|
+#define ETH_MACCR_BL_Pos (5U)
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|
|
+#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
|
|
|
+#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
|
|
|
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
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|
|
+#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
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|
+#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
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|
+#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
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+#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
|
|
|
+#define ETH_MACCR_DC_Pos (4U)
|
|
|
+#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
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|
|
+#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
|
|
|
+#define ETH_MACCR_TE_Pos (3U)
|
|
|
+#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
|
|
|
+#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
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|
|
+#define ETH_MACCR_RE_Pos (2U)
|
|
|
+#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
|
|
|
+#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
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|
+
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|
|
+/* Bit definition for Ethernet MAC Frame Filter Register */
|
|
|
+#define ETH_MACFFR_RA_Pos (31U)
|
|
|
+#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
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|
|
+#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
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|
+#define ETH_MACFFR_HPF_Pos (10U)
|
|
|
+#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
|
|
|
+#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
|
|
|
+#define ETH_MACFFR_SAF_Pos (9U)
|
|
|
+#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
|
|
|
+#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
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|
|
+#define ETH_MACFFR_SAIF_Pos (8U)
|
|
|
+#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
|
|
|
+#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
|
|
|
+#define ETH_MACFFR_PCF_Pos (6U)
|
|
|
+#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
|
|
|
+#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
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|
|
+#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
|
|
|
+#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
|
|
|
+#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
|
|
|
+#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
|
|
|
+#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
|
|
|
+#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
|
|
|
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
|
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|
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
|
|
|
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
|
|
|
+#define ETH_MACFFR_BFD_Pos (5U)
|
|
|
+#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
|
|
|
+#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
|
|
|
+#define ETH_MACFFR_PAM_Pos (4U)
|
|
|
+#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
|
|
|
+#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
|
|
|
+#define ETH_MACFFR_DAIF_Pos (3U)
|
|
|
+#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
|
|
|
+#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
|
|
|
+#define ETH_MACFFR_HM_Pos (2U)
|
|
|
+#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
|
|
|
+#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
|
|
|
+#define ETH_MACFFR_HU_Pos (1U)
|
|
|
+#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
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|
|
+#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
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|
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+#define ETH_MACFFR_PM_Pos (0U)
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|
+#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
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|
|
+#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
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+
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|
|
+/* Bit definition for Ethernet MAC Hash Table High Register */
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+#define ETH_MACHTHR_HTH_Pos (0U)
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+#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
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|
|
+#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
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|
+
|
|
|
+/* Bit definition for Ethernet MAC Hash Table Low Register */
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|
+#define ETH_MACHTLR_HTL_Pos (0U)
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+#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
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|
|
+#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
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+
|
|
|
+/* Bit definition for Ethernet MAC MII Address Register */
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|
|
+#define ETH_MACMIIAR_PA_Pos (11U)
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+#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
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+#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
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+#define ETH_MACMIIAR_MR_Pos (6U)
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+#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
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+#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
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+#define ETH_MACMIIAR_CR_Pos (2U)
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+#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
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+#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
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+#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
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+#define ETH_MACMIIAR_CR_Div62_Pos (2U)
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+#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
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+#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
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+#define ETH_MACMIIAR_CR_Div16_Pos (3U)
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+#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
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+#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
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+#define ETH_MACMIIAR_CR_Div26_Pos (2U)
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+#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
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+#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
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+#define ETH_MACMIIAR_CR_Div102_Pos (4U)
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+#define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
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+#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
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+#define ETH_MACMIIAR_MW_Pos (1U)
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+#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
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+#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
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+#define ETH_MACMIIAR_MB_Pos (0U)
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|
+#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
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|
+#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
|
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+
|
|
|
+/* Bit definition for Ethernet MAC MII Data Register */
|
|
|
+#define ETH_MACMIIDR_MD_Pos (0U)
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|
+#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
|
|
|
+#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
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+
|
|
|
+/* Bit definition for Ethernet MAC Flow Control Register */
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|
+#define ETH_MACFCR_PT_Pos (16U)
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|
+#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
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|
|
+#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
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|
+#define ETH_MACFCR_ZQPD_Pos (7U)
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|
+#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
|
|
|
+#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
|
|
|
+#define ETH_MACFCR_PLT_Pos (4U)
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|
+#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
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|
+#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
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|
|
+#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
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|
|
+#define ETH_MACFCR_PLT_Minus28_Pos (4U)
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|
|
+#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
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|
+#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
|
|
|
+#define ETH_MACFCR_PLT_Minus144_Pos (5U)
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|
|
+#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
|
|
|
+#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
|
|
|
+#define ETH_MACFCR_PLT_Minus256_Pos (4U)
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|
|
+#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
|
|
|
+#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
|
|
|
+#define ETH_MACFCR_UPFD_Pos (3U)
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|
|
+#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
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|
|
+#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
|
|
|
+#define ETH_MACFCR_RFCE_Pos (2U)
|
|
|
+#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
|
|
|
+#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
|
|
|
+#define ETH_MACFCR_TFCE_Pos (1U)
|
|
|
+#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
|
|
|
+#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
|
|
|
+#define ETH_MACFCR_FCBBPA_Pos (0U)
|
|
|
+#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
|
|
|
+#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC VLAN Tag Register */
|
|
|
+#define ETH_MACVLANTR_VLANTC_Pos (16U)
|
|
|
+#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
|
|
|
+#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
|
|
|
+#define ETH_MACVLANTR_VLANTI_Pos (0U)
|
|
|
+#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
|
|
|
+#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
|
|
|
+#define ETH_MACRWUFFR_D_Pos (0U)
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|
+#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
|
|
|
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
|
|
|
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
|
|
|
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
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|
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
|
|
|
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
|
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|
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
|
|
|
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
|
|
|
+ RSVD - Filter1 Command - RSVD - Filter0 Command
|
|
|
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
|
|
|
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
|
|
|
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
|
|
|
+#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
|
|
|
+#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
|
|
|
+#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
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|
|
+#define ETH_MACPMTCSR_GU_Pos (9U)
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|
|
+#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
|
|
|
+#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
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|
|
+#define ETH_MACPMTCSR_WFR_Pos (6U)
|
|
|
+#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
|
|
|
+#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
|
|
|
+#define ETH_MACPMTCSR_MPR_Pos (5U)
|
|
|
+#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
|
|
|
+#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
|
|
|
+#define ETH_MACPMTCSR_WFE_Pos (2U)
|
|
|
+#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
|
|
|
+#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
|
|
|
+#define ETH_MACPMTCSR_MPE_Pos (1U)
|
|
|
+#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
|
|
|
+#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
|
|
|
+#define ETH_MACPMTCSR_PD_Pos (0U)
|
|
|
+#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
|
|
|
+#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC debug Register */
|
|
|
+#define ETH_MACDBGR_TFF_Pos (25U)
|
|
|
+#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
|
|
|
+#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
|
|
|
+#define ETH_MACDBGR_TFNE_Pos (24U)
|
|
|
+#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
|
|
|
+#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
|
|
|
+#define ETH_MACDBGR_TPWA_Pos (22U)
|
|
|
+#define ETH_MACDBGR_TPWA_Msk (0x1UL << ETH_MACDBGR_TPWA_Pos) /*!< 0x00400000 */
|
|
|
+#define ETH_MACDBGR_TPWA ETH_MACDBGR_TPWA_Msk /* Tx FIFO write active */
|
|
|
+#define ETH_MACDBGR_TFRS_Pos (20U)
|
|
|
+#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
|
|
|
+#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
|
|
|
+#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
|
|
|
+#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
|
|
|
+#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
|
|
|
+#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
|
|
|
+#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
|
|
|
+#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
|
|
|
+#define ETH_MACDBGR_TFRS_READ_Pos (20U)
|
|
|
+#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
|
|
|
+#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
|
|
|
+#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
|
|
|
+#define ETH_MACDBGR_MTP_Pos (19U)
|
|
|
+#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
|
|
|
+#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
|
|
|
+#define ETH_MACDBGR_MTFCS_Pos (17U)
|
|
|
+#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
|
|
|
+#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
|
|
|
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
|
|
|
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
|
|
|
+#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
|
|
|
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
|
|
|
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
|
|
|
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
|
|
|
+#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
|
|
|
+#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
|
|
|
+#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
|
|
|
+#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
|
|
|
+#define ETH_MACDBGR_MMTEA_Pos (16U)
|
|
|
+#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
|
|
|
+#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
|
|
|
+#define ETH_MACDBGR_RFFL_Pos (8U)
|
|
|
+#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
|
|
|
+#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
|
|
|
+#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
|
|
|
+#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
|
|
|
+#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
|
|
|
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
|
|
|
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
|
|
|
+#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
|
|
|
+#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
|
|
|
+#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
|
|
|
+#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
|
|
|
+#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
|
|
|
+#define ETH_MACDBGR_RFRCS_Pos (5U)
|
|
|
+#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
|
|
|
+#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
|
|
|
+#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
|
|
|
+#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
|
|
|
+#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
|
|
|
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
|
|
|
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
|
|
|
+#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
|
|
|
+#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
|
|
|
+#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
|
|
|
+#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
|
|
|
+#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
|
|
|
+#define ETH_MACDBGR_RFWRA_Pos (4U)
|
|
|
+#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
|
|
|
+#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
|
|
|
+#define ETH_MACDBGR_MSFRWCS_Pos (1U)
|
|
|
+#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
|
|
|
+#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
|
|
|
+#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
|
|
|
+#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
|
|
|
+#define ETH_MACDBGR_MMRPEA_Pos (0U)
|
|
|
+#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
|
|
|
+#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC Status Register */
|
|
|
+#define ETH_MACSR_TSTS_Pos (9U)
|
|
|
+#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
|
|
|
+#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
|
|
|
+#define ETH_MACSR_MMCTS_Pos (6U)
|
|
|
+#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
|
|
|
+#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
|
|
|
+#define ETH_MACSR_MMMCRS_Pos (5U)
|
|
|
+#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
|
|
|
+#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
|
|
|
+#define ETH_MACSR_MMCS_Pos (4U)
|
|
|
+#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
|
|
|
+#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
|
|
|
+#define ETH_MACSR_PMTS_Pos (3U)
|
|
|
+#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
|
|
|
+#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
|
|
|
+#define ETH_MACIMR_TSTIM_Pos (9U)
|
|
|
+#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
|
|
|
+#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
|
|
|
+#define ETH_MACIMR_PMTIM_Pos (3U)
|
|
|
+#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
|
|
|
+#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC Address0 High Register */
|
|
|
+#define ETH_MACA0HR_MACA0H_Pos (0U)
|
|
|
+#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
|
|
|
+#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC Address0 Low Register */
|
|
|
+#define ETH_MACA0LR_MACA0L_Pos (0U)
|
|
|
+#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC Address1 High Register */
|
|
|
+#define ETH_MACA1HR_AE_Pos (31U)
|
|
|
+#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
|
|
|
+#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
|
|
|
+#define ETH_MACA1HR_SA_Pos (30U)
|
|
|
+#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
|
|
|
+#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
|
|
|
+#define ETH_MACA1HR_MBC_Pos (24U)
|
|
|
+#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
|
|
|
+#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
|
|
+#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
|
|
|
+#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
|
|
|
+#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
|
|
|
+#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
|
|
|
+#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
|
|
|
+#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
|
|
|
+#define ETH_MACA1HR_MACA1H_Pos (0U)
|
|
|
+#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
|
|
|
+#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC Address1 Low Register */
|
|
|
+#define ETH_MACA1LR_MACA1L_Pos (0U)
|
|
|
+#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC Address2 High Register */
|
|
|
+#define ETH_MACA2HR_AE_Pos (31U)
|
|
|
+#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
|
|
|
+#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
|
|
|
+#define ETH_MACA2HR_SA_Pos (30U)
|
|
|
+#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
|
|
|
+#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
|
|
|
+#define ETH_MACA2HR_MBC_Pos (24U)
|
|
|
+#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
|
|
|
+#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
|
|
|
+#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
|
|
|
+#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
|
|
|
+#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
|
|
|
+#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
|
|
|
+#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
|
|
|
+#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
|
|
|
+#define ETH_MACA2HR_MACA2H_Pos (0U)
|
|
|
+#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
|
|
|
+#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC Address2 Low Register */
|
|
|
+#define ETH_MACA2LR_MACA2L_Pos (0U)
|
|
|
+#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC Address3 High Register */
|
|
|
+#define ETH_MACA3HR_AE_Pos (31U)
|
|
|
+#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
|
|
|
+#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
|
|
|
+#define ETH_MACA3HR_SA_Pos (30U)
|
|
|
+#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
|
|
|
+#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
|
|
|
+#define ETH_MACA3HR_MBC_Pos (24U)
|
|
|
+#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
|
|
|
+#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
|
|
|
+#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
|
|
|
+#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
|
|
|
+#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
|
|
|
+#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
|
|
|
+#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
|
|
|
+#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
|
|
|
+#define ETH_MACA3HR_MACA3H_Pos (0U)
|
|
|
+#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
|
|
|
+#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MAC Address3 Low Register */
|
|
|
+#define ETH_MACA3LR_MACA3L_Pos (0U)
|
|
|
+#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* Ethernet MMC Registers bits definition */
|
|
|
+/******************************************************************************/
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MMC Contol Register */
|
|
|
+#define ETH_MMCCR_MCFHP_Pos (5U)
|
|
|
+#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
|
|
|
+#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
|
|
|
+#define ETH_MMCCR_MCP_Pos (4U)
|
|
|
+#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
|
|
|
+#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
|
|
|
+#define ETH_MMCCR_MCF_Pos (3U)
|
|
|
+#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
|
|
|
+#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
|
|
|
+#define ETH_MMCCR_ROR_Pos (2U)
|
|
|
+#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
|
|
|
+#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
|
|
|
+#define ETH_MMCCR_CSR_Pos (1U)
|
|
|
+#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
|
|
|
+#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
|
|
|
+#define ETH_MMCCR_CR_Pos (0U)
|
|
|
+#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
|
|
|
+#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
|
|
|
+#define ETH_MMCRIR_RGUFS_Pos (17U)
|
|
|
+#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
|
|
|
+#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
|
|
|
+#define ETH_MMCRIR_RFAES_Pos (6U)
|
|
|
+#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
|
|
|
+#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
|
|
|
+#define ETH_MMCRIR_RFCES_Pos (5U)
|
|
|
+#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
|
|
|
+#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
|
|
|
+#define ETH_MMCTIR_TGFS_Pos (21U)
|
|
|
+#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
|
|
|
+#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
|
|
|
+#define ETH_MMCTIR_TGFMSCS_Pos (15U)
|
|
|
+#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
|
|
|
+#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
|
|
|
+#define ETH_MMCTIR_TGFSCS_Pos (14U)
|
|
|
+#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
|
|
|
+#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
|
|
|
+#define ETH_MMCRIMR_RGUFM_Pos (17U)
|
|
|
+#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
|
|
|
+#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
|
|
|
+#define ETH_MMCRIMR_RFAEM_Pos (6U)
|
|
|
+#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
|
|
|
+#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
|
|
|
+#define ETH_MMCRIMR_RFCEM_Pos (5U)
|
|
|
+#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
|
|
|
+#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
|
|
|
+#define ETH_MMCTIMR_TGFM_Pos (21U)
|
|
|
+#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
|
|
|
+#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
|
|
|
+#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
|
|
|
+#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
|
|
|
+#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
|
|
|
+#define ETH_MMCTIMR_TGFSCM_Pos (14U)
|
|
|
+#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
|
|
|
+#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
|
|
|
+#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
|
|
|
+#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
|
|
|
+#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
|
|
|
+#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
|
|
|
+#define ETH_MMCTGFCR_TGFC_Pos (0U)
|
|
|
+#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
|
|
|
+#define ETH_MMCRFCECR_RFCEC_Pos (0U)
|
|
|
+#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
|
|
|
+#define ETH_MMCRFAECR_RFAEC_Pos (0U)
|
|
|
+#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
|
|
|
+#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
|
|
|
+#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* Ethernet PTP Registers bits definition */
|
|
|
+/******************************************************************************/
|
|
|
+
|
|
|
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
|
|
|
+#define ETH_PTPTSCR_TSCNT_Pos (16U)
|
|
|
+#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
|
|
|
+#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
|
|
|
+#define ETH_PTPTSSR_TSSMRME_Pos (15U)
|
|
|
+#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
|
|
|
+#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
|
|
+#define ETH_PTPTSSR_TSSEME_Pos (14U)
|
|
|
+#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
|
|
|
+#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
|
|
+#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
|
|
|
+#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
|
|
+#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
|
|
+#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
|
|
|
+#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
|
|
+#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
|
|
+#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
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|
|
+#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
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|
|
+#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
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|
|
+#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
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|
|
+#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
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+#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
|
|
+#define ETH_PTPTSSR_TSSSR_Pos (9U)
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+#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
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+#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
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|
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+#define ETH_PTPTSSR_TSSARFE_Pos (8U)
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+#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
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|
|
+#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
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+
|
|
|
+#define ETH_PTPTSCR_TSARU_Pos (5U)
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+#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
|
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+#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
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|
|
+#define ETH_PTPTSCR_TSITE_Pos (4U)
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+#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
|
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+#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
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|
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+#define ETH_PTPTSCR_TSSTU_Pos (3U)
|
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+#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
|
|
|
+#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
|
|
|
+#define ETH_PTPTSCR_TSSTI_Pos (2U)
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|
+#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
|
|
|
+#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
|
|
|
+#define ETH_PTPTSCR_TSFCU_Pos (1U)
|
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+#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
|
|
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+#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
|
|
|
+#define ETH_PTPTSCR_TSE_Pos (0U)
|
|
|
+#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
|
|
|
+#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
|
|
|
+#define ETH_PTPSSIR_STSSI_Pos (0U)
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|
|
+#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
|
|
|
+#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
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|
|
+
|
|
|
+/* Bit definition for Ethernet PTP Time Stamp High Register */
|
|
|
+#define ETH_PTPTSHR_STS_Pos (0U)
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|
|
+#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
|
|
|
+#define ETH_PTPTSLR_STPNS_Pos (31U)
|
|
|
+#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
|
|
|
+#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
|
|
|
+#define ETH_PTPTSLR_STSS_Pos (0U)
|
|
|
+#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
|
|
|
+#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
|
|
|
+#define ETH_PTPTSHUR_TSUS_Pos (0U)
|
|
|
+#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
|
|
|
+#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
|
|
|
+#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
|
|
|
+#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
|
|
|
+#define ETH_PTPTSLUR_TSUSS_Pos (0U)
|
|
|
+#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
|
|
|
+#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
|
|
|
+#define ETH_PTPTSAR_TSA_Pos (0U)
|
|
|
+#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet PTP Target Time High Register */
|
|
|
+#define ETH_PTPTTHR_TTSH_Pos (0U)
|
|
|
+#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet PTP Target Time Low Register */
|
|
|
+#define ETH_PTPTTLR_TTSL_Pos (0U)
|
|
|
+#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
|
|
|
+#define ETH_PTPTSSR_TSTTR_Pos (5U)
|
|
|
+#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
|
|
|
+#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
|
|
|
+#define ETH_PTPTSSR_TSSO_Pos (4U)
|
|
|
+#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
|
|
|
+#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet PTP PPS Control Register */
|
|
|
+#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
|
|
|
+#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
|
|
|
+#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* Ethernet DMA Registers bits definition */
|
|
|
+/******************************************************************************/
|
|
|
+
|
|
|
+/* Bit definition for Ethernet DMA Bus Mode Register */
|
|
|
+#define ETH_DMABMR_AAB_Pos (25U)
|
|
|
+#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
|
|
|
+#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
|
|
|
+#define ETH_DMABMR_FPM_Pos (24U)
|
|
|
+#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
|
|
|
+#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
|
|
|
+#define ETH_DMABMR_USP_Pos (23U)
|
|
|
+#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
|
|
|
+#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
|
|
|
+#define ETH_DMABMR_RDP_Pos (17U)
|
|
|
+#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
|
|
|
+#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
|
|
|
+#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
|
|
|
+#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
|
|
|
+#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
|
|
|
+#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
|
|
|
+#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
|
|
|
+#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
|
|
|
+#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
|
|
|
+#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
|
|
|
+#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
|
|
|
+#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
|
|
|
+#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
|
|
|
+#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
|
|
|
+#define ETH_DMABMR_FB_Pos (16U)
|
|
|
+#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
|
|
|
+#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
|
|
|
+#define ETH_DMABMR_RTPR_Pos (14U)
|
|
|
+#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
|
|
|
+#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
|
|
|
+#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
|
|
|
+#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
|
|
|
+#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
|
|
|
+#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
|
|
|
+#define ETH_DMABMR_PBL_Pos (8U)
|
|
|
+#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
|
|
|
+#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
|
|
|
+#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
|
|
|
+#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
|
|
|
+#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
|
|
|
+#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
|
|
|
+#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
|
|
|
+#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
|
|
|
+#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
|
|
|
+#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
|
|
|
+#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
|
|
|
+#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
|
|
|
+#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
|
|
|
+#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
|
|
|
+#define ETH_DMABMR_EDE_Pos (7U)
|
|
|
+#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
|
|
|
+#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
|
|
|
+#define ETH_DMABMR_DSL_Pos (2U)
|
|
|
+#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
|
|
|
+#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
|
|
|
+#define ETH_DMABMR_DA_Pos (1U)
|
|
|
+#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
|
|
|
+#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
|
|
|
+#define ETH_DMABMR_SR_Pos (0U)
|
|
|
+#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
|
|
|
+#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
|
|
|
+#define ETH_DMATPDR_TPD_Pos (0U)
|
|
|
+#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
|
|
|
+#define ETH_DMARPDR_RPD_Pos (0U)
|
|
|
+#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
|
|
|
+#define ETH_DMARDLAR_SRL_Pos (0U)
|
|
|
+#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
|
|
|
+#define ETH_DMATDLAR_STL_Pos (0U)
|
|
|
+#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet DMA Status Register */
|
|
|
+#define ETH_DMASR_TSTS_Pos (29U)
|
|
|
+#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
|
|
|
+#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
|
|
|
+#define ETH_DMASR_PMTS_Pos (28U)
|
|
|
+#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
|
|
|
+#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
|
|
|
+#define ETH_DMASR_MMCS_Pos (27U)
|
|
|
+#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
|
|
|
+#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
|
|
|
+#define ETH_DMASR_EBS_Pos (23U)
|
|
|
+#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
|
|
|
+#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
|
|
|
+ /* combination with EBS[2:0] for GetFlagStatus function */
|
|
|
+#define ETH_DMASR_EBS_DescAccess_Pos (25U)
|
|
|
+#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
|
|
|
+#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
|
|
|
+#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
|
|
|
+#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
|
|
|
+#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
|
|
|
+#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
|
|
|
+#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
|
|
|
+#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
|
|
|
+#define ETH_DMASR_TPS_Pos (20U)
|
|
|
+#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
|
|
|
+#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
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+#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
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+#define ETH_DMASR_TPS_Fetching_Pos (20U)
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+#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
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+#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
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+#define ETH_DMASR_TPS_Waiting_Pos (21U)
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+#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
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+#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
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+#define ETH_DMASR_TPS_Reading_Pos (20U)
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+#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
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+#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
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+#define ETH_DMASR_TPS_Suspended_Pos (21U)
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+#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
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+#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
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+#define ETH_DMASR_TPS_Closing_Pos (20U)
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+#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
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+#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
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+#define ETH_DMASR_RPS_Pos (17U)
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+#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
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+#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
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+#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
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+#define ETH_DMASR_RPS_Fetching_Pos (17U)
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+#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
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+#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
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+#define ETH_DMASR_RPS_Waiting_Pos (17U)
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+#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
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+#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
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+#define ETH_DMASR_RPS_Suspended_Pos (19U)
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+#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
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+#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
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+#define ETH_DMASR_RPS_Closing_Pos (17U)
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+#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
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+#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
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+#define ETH_DMASR_RPS_Queuing_Pos (17U)
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+#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
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+#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
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+#define ETH_DMASR_NIS_Pos (16U)
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+#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
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+#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
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+#define ETH_DMASR_AIS_Pos (15U)
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+#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
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+#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
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+#define ETH_DMASR_ERS_Pos (14U)
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+#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
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+#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
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+#define ETH_DMASR_FBES_Pos (13U)
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+#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
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+#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
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+#define ETH_DMASR_ETS_Pos (10U)
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+#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
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+#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
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+#define ETH_DMASR_RWTS_Pos (9U)
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+#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
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+#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
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+#define ETH_DMASR_RPSS_Pos (8U)
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+#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
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+#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
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+#define ETH_DMASR_RBUS_Pos (7U)
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+#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
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+#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
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+#define ETH_DMASR_RS_Pos (6U)
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+#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
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+#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
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+#define ETH_DMASR_TUS_Pos (5U)
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+#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
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+#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
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+#define ETH_DMASR_ROS_Pos (4U)
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+#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
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+#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
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+#define ETH_DMASR_TJTS_Pos (3U)
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+#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
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+#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
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+#define ETH_DMASR_TBUS_Pos (2U)
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+#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
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+#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
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+#define ETH_DMASR_TPSS_Pos (1U)
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+#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
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+#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
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+#define ETH_DMASR_TS_Pos (0U)
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+#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
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+#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
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+
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|
|
+/* Bit definition for Ethernet DMA Operation Mode Register */
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+#define ETH_DMAOMR_DTCEFD_Pos (26U)
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+#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
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+#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
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+#define ETH_DMAOMR_RSF_Pos (25U)
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+#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
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+#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
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+#define ETH_DMAOMR_DFRF_Pos (24U)
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+#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
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+#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
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+#define ETH_DMAOMR_TSF_Pos (21U)
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+#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
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+#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
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+#define ETH_DMAOMR_FTF_Pos (20U)
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+#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
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+#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
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+#define ETH_DMAOMR_TTC_Pos (14U)
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+#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
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+#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
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+#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
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+#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
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+#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
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+#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
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+#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
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+#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
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+#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
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+#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
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+#define ETH_DMAOMR_ST_Pos (13U)
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+#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
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+#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
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+#define ETH_DMAOMR_FEF_Pos (7U)
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+#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
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+#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
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+#define ETH_DMAOMR_FUGF_Pos (6U)
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+#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
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+#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
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+#define ETH_DMAOMR_RTC_Pos (3U)
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+#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
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+#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
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+#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
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+#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
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+#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
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+#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
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+#define ETH_DMAOMR_OSF_Pos (2U)
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+#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
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+#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
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+#define ETH_DMAOMR_SR_Pos (1U)
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+#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
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+#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
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+
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|
|
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
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|
+#define ETH_DMAIER_NISE_Pos (16U)
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+#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
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+#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
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+#define ETH_DMAIER_AISE_Pos (15U)
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+#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
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+#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
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+#define ETH_DMAIER_ERIE_Pos (14U)
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|
+#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
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+#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
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+#define ETH_DMAIER_FBEIE_Pos (13U)
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+#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
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+#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
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+#define ETH_DMAIER_ETIE_Pos (10U)
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+#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
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+#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
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+#define ETH_DMAIER_RWTIE_Pos (9U)
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+#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
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+#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
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+#define ETH_DMAIER_RPSIE_Pos (8U)
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|
+#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
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+#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
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+#define ETH_DMAIER_RBUIE_Pos (7U)
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+#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
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|
+#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
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+#define ETH_DMAIER_RIE_Pos (6U)
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+#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
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+#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
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+#define ETH_DMAIER_TUIE_Pos (5U)
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+#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
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+#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
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|
+#define ETH_DMAIER_ROIE_Pos (4U)
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|
+#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
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+#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
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|
+#define ETH_DMAIER_TJTIE_Pos (3U)
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|
+#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
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|
+#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
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|
+#define ETH_DMAIER_TBUIE_Pos (2U)
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|
+#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
|
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|
+#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
|
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|
+#define ETH_DMAIER_TPSIE_Pos (1U)
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|
+#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
|
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|
+#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
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|
|
+#define ETH_DMAIER_TIE_Pos (0U)
|
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|
+#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
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|
+#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
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|
+
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|
|
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
|
|
|
+#define ETH_DMAMFBOCR_OFOC_Pos (28U)
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|
+#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
|
|
|
+#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
|
|
|
+#define ETH_DMAMFBOCR_MFA_Pos (17U)
|
|
|
+#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
|
|
|
+#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
|
|
|
+#define ETH_DMAMFBOCR_OMFC_Pos (16U)
|
|
|
+#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
|
|
|
+#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
|
|
|
+#define ETH_DMAMFBOCR_MFC_Pos (0U)
|
|
|
+#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
|
|
|
+#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
|
|
|
+#define ETH_DMACHTDR_HTDAP_Pos (0U)
|
|
|
+#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
|
|
|
+#define ETH_DMACHRDR_HRDAP_Pos (0U)
|
|
|
+#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
|
|
|
+#define ETH_DMACHTBAR_HTBAP_Pos (0U)
|
|
|
+#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
|
|
|
+
|
|
|
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
|
|
|
+#define ETH_DMACHRBAR_HRBAP_Pos (0U)
|
|
|
+#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
|
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|
+#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
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+
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+/******************************************************************************/
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+/* */
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+/* USB_OTG */
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+/* */
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+/******************************************************************************/
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+/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
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+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
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+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
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+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
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+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
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+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
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+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
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+#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
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+#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
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+#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
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+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
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+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
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+#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
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+#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
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+#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
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+#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
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+#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
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+#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
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+#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
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+#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
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+#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
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+#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
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+#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
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+#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
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+#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
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+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
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+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
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+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
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+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
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+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
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+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
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+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
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+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
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+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
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+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
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+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
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+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
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+#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
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+#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
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+#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
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+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
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+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
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+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
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+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
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+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
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+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
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+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
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+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
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+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
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+#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
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+#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
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+#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
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+#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
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+#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
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+#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
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+
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+/******************** Bit definition for USB_OTG_HCFG register ********************/
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+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
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+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
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+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
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+#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
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|
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+#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
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|
|
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
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|
+#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
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|
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
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+
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+/******************** Bit definition for USB_OTG_DCFG register ********************/
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|
|
+#define USB_OTG_DCFG_DSPD_Pos (0U)
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+#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
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+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
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+#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
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+#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
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+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
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+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
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+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
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+
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|
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+#define USB_OTG_DCFG_DAD_Pos (4U)
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+#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
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+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
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+#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
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+#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
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+#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
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+#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
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+#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
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+#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
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+#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
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+
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+#define USB_OTG_DCFG_PFIVL_Pos (11U)
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+#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
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+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
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+#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
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+#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
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+
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+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
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+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
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+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
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+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
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+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
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+
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+/******************** Bit definition for USB_OTG_PCGCR register ********************/
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+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
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+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
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+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
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+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
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+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
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+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
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+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
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+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
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+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
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+
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|
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+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
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+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
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+#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
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|
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+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
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+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
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+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
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+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
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|
|
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
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|
|
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
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+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
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+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
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|
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
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+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
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|
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
|
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|
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
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+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
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+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
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|
|
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
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|
|
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
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|
+#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
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|
|
+#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
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+#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
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+
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|
|
+/******************** Bit definition for USB_OTG_DCTL register ********************/
|
|
|
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
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+#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
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|
|
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
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+#define USB_OTG_DCTL_SDIS_Pos (1U)
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|
+#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
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|
|
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
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|
|
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
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|
+#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
|
|
|
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
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|
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
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|
|
+#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
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|
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
|
|
|
+
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|
|
+#define USB_OTG_DCTL_TCTL_Pos (4U)
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|
+#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
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|
|
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
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|
+#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
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|
|
+#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
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|
|
+#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
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|
|
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
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|
|
+#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
|
|
|
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
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|
|
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
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|
|
+#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
|
|
|
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
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|
|
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
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|
|
+#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
|
|
|
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
|
|
|
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
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|
|
+#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
|
|
|
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
|
|
|
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
|
|
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
|
|
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
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|
|
+
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|
|
+/******************** Bit definition for USB_OTG_HFIR register ********************/
|
|
|
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
|
|
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
|
|
|
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
|
|
|
+
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|
|
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
|
|
|
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
|
|
|
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
|
|
|
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
|
|
|
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
|
|
|
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
|
|
|
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
|
|
|
+
|
|
|
+/******************** Bit definition for USB_OTG_DSTS register ********************/
|
|
|
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
|
|
|
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
|
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+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
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+
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+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
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+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
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+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
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+#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
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+#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
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+#define USB_OTG_DSTS_EERR_Pos (3U)
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+#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
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+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
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+#define USB_OTG_DSTS_FNSOF_Pos (8U)
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+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
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+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
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+
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+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
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+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
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+#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
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+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
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+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
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+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
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+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
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+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
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+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
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+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
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+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
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+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
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+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
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+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
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+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
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+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
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+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
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+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
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+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
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+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
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+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
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+
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+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
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+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
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+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
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+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
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+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
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+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
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+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
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+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
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+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
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+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
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+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
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+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
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+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
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+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
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+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
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+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
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+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
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+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
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+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
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+#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
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+#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
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+#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
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+#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
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+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
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+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
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+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
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+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
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+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
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+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
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+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
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+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
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+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
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+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
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+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
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+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
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+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
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+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
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+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
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+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
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+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
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+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
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+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
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+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
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+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
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+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
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+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
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+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
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+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
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+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
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+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
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+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
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+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
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+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
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+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
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+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
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+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
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+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
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+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
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+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
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+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
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+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
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+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
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+
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+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
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+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
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+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
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+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
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+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
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+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
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+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
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+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
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+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
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+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
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+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
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+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
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+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
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+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
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+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
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+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
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+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
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+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
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+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
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+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
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+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
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+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
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+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
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+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
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+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
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+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
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+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
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+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
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+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
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+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
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+
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+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
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+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
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+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
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+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
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+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
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+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
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+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
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+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
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+#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
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+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
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+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
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+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
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+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
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+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
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+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
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+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
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+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
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+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
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+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
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+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
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+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
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+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
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+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
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+#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
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+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
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+
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+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
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+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
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+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
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+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
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+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
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+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
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+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
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+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
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+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
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+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
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+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
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+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
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+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
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+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
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+
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+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
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+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
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+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
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+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
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+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
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+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
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+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
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+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
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+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
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+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
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+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
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+
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+/******************** Bit definition for USB_OTG_HAINT register ********************/
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+#define USB_OTG_HAINT_HAINT_Pos (0U)
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+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
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+
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+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
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+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
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+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
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+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
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+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
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+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
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+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
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+#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
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+#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
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+#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
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+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
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+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
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+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
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+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
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+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
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+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
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+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
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+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
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+#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
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+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
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+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
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+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
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+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
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+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
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+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
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+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
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+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
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+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
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+#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
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+#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
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+#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
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+#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
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+#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
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+#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
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+#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
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+#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
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+#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
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+
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+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
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+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
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+#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
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+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
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+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
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+#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
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+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
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+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
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+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
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+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
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+#define USB_OTG_GINTSTS_SOF_Pos (3U)
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+#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
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+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
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+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
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+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
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+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
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+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
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+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
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+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
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+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
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+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
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+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
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+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
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+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
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+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
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+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
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+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
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+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
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+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
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+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
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+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
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+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
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+#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
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+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
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+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
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+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
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+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
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+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
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+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
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+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
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+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
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+#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
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+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
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+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
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+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
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+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
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+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
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+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
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+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
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+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
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+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
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+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
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+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
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+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
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+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
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+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
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+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
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+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
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+#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
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+#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
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+#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
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+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
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+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
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+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
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+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
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+#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
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+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
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+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
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+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
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+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
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+#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
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+#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
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+#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
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+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
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+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
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+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
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+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
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+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
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+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
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+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
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+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
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+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
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+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
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+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
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+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
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+
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+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
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+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
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+#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
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+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
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+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
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+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
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+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
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+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
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+#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
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+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
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+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
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+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
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+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
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+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
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+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
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+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
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+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
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+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
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+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
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+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
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+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
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+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
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+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
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+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
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+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
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+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
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+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
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+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
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+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
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+#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
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+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
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+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
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+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
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+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
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+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
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+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
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+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
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+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
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+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
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+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
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+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
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+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
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+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
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+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
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+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
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+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
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+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
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+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
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+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
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+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
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+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
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+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
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+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
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+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
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+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
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+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
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+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
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+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
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+#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
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+#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
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+#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
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+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
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+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
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+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
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+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
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+#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
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+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
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+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
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+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
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+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
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+#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
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+#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
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+#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
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+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
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+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
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+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
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+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
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+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
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+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
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+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
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+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
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+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
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+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
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+#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
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+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
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+
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+/******************** Bit definition for USB_OTG_DAINT register ********************/
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+#define USB_OTG_DAINT_IEPINT_Pos (0U)
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+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
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+#define USB_OTG_DAINT_OEPINT_Pos (16U)
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+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
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+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
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+
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+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
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+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
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+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
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+
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+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
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+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
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+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
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+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
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+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
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+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
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+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
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+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
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+#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
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+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
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+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
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+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
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+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
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+
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+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
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+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
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+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
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+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
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+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
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+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
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+
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+/******************** Bit definition for OTG register ********************/
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+
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+#define USB_OTG_CHNUM_Pos (0U)
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+#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
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+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
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+#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
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+#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
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+#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
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+#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
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+#define USB_OTG_BCNT_Pos (4U)
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+#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
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+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
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+
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+#define USB_OTG_DPID_Pos (15U)
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+#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
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+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
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+#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
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+#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
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+
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+#define USB_OTG_PKTSTS_Pos (17U)
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+#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
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+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
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+#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
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+#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
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+#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
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+#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
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+
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+#define USB_OTG_EPNUM_Pos (0U)
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+#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
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+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
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+#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
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+#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
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+#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
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+#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
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+
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+#define USB_OTG_FRMNUM_Pos (21U)
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+#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
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+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
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+#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
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+#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
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+#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
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+#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
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+
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+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
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+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
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+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
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+
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+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
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+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
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+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
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+
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+/******************** Bit definition for OTG register ********************/
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+#define USB_OTG_NPTXFSA_Pos (0U)
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+#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
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+#define USB_OTG_NPTXFD_Pos (16U)
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+#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
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+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
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+#define USB_OTG_TX0FSA_Pos (0U)
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+#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
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+#define USB_OTG_TX0FD_Pos (16U)
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+#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
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+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
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+
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+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
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+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
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+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
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+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
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+
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+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
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+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
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+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
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+
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|
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+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
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+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
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+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
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+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
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+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
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+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
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+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
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+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
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+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
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|
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+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
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|
|
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
|
|
|
+
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|
|
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
|
|
|
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
|
|
|
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
|
|
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+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
|
|
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+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
|
|
|
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
|
|
|
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
|
|
|
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
|
|
|
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
|
|
|
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
|
|
|
+
|
|
|
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
|
|
|
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
|
|
|
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
|
|
|
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
|
|
|
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
|
|
|
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
|
|
|
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
|
|
|
+
|
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+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
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+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
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+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
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+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
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+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
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+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
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+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
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+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
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+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
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+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
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+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
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+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
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+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
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+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
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+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
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+
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+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
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+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
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+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
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+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
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+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
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+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
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+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
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+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
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+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
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+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
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+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
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+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
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+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
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+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
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+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
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+
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+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
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+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
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+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
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+
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+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
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+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
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+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
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+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
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+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
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+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
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+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
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+
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+/******************** Bit definition for USB_OTG_GCCFG register ********************/
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+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
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+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
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+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
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+#define USB_OTG_GCCFG_VBDEN_Pos (21U)
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+#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
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+#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
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+
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+/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
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+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
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+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
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+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
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+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
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+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
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+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
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+
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+/******************** Bit definition for USB_OTG_CID register ********************/
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+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
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+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
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+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
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+
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+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
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+#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
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+#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
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+#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
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+#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
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+#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
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+#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
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+#define USB_OTG_GLPMCFG_BESL_Pos (2U)
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+#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
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+#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
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+#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
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+#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
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+#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
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+#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
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+#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
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+#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
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+#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
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+#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
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+#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
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+#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
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+#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
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+#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
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+#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
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+#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
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+#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
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+#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
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+#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
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+#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
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+#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
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+#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
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+#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
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+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
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+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
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+#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
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+#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
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+#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
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+#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
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+#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
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+#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
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+#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
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+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
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+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
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+#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
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+#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
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+#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
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+#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
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+
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+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
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+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
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+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
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+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
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+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
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+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
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+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
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+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
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+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
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+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
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+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
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+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
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+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
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+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
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+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
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+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
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+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
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+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
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+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
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+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
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+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
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+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
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+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
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+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
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+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
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+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
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+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
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+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
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+
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+/******************** Bit definition for USB_OTG_HPRT register ********************/
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+#define USB_OTG_HPRT_PCSTS_Pos (0U)
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+#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
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+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
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+#define USB_OTG_HPRT_PCDET_Pos (1U)
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+#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
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+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
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+#define USB_OTG_HPRT_PENA_Pos (2U)
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+#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
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+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
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+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
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+#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
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+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
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+#define USB_OTG_HPRT_POCA_Pos (4U)
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+#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
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+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
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+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
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+#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
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+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
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+#define USB_OTG_HPRT_PRES_Pos (6U)
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+#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
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+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
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+#define USB_OTG_HPRT_PSUSP_Pos (7U)
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+#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
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+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
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+#define USB_OTG_HPRT_PRST_Pos (8U)
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+#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
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+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
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+
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+#define USB_OTG_HPRT_PLSTS_Pos (10U)
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+#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
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+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
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+#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
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+#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
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+#define USB_OTG_HPRT_PPWR_Pos (12U)
|
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+#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
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+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
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+
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+#define USB_OTG_HPRT_PTCTL_Pos (13U)
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+#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
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+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
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+#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
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+#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
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+#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
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+#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
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+
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+#define USB_OTG_HPRT_PSPD_Pos (17U)
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+#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
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+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
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+#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
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+#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
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+
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+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
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+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
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+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
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+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
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+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
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+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
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+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
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+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
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+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
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+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
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+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
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+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
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+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
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+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
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+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
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+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
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+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
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+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
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+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
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+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
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+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
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+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
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+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
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+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
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+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
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+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
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+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
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+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
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+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
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+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
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+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
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+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
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+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
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+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
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+
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+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
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+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
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+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
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+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
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+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
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+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
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+
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+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
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+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
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+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
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+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
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+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
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+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
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+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
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+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
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+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
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+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
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+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
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+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
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+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
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+
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+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
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+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
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+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
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+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
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+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
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+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
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+#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
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+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
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+
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+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
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+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
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+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
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+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
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+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
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+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
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+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
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+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
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+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
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+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
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+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
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+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
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+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
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+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
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+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
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+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
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+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
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+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
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+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
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+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
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+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
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+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
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+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
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+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
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+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
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+
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+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
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+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
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+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
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+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
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+
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+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
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+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
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+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
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+#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
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+#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
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+#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
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+#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
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+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
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+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
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+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
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+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
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+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
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+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
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+
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+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
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+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
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+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
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+#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
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+#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
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+
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+#define USB_OTG_HCCHAR_MC_Pos (20U)
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+#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
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+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
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+#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
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+#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
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+
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+#define USB_OTG_HCCHAR_DAD_Pos (22U)
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+#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
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+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
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+#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
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+#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
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+#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
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+#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
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+#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
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+#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
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+#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
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+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
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+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
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+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
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+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
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+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
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+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
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+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
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+#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
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+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
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+
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|
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+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
|
|
|
+
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|
|
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
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+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
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+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
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+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
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+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
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+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
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+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
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+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
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+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
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+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
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+
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|
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+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
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+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
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|
|
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
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+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
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+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
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+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
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+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
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+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
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+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
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+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
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+
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+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
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+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
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+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
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+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
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+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
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+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
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+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
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+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
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+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
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+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
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+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
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+
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+/******************** Bit definition for USB_OTG_HCINT register ********************/
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+#define USB_OTG_HCINT_XFRC_Pos (0U)
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+#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
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+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
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+#define USB_OTG_HCINT_CHH_Pos (1U)
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+#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
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+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
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+#define USB_OTG_HCINT_AHBERR_Pos (2U)
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+#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
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+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
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+#define USB_OTG_HCINT_STALL_Pos (3U)
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+#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
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+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
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+#define USB_OTG_HCINT_NAK_Pos (4U)
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+#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
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+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
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+#define USB_OTG_HCINT_ACK_Pos (5U)
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+#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
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+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
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+#define USB_OTG_HCINT_NYET_Pos (6U)
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+#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
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+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
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+#define USB_OTG_HCINT_TXERR_Pos (7U)
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+#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
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+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
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+#define USB_OTG_HCINT_BBERR_Pos (8U)
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+#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
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+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
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+#define USB_OTG_HCINT_FRMOR_Pos (9U)
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+#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
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+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
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+#define USB_OTG_HCINT_DTERR_Pos (10U)
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+#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
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+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
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+
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+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
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+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
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+#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
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+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
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+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
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+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
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+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
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+#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
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+#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
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+#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
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+#define USB_OTG_DIEPINT_TOC_Pos (3U)
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+#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
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+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
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+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
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+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
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+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
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+#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
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+#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
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+#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
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+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
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+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
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+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
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+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
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+#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
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+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
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+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
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+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
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+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
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+#define USB_OTG_DIEPINT_BNA_Pos (9U)
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+#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
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+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
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+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
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+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
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+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
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+#define USB_OTG_DIEPINT_BERR_Pos (12U)
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+#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
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+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
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+#define USB_OTG_DIEPINT_NAK_Pos (13U)
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+#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
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+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
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+
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+/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
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+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
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+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
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+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
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+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
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+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
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+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
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+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
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+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
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+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
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+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
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+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
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+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
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+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
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+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
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+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
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+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
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+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
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+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
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+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
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+#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
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+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
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+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
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+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
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+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
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+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
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+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
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+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
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+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
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+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
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+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
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+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
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+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
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+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
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+
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+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
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+
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+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
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+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
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+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
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+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
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+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
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+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
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+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
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+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
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+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
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+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
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+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
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+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
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+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
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+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
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+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
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+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
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+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
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+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
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+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
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+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
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+#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
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+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
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+#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
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+#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
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+
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+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
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+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
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+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
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+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
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+
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+/******************** Bit definition for USB_OTG_HCDMA register ********************/
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+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
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+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
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+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
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+
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+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
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+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
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+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
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+
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+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
|
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+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
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+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
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+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
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+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
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+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
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+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
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+
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+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
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|
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
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+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
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+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
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+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
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+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
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+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
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|
|
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
|
|
|
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
|
|
|
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
|
|
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+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
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|
|
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
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|
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+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
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|
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+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
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|
|
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
|
|
|
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
|
|
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+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
|
|
|
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
|
|
|
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
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|
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+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
|
|
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+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
|
|
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+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
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|
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
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+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
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+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
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+#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
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|
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+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
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+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
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|
|
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
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|
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+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
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|
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+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
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+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
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|
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
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+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
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+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
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+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
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+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
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+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
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|
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
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|
|
+
|
|
|
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
|
|
|
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
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|
|
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
|
|
|
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
|
|
|
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
|
|
|
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
|
|
|
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
|
|
|
+#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
|
|
|
+#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
|
|
|
+#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
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|
|
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
|
|
|
+#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
|
|
|
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
|
|
|
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
|
|
|
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
|
|
|
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
|
|
|
+#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
|
|
|
+#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
|
|
|
+#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
|
|
|
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
|
|
|
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
|
|
|
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
|
|
|
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
|
|
|
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
|
|
|
+#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
|
|
|
+#define USB_OTG_DOEPINT_NAK_Pos (13U)
|
|
|
+#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
|
|
|
+#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
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|
|
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
|
|
|
+#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
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|
|
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
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|
|
+#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
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|
|
+#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
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|
|
+#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
|
|
|
+
|
|
|
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
|
|
|
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
|
|
|
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
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+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
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|
|
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
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+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
|
|
|
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
|
|
|
+
|
|
|
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
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|
|
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
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|
|
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
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+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
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+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
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+
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|
|
+/******************** Bit definition for PCGCCTL register ********************/
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|
|
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
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+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
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+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
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|
|
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
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+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
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+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
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+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
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+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
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+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
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+
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|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* JPEG Encoder/Decoder */
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|
|
+/* */
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|
|
+/******************************************************************************/
|
|
|
+/******************** Bit definition for CONFR0 register ********************/
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|
|
+#define JPEG_CONFR0_START_Pos (0U)
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|
+#define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */
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+#define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */
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|
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+
|
|
|
+/******************** Bit definition for CONFR1 register *******************/
|
|
|
+#define JPEG_CONFR1_NF_Pos (0U)
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+#define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */
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|
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+#define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */
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+#define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */
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+#define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */
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+#define JPEG_CONFR1_RE_Pos (2U)
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|
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+#define JPEG_CONFR1_RE_Msk (0x1UL << JPEG_CONFR1_RE_Pos) /*!< 0x00000004 */
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|
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+#define JPEG_CONFR1_RE JPEG_CONFR1_RE_Msk /*!<Restart maker Enable */
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|
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+#define JPEG_CONFR1_DE_Pos (3U)
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|
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+#define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */
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|
|
+#define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */
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|
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+#define JPEG_CONFR1_COLORSPACE_Pos (4U)
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|
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+#define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */
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|
|
+#define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */
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|
|
+#define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */
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|
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+#define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */
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|
|
+#define JPEG_CONFR1_NS_Pos (6U)
|
|
|
+#define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */
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|
|
+#define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */
|
|
|
+#define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */
|
|
|
+#define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */
|
|
|
+#define JPEG_CONFR1_HDR_Pos (8U)
|
|
|
+#define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */
|
|
|
+#define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */
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|
|
+#define JPEG_CONFR1_YSIZE_Pos (16U)
|
|
|
+#define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */
|
|
|
+#define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */
|
|
|
+
|
|
|
+/******************** Bit definition for CONFR2 register *******************/
|
|
|
+#define JPEG_CONFR2_NMCU_Pos (0U)
|
|
|
+#define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */
|
|
|
+#define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */
|
|
|
+
|
|
|
+/******************** Bit definition for CONFR3 register *******************/
|
|
|
+#define JPEG_CONFR3_NRST_Pos (0U)
|
|
|
+#define JPEG_CONFR3_NRST_Msk (0xFFFFUL << JPEG_CONFR3_NRST_Pos) /*!< 0x0000FFFF */
|
|
|
+#define JPEG_CONFR3_NRST JPEG_CONFR3_NRST_Msk /*!<Number of MCU between two restart makers minus 1 */
|
|
|
+#define JPEG_CONFR3_XSIZE_Pos (16U)
|
|
|
+#define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */
|
|
|
+#define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */
|
|
|
+
|
|
|
+/******************** Bit definition for CONFR4 register *******************/
|
|
|
+#define JPEG_CONFR4_HD_Pos (0U)
|
|
|
+#define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */
|
|
|
+#define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
|
|
|
+#define JPEG_CONFR4_HA_Pos (1U)
|
|
|
+#define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */
|
|
|
+#define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
|
|
|
+#define JPEG_CONFR4_QT_Pos (2U)
|
|
|
+#define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */
|
|
|
+#define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */
|
|
|
+#define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */
|
|
|
+#define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */
|
|
|
+#define JPEG_CONFR4_NB_Pos (4U)
|
|
|
+#define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */
|
|
|
+#define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
|
|
|
+#define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */
|
|
|
+#define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */
|
|
|
+#define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */
|
|
|
+#define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */
|
|
|
+#define JPEG_CONFR4_VSF_Pos (8U)
|
|
|
+#define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */
|
|
|
+#define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */
|
|
|
+#define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */
|
|
|
+#define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */
|
|
|
+#define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */
|
|
|
+#define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */
|
|
|
+#define JPEG_CONFR4_HSF_Pos (12U)
|
|
|
+#define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */
|
|
|
+#define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */
|
|
|
+#define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */
|
|
|
+#define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */
|
|
|
+#define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */
|
|
|
+#define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */
|
|
|
+
|
|
|
+/******************** Bit definition for CONFR5 register *******************/
|
|
|
+#define JPEG_CONFR5_HD_Pos (0U)
|
|
|
+#define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */
|
|
|
+#define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
|
|
|
+#define JPEG_CONFR5_HA_Pos (1U)
|
|
|
+#define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */
|
|
|
+#define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
|
|
|
+#define JPEG_CONFR5_QT_Pos (2U)
|
|
|
+#define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */
|
|
|
+#define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */
|
|
|
+#define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */
|
|
|
+#define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */
|
|
|
+#define JPEG_CONFR5_NB_Pos (4U)
|
|
|
+#define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */
|
|
|
+#define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
|
|
|
+#define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */
|
|
|
+#define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */
|
|
|
+#define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */
|
|
|
+#define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */
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|
|
+#define JPEG_CONFR5_VSF_Pos (8U)
|
|
|
+#define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */
|
|
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+#define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */
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|
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+#define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */
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|
+#define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */
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|
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+#define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */
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|
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+#define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */
|
|
|
+#define JPEG_CONFR5_HSF_Pos (12U)
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|
+#define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */
|
|
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+#define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */
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|
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+#define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */
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|
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+#define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */
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+#define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */
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+#define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */
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|
|
+
|
|
|
+/******************** Bit definition for CONFR6 register *******************/
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+#define JPEG_CONFR6_HD_Pos (0U)
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+#define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */
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+#define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
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+#define JPEG_CONFR6_HA_Pos (1U)
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+#define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */
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+#define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
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+#define JPEG_CONFR6_QT_Pos (2U)
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|
+#define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */
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+#define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */
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+#define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */
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+#define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */
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+#define JPEG_CONFR6_NB_Pos (4U)
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+#define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */
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+#define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
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+#define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */
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+#define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */
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+#define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */
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+#define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */
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+#define JPEG_CONFR6_VSF_Pos (8U)
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+#define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */
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|
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+#define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */
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+#define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */
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+#define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */
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+#define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */
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+#define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */
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|
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+#define JPEG_CONFR6_HSF_Pos (12U)
|
|
|
+#define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */
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|
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+#define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */
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|
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+#define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */
|
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+#define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */
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+#define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */
|
|
|
+#define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */
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|
|
+
|
|
|
+/******************** Bit definition for CONFR7 register *******************/
|
|
|
+#define JPEG_CONFR7_HD_Pos (0U)
|
|
|
+#define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */
|
|
|
+#define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
|
|
|
+#define JPEG_CONFR7_HA_Pos (1U)
|
|
|
+#define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */
|
|
|
+#define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
|
|
|
+#define JPEG_CONFR7_QT_Pos (2U)
|
|
|
+#define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */
|
|
|
+#define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */
|
|
|
+#define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */
|
|
|
+#define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */
|
|
|
+#define JPEG_CONFR7_NB_Pos (4U)
|
|
|
+#define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */
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|
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+#define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
|
|
|
+#define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */
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+#define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */
|
|
|
+#define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */
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|
+#define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */
|
|
|
+#define JPEG_CONFR7_VSF_Pos (8U)
|
|
|
+#define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */
|
|
|
+#define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */
|
|
|
+#define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */
|
|
|
+#define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */
|
|
|
+#define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */
|
|
|
+#define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */
|
|
|
+#define JPEG_CONFR7_HSF_Pos (12U)
|
|
|
+#define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */
|
|
|
+#define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */
|
|
|
+#define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */
|
|
|
+#define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */
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+#define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */
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|
+#define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */
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|
|
+
|
|
|
+/******************** Bit definition for CR register *******************/
|
|
|
+#define JPEG_CR_JCEN_Pos (0U)
|
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|
+#define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */
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|
|
+#define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */
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|
|
+#define JPEG_CR_IFTIE_Pos (1U)
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|
|
+#define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */
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|
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+#define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */
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+#define JPEG_CR_IFNFIE_Pos (2U)
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+#define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */
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+#define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */
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+#define JPEG_CR_OFTIE_Pos (3U)
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+#define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */
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+#define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */
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+#define JPEG_CR_OFNEIE_Pos (4U)
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+#define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */
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+#define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */
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+#define JPEG_CR_EOCIE_Pos (5U)
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+#define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */
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|
+#define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */
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+#define JPEG_CR_HPDIE_Pos (6U)
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|
+#define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */
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|
|
+#define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */
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|
|
+#define JPEG_CR_IDMAEN_Pos (11U)
|
|
|
+#define JPEG_CR_IDMAEN_Msk (0x1UL << JPEG_CR_IDMAEN_Pos) /*!< 0x00000800 */
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|
|
+#define JPEG_CR_IDMAEN JPEG_CR_IDMAEN_Msk /*!<Enable the DMA request generation for the input FIFO */
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+#define JPEG_CR_ODMAEN_Pos (12U)
|
|
|
+#define JPEG_CR_ODMAEN_Msk (0x1UL << JPEG_CR_ODMAEN_Pos) /*!< 0x00001000 */
|
|
|
+#define JPEG_CR_ODMAEN JPEG_CR_ODMAEN_Msk /*!<Enable the DMA request generation for the output FIFO */
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|
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+#define JPEG_CR_IFF_Pos (13U)
|
|
|
+#define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos) /*!< 0x00002000 */
|
|
|
+#define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */
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|
|
+#define JPEG_CR_OFF_Pos (14U)
|
|
|
+#define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos) /*!< 0x00004000 */
|
|
|
+#define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */
|
|
|
+
|
|
|
+/******************** Bit definition for SR register *******************/
|
|
|
+#define JPEG_SR_IFTF_Pos (1U)
|
|
|
+#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
|
|
+#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
|
|
+#define JPEG_SR_IFNFF_Pos (2U)
|
|
|
+#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
|
|
+#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
|
|
+#define JPEG_SR_OFTF_Pos (3U)
|
|
|
+#define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */
|
|
|
+#define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */
|
|
|
+#define JPEG_SR_OFNEF_Pos (4U)
|
|
|
+#define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos) /*!< 0x00000001 */
|
|
|
+#define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */
|
|
|
+#define JPEG_SR_EOCF_Pos (5U)
|
|
|
+#define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos) /*!< 0x00000002 */
|
|
|
+#define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
|
|
|
+#define JPEG_SR_HPDF_Pos (6U)
|
|
|
+#define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos) /*!< 0x00000004 */
|
|
|
+#define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
|
|
|
+#define JPEG_SR_COF_Pos (7U)
|
|
|
+#define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos) /*!< 0x00000008 */
|
|
|
+#define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */
|
|
|
+
|
|
|
+/******************** Bit definition for CFR register *******************/
|
|
|
+#define JPEG_CFR_CEOCF_Pos (5U)
|
|
|
+#define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) /*!< 0x00000020 */
|
|
|
+#define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */
|
|
|
+#define JPEG_CFR_CHPDF_Pos (6U)
|
|
|
+#define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) /*!< 0x00000040 */
|
|
|
+#define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */
|
|
|
+
|
|
|
+/******************** Bit definition for DIR register ********************/
|
|
|
+#define JPEG_DIR_DATAIN_Pos (0U)
|
|
|
+#define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */
|
|
|
+
|
|
|
+/******************** Bit definition for DOR register ********************/
|
|
|
+#define JPEG_DOR_DATAOUT_Pos (0U)
|
|
|
+#define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* MDIOS */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************** Bit definition for MDIOS_CR register *******************/
|
|
|
+#define MDIOS_CR_EN_Pos (0U)
|
|
|
+#define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
|
|
|
+#define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!<Peripheral enable */
|
|
|
+#define MDIOS_CR_WRIE_Pos (1U)
|
|
|
+#define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
|
|
|
+#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!<Register write interrupt enable */
|
|
|
+#define MDIOS_CR_RDIE_Pos (2U)
|
|
|
+#define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
|
|
|
+#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!<Register Read Interrupt Enable */
|
|
|
+#define MDIOS_CR_EIE_Pos (3U)
|
|
|
+#define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
|
|
|
+#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!<Error interrupt enable */
|
|
|
+#define MDIOS_CR_DPC_Pos (7U)
|
|
|
+#define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
|
|
|
+#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!<Disable Preamble Check */
|
|
|
+#define MDIOS_CR_PORT_ADDRESS_Pos (8U)
|
|
|
+#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
|
|
|
+#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!<PORT_ADDRESS[4:0] bits */
|
|
|
+#define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
|
|
|
+#define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
|
|
|
+#define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
|
|
|
+#define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
|
|
|
+#define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
|
|
|
+
|
|
|
+/******************** Bit definition for MDIOS_WRFR register *******************/
|
|
|
+#define MDIOS_WRFR_WRF_Pos (0U)
|
|
|
+#define MDIOS_WRFR_WRF_Msk (0xFFFFFFFFUL << MDIOS_WRFR_WRF_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define MDIOS_WRFR_WRF MDIOS_WRFR_WRF_Msk /*!<WRF[31:0] bits (Write flags for MDIO register 0 to 31) */
|
|
|
+
|
|
|
+/******************** Bit definition for MDIOS_CWRFR register *******************/
|
|
|
+#define MDIOS_CWRFR_CWRF_Pos (0U)
|
|
|
+#define MDIOS_CWRFR_CWRF_Msk (0xFFFFFFFFUL << MDIOS_CWRFR_CWRF_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define MDIOS_CWRFR_CWRF MDIOS_CWRFR_CWRF_Msk /*!<CWRF[31:0] bits (Clear the write flag for MDIO register 0 to 31) */
|
|
|
+
|
|
|
+/******************** Bit definition for MDIOS_RDFR register *******************/
|
|
|
+#define MDIOS_RDFR_RDF_Pos (0U)
|
|
|
+#define MDIOS_RDFR_RDF_Msk (0xFFFFFFFFUL << MDIOS_RDFR_RDF_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define MDIOS_RDFR_RDF MDIOS_RDFR_RDF_Msk /*!<RDF[31:0] bits (Read flags for MDIO registers 0 to 31) */
|
|
|
+
|
|
|
+/******************** Bit definition for MDIOS_CRDFR register *******************/
|
|
|
+#define MDIOS_CRDFR_CRDF_Pos (0U)
|
|
|
+#define MDIOS_CRDFR_CRDF_Msk (0xFFFFFFFFUL << MDIOS_CRDFR_CRDF_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define MDIOS_CRDFR_CRDF MDIOS_CRDFR_CRDF_Msk /*!<CRDF[31:0] bits (Clear the read flag for MDIO registers 0 to 31) */
|
|
|
+
|
|
|
+/******************** Bit definition for MDIOS_SR register *******************/
|
|
|
+#define MDIOS_SR_PERF_Pos (0U)
|
|
|
+#define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
|
|
|
+#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< Preamble error flag */
|
|
|
+#define MDIOS_SR_SERF_Pos (1U)
|
|
|
+#define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
|
|
|
+#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< Start error flag */
|
|
|
+#define MDIOS_SR_TERF_Pos (2U)
|
|
|
+#define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
|
|
|
+#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< Turnaround error flag */
|
|
|
+
|
|
|
+/******************** Bit definition for MDIOS_CLRFR register *******************/
|
|
|
+#define MDIOS_CLRFR_CPERF_Pos (0U)
|
|
|
+#define MDIOS_CLRFR_CPERF_Msk (0x1UL << MDIOS_CLRFR_CPERF_Pos) /*!< 0x00000001 */
|
|
|
+#define MDIOS_CLRFR_CPERF MDIOS_CLRFR_CPERF_Msk /*!< Clear the preamble error flag */
|
|
|
+#define MDIOS_CLRFR_CSERF_Pos (1U)
|
|
|
+#define MDIOS_CLRFR_CSERF_Msk (0x1UL << MDIOS_CLRFR_CSERF_Pos) /*!< 0x00000002 */
|
|
|
+#define MDIOS_CLRFR_CSERF MDIOS_CLRFR_CSERF_Msk /*!< Clear the start error flag */
|
|
|
+#define MDIOS_CLRFR_CTERF_Pos (2U)
|
|
|
+#define MDIOS_CLRFR_CTERF_Msk (0x1UL << MDIOS_CLRFR_CTERF_Pos) /*!< 0x00000004 */
|
|
|
+#define MDIOS_CLRFR_CTERF MDIOS_CLRFR_CTERF_Msk /*!< Clear the turnaround error flag */
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|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Display Serial Interface (DSI) */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************* Bit definition for DSI_VR register *****************/
|
|
|
+#define DSI_VR_Pos (1U)
|
|
|
+#define DSI_VR_Msk (0x18999815UL << DSI_VR_Pos) /*!< 0x3133302A */
|
|
|
+#define DSI_VR DSI_VR_Msk /*!< DSI Host Version */
|
|
|
+
|
|
|
+/******************* Bit definition for DSI_CR register *****************/
|
|
|
+#define DSI_CR_EN_Pos (0U)
|
|
|
+#define DSI_CR_EN_Msk (0x1UL << DSI_CR_EN_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_CR_EN DSI_CR_EN_Msk /*!< DSI Host power up and reset */
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|
|
+
|
|
|
+/******************* Bit definition for DSI_CCR register ****************/
|
|
|
+#define DSI_CCR_TXECKDIV_Pos (0U)
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|
|
+#define DSI_CCR_TXECKDIV_Msk (0xFFUL << DSI_CCR_TXECKDIV_Pos) /*!< 0x000000FF */
|
|
|
+#define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk /*!< TX Escape Clock Division */
|
|
|
+#define DSI_CCR_TXECKDIV0_Pos (0U)
|
|
|
+#define DSI_CCR_TXECKDIV0_Msk (0x1UL << DSI_CCR_TXECKDIV0_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk
|
|
|
+#define DSI_CCR_TXECKDIV1_Pos (1U)
|
|
|
+#define DSI_CCR_TXECKDIV1_Msk (0x1UL << DSI_CCR_TXECKDIV1_Pos) /*!< 0x00000002 */
|
|
|
+#define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk
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|
|
+#define DSI_CCR_TXECKDIV2_Pos (2U)
|
|
|
+#define DSI_CCR_TXECKDIV2_Msk (0x1UL << DSI_CCR_TXECKDIV2_Pos) /*!< 0x00000004 */
|
|
|
+#define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk
|
|
|
+#define DSI_CCR_TXECKDIV3_Pos (3U)
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|
|
+#define DSI_CCR_TXECKDIV3_Msk (0x1UL << DSI_CCR_TXECKDIV3_Pos) /*!< 0x00000008 */
|
|
|
+#define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk
|
|
|
+#define DSI_CCR_TXECKDIV4_Pos (4U)
|
|
|
+#define DSI_CCR_TXECKDIV4_Msk (0x1UL << DSI_CCR_TXECKDIV4_Pos) /*!< 0x00000010 */
|
|
|
+#define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk
|
|
|
+#define DSI_CCR_TXECKDIV5_Pos (5U)
|
|
|
+#define DSI_CCR_TXECKDIV5_Msk (0x1UL << DSI_CCR_TXECKDIV5_Pos) /*!< 0x00000020 */
|
|
|
+#define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk
|
|
|
+#define DSI_CCR_TXECKDIV6_Pos (6U)
|
|
|
+#define DSI_CCR_TXECKDIV6_Msk (0x1UL << DSI_CCR_TXECKDIV6_Pos) /*!< 0x00000040 */
|
|
|
+#define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk
|
|
|
+#define DSI_CCR_TXECKDIV7_Pos (7U)
|
|
|
+#define DSI_CCR_TXECKDIV7_Msk (0x1UL << DSI_CCR_TXECKDIV7_Pos) /*!< 0x00000080 */
|
|
|
+#define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk
|
|
|
+
|
|
|
+#define DSI_CCR_TOCKDIV_Pos (8U)
|
|
|
+#define DSI_CCR_TOCKDIV_Msk (0xFFUL << DSI_CCR_TOCKDIV_Pos) /*!< 0x0000FF00 */
|
|
|
+#define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk /*!< Timeout Clock Division */
|
|
|
+#define DSI_CCR_TOCKDIV0_Pos (8U)
|
|
|
+#define DSI_CCR_TOCKDIV0_Msk (0x1UL << DSI_CCR_TOCKDIV0_Pos) /*!< 0x00000100 */
|
|
|
+#define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk
|
|
|
+#define DSI_CCR_TOCKDIV1_Pos (9U)
|
|
|
+#define DSI_CCR_TOCKDIV1_Msk (0x1UL << DSI_CCR_TOCKDIV1_Pos) /*!< 0x00000200 */
|
|
|
+#define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk
|
|
|
+#define DSI_CCR_TOCKDIV2_Pos (10U)
|
|
|
+#define DSI_CCR_TOCKDIV2_Msk (0x1UL << DSI_CCR_TOCKDIV2_Pos) /*!< 0x00000400 */
|
|
|
+#define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk
|
|
|
+#define DSI_CCR_TOCKDIV3_Pos (11U)
|
|
|
+#define DSI_CCR_TOCKDIV3_Msk (0x1UL << DSI_CCR_TOCKDIV3_Pos) /*!< 0x00000800 */
|
|
|
+#define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk
|
|
|
+#define DSI_CCR_TOCKDIV4_Pos (12U)
|
|
|
+#define DSI_CCR_TOCKDIV4_Msk (0x1UL << DSI_CCR_TOCKDIV4_Pos) /*!< 0x00001000 */
|
|
|
+#define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk
|
|
|
+#define DSI_CCR_TOCKDIV5_Pos (13U)
|
|
|
+#define DSI_CCR_TOCKDIV5_Msk (0x1UL << DSI_CCR_TOCKDIV5_Pos) /*!< 0x00002000 */
|
|
|
+#define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk
|
|
|
+#define DSI_CCR_TOCKDIV6_Pos (14U)
|
|
|
+#define DSI_CCR_TOCKDIV6_Msk (0x1UL << DSI_CCR_TOCKDIV6_Pos) /*!< 0x00004000 */
|
|
|
+#define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk
|
|
|
+#define DSI_CCR_TOCKDIV7_Pos (15U)
|
|
|
+#define DSI_CCR_TOCKDIV7_Msk (0x1UL << DSI_CCR_TOCKDIV7_Pos) /*!< 0x00008000 */
|
|
|
+#define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk
|
|
|
+
|
|
|
+/******************* Bit definition for DSI_LVCIDR register *************/
|
|
|
+#define DSI_LVCIDR_VCID_Pos (0U)
|
|
|
+#define DSI_LVCIDR_VCID_Msk (0x3UL << DSI_LVCIDR_VCID_Pos) /*!< 0x00000003 */
|
|
|
+#define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk /*!< Virtual Channel ID */
|
|
|
+#define DSI_LVCIDR_VCID0_Pos (0U)
|
|
|
+#define DSI_LVCIDR_VCID0_Msk (0x1UL << DSI_LVCIDR_VCID0_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk
|
|
|
+#define DSI_LVCIDR_VCID1_Pos (1U)
|
|
|
+#define DSI_LVCIDR_VCID1_Msk (0x1UL << DSI_LVCIDR_VCID1_Pos) /*!< 0x00000002 */
|
|
|
+#define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk
|
|
|
+
|
|
|
+/******************* Bit definition for DSI_LCOLCR register *************/
|
|
|
+#define DSI_LCOLCR_COLC_Pos (0U)
|
|
|
+#define DSI_LCOLCR_COLC_Msk (0xFUL << DSI_LCOLCR_COLC_Pos) /*!< 0x0000000F */
|
|
|
+#define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk /*!< Color Coding */
|
|
|
+#define DSI_LCOLCR_COLC0_Pos (0U)
|
|
|
+#define DSI_LCOLCR_COLC0_Msk (0x1UL << DSI_LCOLCR_COLC0_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk
|
|
|
+#define DSI_LCOLCR_COLC1_Pos (5U)
|
|
|
+#define DSI_LCOLCR_COLC1_Msk (0x1UL << DSI_LCOLCR_COLC1_Pos) /*!< 0x00000020 */
|
|
|
+#define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk
|
|
|
+#define DSI_LCOLCR_COLC2_Pos (6U)
|
|
|
+#define DSI_LCOLCR_COLC2_Msk (0x1UL << DSI_LCOLCR_COLC2_Pos) /*!< 0x00000040 */
|
|
|
+#define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk
|
|
|
+#define DSI_LCOLCR_COLC3_Pos (7U)
|
|
|
+#define DSI_LCOLCR_COLC3_Msk (0x1UL << DSI_LCOLCR_COLC3_Pos) /*!< 0x00000080 */
|
|
|
+#define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk
|
|
|
+
|
|
|
+#define DSI_LCOLCR_LPE_Pos (8U)
|
|
|
+#define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
|
|
|
+#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
|
|
|
+
|
|
|
+/******************* Bit definition for DSI_LPCR register ***************/
|
|
|
+#define DSI_LPCR_DEP_Pos (0U)
|
|
|
+#define DSI_LPCR_DEP_Msk (0x1UL << DSI_LPCR_DEP_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_LPCR_DEP DSI_LPCR_DEP_Msk /*!< Data Enable Polarity */
|
|
|
+#define DSI_LPCR_VSP_Pos (1U)
|
|
|
+#define DSI_LPCR_VSP_Msk (0x1UL << DSI_LPCR_VSP_Pos) /*!< 0x00000002 */
|
|
|
+#define DSI_LPCR_VSP DSI_LPCR_VSP_Msk /*!< VSYNC Polarity */
|
|
|
+#define DSI_LPCR_HSP_Pos (2U)
|
|
|
+#define DSI_LPCR_HSP_Msk (0x1UL << DSI_LPCR_HSP_Pos) /*!< 0x00000004 */
|
|
|
+#define DSI_LPCR_HSP DSI_LPCR_HSP_Msk /*!< HSYNC Polarity */
|
|
|
+
|
|
|
+/******************* Bit definition for DSI_LPMCR register **************/
|
|
|
+#define DSI_LPMCR_VLPSIZE_Pos (0U)
|
|
|
+#define DSI_LPMCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCR_VLPSIZE_Pos) /*!< 0x000000FF */
|
|
|
+#define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
|
|
|
+#define DSI_LPMCR_VLPSIZE0_Pos (0U)
|
|
|
+#define DSI_LPMCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCR_VLPSIZE0_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk
|
|
|
+#define DSI_LPMCR_VLPSIZE1_Pos (1U)
|
|
|
+#define DSI_LPMCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCR_VLPSIZE1_Pos) /*!< 0x00000002 */
|
|
|
+#define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk
|
|
|
+#define DSI_LPMCR_VLPSIZE2_Pos (2U)
|
|
|
+#define DSI_LPMCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCR_VLPSIZE2_Pos) /*!< 0x00000004 */
|
|
|
+#define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk
|
|
|
+#define DSI_LPMCR_VLPSIZE3_Pos (3U)
|
|
|
+#define DSI_LPMCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCR_VLPSIZE3_Pos) /*!< 0x00000008 */
|
|
|
+#define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk
|
|
|
+#define DSI_LPMCR_VLPSIZE4_Pos (4U)
|
|
|
+#define DSI_LPMCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCR_VLPSIZE4_Pos) /*!< 0x00000010 */
|
|
|
+#define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk
|
|
|
+#define DSI_LPMCR_VLPSIZE5_Pos (5U)
|
|
|
+#define DSI_LPMCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCR_VLPSIZE5_Pos) /*!< 0x00000020 */
|
|
|
+#define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk
|
|
|
+#define DSI_LPMCR_VLPSIZE6_Pos (6U)
|
|
|
+#define DSI_LPMCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCR_VLPSIZE6_Pos) /*!< 0x00000040 */
|
|
|
+#define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk
|
|
|
+#define DSI_LPMCR_VLPSIZE7_Pos (7U)
|
|
|
+#define DSI_LPMCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCR_VLPSIZE7_Pos) /*!< 0x00000080 */
|
|
|
+#define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk
|
|
|
+
|
|
|
+#define DSI_LPMCR_LPSIZE_Pos (16U)
|
|
|
+#define DSI_LPMCR_LPSIZE_Msk (0xFFUL << DSI_LPMCR_LPSIZE_Pos) /*!< 0x00FF0000 */
|
|
|
+#define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk /*!< Largest Packet Size */
|
|
|
+#define DSI_LPMCR_LPSIZE0_Pos (16U)
|
|
|
+#define DSI_LPMCR_LPSIZE0_Msk (0x1UL << DSI_LPMCR_LPSIZE0_Pos) /*!< 0x00010000 */
|
|
|
+#define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk
|
|
|
+#define DSI_LPMCR_LPSIZE1_Pos (17U)
|
|
|
+#define DSI_LPMCR_LPSIZE1_Msk (0x1UL << DSI_LPMCR_LPSIZE1_Pos) /*!< 0x00020000 */
|
|
|
+#define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk
|
|
|
+#define DSI_LPMCR_LPSIZE2_Pos (18U)
|
|
|
+#define DSI_LPMCR_LPSIZE2_Msk (0x1UL << DSI_LPMCR_LPSIZE2_Pos) /*!< 0x00040000 */
|
|
|
+#define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk
|
|
|
+#define DSI_LPMCR_LPSIZE3_Pos (19U)
|
|
|
+#define DSI_LPMCR_LPSIZE3_Msk (0x1UL << DSI_LPMCR_LPSIZE3_Pos) /*!< 0x00080000 */
|
|
|
+#define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk
|
|
|
+#define DSI_LPMCR_LPSIZE4_Pos (20U)
|
|
|
+#define DSI_LPMCR_LPSIZE4_Msk (0x1UL << DSI_LPMCR_LPSIZE4_Pos) /*!< 0x00100000 */
|
|
|
+#define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk
|
|
|
+#define DSI_LPMCR_LPSIZE5_Pos (21U)
|
|
|
+#define DSI_LPMCR_LPSIZE5_Msk (0x1UL << DSI_LPMCR_LPSIZE5_Pos) /*!< 0x00200000 */
|
|
|
+#define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk
|
|
|
+#define DSI_LPMCR_LPSIZE6_Pos (22U)
|
|
|
+#define DSI_LPMCR_LPSIZE6_Msk (0x1UL << DSI_LPMCR_LPSIZE6_Pos) /*!< 0x00400000 */
|
|
|
+#define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk
|
|
|
+#define DSI_LPMCR_LPSIZE7_Pos (23U)
|
|
|
+#define DSI_LPMCR_LPSIZE7_Msk (0x1UL << DSI_LPMCR_LPSIZE7_Pos) /*!< 0x00800000 */
|
|
|
+#define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk
|
|
|
+
|
|
|
+/******************* Bit definition for DSI_PCR register ****************/
|
|
|
+#define DSI_PCR_ETTXE_Pos (0U)
|
|
|
+#define DSI_PCR_ETTXE_Msk (0x1UL << DSI_PCR_ETTXE_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk /*!< EoTp Transmission Enable */
|
|
|
+#define DSI_PCR_ETRXE_Pos (1U)
|
|
|
+#define DSI_PCR_ETRXE_Msk (0x1UL << DSI_PCR_ETRXE_Pos) /*!< 0x00000002 */
|
|
|
+#define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk /*!< EoTp Reception Enable */
|
|
|
+#define DSI_PCR_BTAE_Pos (2U)
|
|
|
+#define DSI_PCR_BTAE_Msk (0x1UL << DSI_PCR_BTAE_Pos) /*!< 0x00000004 */
|
|
|
+#define DSI_PCR_BTAE DSI_PCR_BTAE_Msk /*!< Bus Turn Around Enable */
|
|
|
+#define DSI_PCR_ECCRXE_Pos (3U)
|
|
|
+#define DSI_PCR_ECCRXE_Msk (0x1UL << DSI_PCR_ECCRXE_Pos) /*!< 0x00000008 */
|
|
|
+#define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk /*!< ECC Reception Enable */
|
|
|
+#define DSI_PCR_CRCRXE_Pos (4U)
|
|
|
+#define DSI_PCR_CRCRXE_Msk (0x1UL << DSI_PCR_CRCRXE_Pos) /*!< 0x00000010 */
|
|
|
+#define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk /*!< CRC Reception Enable */
|
|
|
+
|
|
|
+/******************* Bit definition for DSI_GVCIDR register *************/
|
|
|
+#define DSI_GVCIDR_VCID_Pos (0U)
|
|
|
+#define DSI_GVCIDR_VCID_Msk (0x3UL << DSI_GVCIDR_VCID_Pos) /*!< 0x00000003 */
|
|
|
+#define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk /*!< Virtual Channel ID */
|
|
|
+#define DSI_GVCIDR_VCID0_Pos (0U)
|
|
|
+#define DSI_GVCIDR_VCID0_Msk (0x1UL << DSI_GVCIDR_VCID0_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk
|
|
|
+#define DSI_GVCIDR_VCID1_Pos (1U)
|
|
|
+#define DSI_GVCIDR_VCID1_Msk (0x1UL << DSI_GVCIDR_VCID1_Pos) /*!< 0x00000002 */
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+#define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk
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+
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+/******************* Bit definition for DSI_MCR register ****************/
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+#define DSI_MCR_CMDM_Pos (0U)
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+#define DSI_MCR_CMDM_Msk (0x1UL << DSI_MCR_CMDM_Pos) /*!< 0x00000001 */
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+#define DSI_MCR_CMDM DSI_MCR_CMDM_Msk /*!< Command Mode */
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+
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+/******************* Bit definition for DSI_VMCR register ***************/
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+#define DSI_VMCR_VMT_Pos (0U)
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+#define DSI_VMCR_VMT_Msk (0x3UL << DSI_VMCR_VMT_Pos) /*!< 0x00000003 */
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+#define DSI_VMCR_VMT DSI_VMCR_VMT_Msk /*!< Video Mode Type */
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+#define DSI_VMCR_VMT0_Pos (0U)
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+#define DSI_VMCR_VMT0_Msk (0x1UL << DSI_VMCR_VMT0_Pos) /*!< 0x00000001 */
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+#define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk
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+#define DSI_VMCR_VMT1_Pos (1U)
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+#define DSI_VMCR_VMT1_Msk (0x1UL << DSI_VMCR_VMT1_Pos) /*!< 0x00000002 */
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+#define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk
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+
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+#define DSI_VMCR_LPVSAE_Pos (8U)
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+#define DSI_VMCR_LPVSAE_Msk (0x1UL << DSI_VMCR_LPVSAE_Pos) /*!< 0x00000100 */
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+#define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk /*!< Low-Power Vertical Sync Active Enable */
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+#define DSI_VMCR_LPVBPE_Pos (9U)
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+#define DSI_VMCR_LPVBPE_Msk (0x1UL << DSI_VMCR_LPVBPE_Pos) /*!< 0x00000200 */
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+#define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk /*!< Low-power Vertical Back-Porch Enable */
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+#define DSI_VMCR_LPVFPE_Pos (10U)
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+#define DSI_VMCR_LPVFPE_Msk (0x1UL << DSI_VMCR_LPVFPE_Pos) /*!< 0x00000400 */
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+#define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
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+#define DSI_VMCR_LPVAE_Pos (11U)
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+#define DSI_VMCR_LPVAE_Msk (0x1UL << DSI_VMCR_LPVAE_Pos) /*!< 0x00000800 */
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+#define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk /*!< Low-Power Vertical Active Enable */
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+#define DSI_VMCR_LPHBPE_Pos (12U)
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+#define DSI_VMCR_LPHBPE_Msk (0x1UL << DSI_VMCR_LPHBPE_Pos) /*!< 0x00001000 */
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+#define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk /*!< Low-Power Horizontal Back-Porch Enable */
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+#define DSI_VMCR_LPHFPE_Pos (13U)
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+#define DSI_VMCR_LPHFPE_Msk (0x1UL << DSI_VMCR_LPHFPE_Pos) /*!< 0x00002000 */
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+#define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk /*!< Low-Power Horizontal Front-Porch Enable */
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+#define DSI_VMCR_FBTAAE_Pos (14U)
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+#define DSI_VMCR_FBTAAE_Msk (0x1UL << DSI_VMCR_FBTAAE_Pos) /*!< 0x00004000 */
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+#define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk /*!< Frame Bus-Turn-Around Acknowledge Enable */
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+#define DSI_VMCR_LPCE_Pos (15U)
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+#define DSI_VMCR_LPCE_Msk (0x1UL << DSI_VMCR_LPCE_Pos) /*!< 0x00008000 */
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+#define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk /*!< Low-Power Command Enable */
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+#define DSI_VMCR_PGE_Pos (16U)
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+#define DSI_VMCR_PGE_Msk (0x1UL << DSI_VMCR_PGE_Pos) /*!< 0x00010000 */
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+#define DSI_VMCR_PGE DSI_VMCR_PGE_Msk /*!< Pattern Generator Enable */
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+#define DSI_VMCR_PGM_Pos (20U)
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+#define DSI_VMCR_PGM_Msk (0x1UL << DSI_VMCR_PGM_Pos) /*!< 0x00100000 */
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+#define DSI_VMCR_PGM DSI_VMCR_PGM_Msk /*!< Pattern Generator Mode */
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+#define DSI_VMCR_PGO_Pos (24U)
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+#define DSI_VMCR_PGO_Msk (0x1UL << DSI_VMCR_PGO_Pos) /*!< 0x01000000 */
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+#define DSI_VMCR_PGO DSI_VMCR_PGO_Msk /*!< Pattern Generator Orientation */
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+
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+/******************* Bit definition for DSI_VPCR register ***************/
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+#define DSI_VPCR_VPSIZE_Pos (0U)
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+#define DSI_VPCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCR_VPSIZE_Pos) /*!< 0x00003FFF */
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+#define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk /*!< Video Packet Size */
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+#define DSI_VPCR_VPSIZE0_Pos (0U)
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+#define DSI_VPCR_VPSIZE0_Msk (0x1UL << DSI_VPCR_VPSIZE0_Pos) /*!< 0x00000001 */
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+#define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk
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+#define DSI_VPCR_VPSIZE1_Pos (1U)
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+#define DSI_VPCR_VPSIZE1_Msk (0x1UL << DSI_VPCR_VPSIZE1_Pos) /*!< 0x00000002 */
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+#define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk
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+#define DSI_VPCR_VPSIZE2_Pos (2U)
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+#define DSI_VPCR_VPSIZE2_Msk (0x1UL << DSI_VPCR_VPSIZE2_Pos) /*!< 0x00000004 */
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+#define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk
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+#define DSI_VPCR_VPSIZE3_Pos (3U)
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+#define DSI_VPCR_VPSIZE3_Msk (0x1UL << DSI_VPCR_VPSIZE3_Pos) /*!< 0x00000008 */
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+#define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk
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+#define DSI_VPCR_VPSIZE4_Pos (4U)
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+#define DSI_VPCR_VPSIZE4_Msk (0x1UL << DSI_VPCR_VPSIZE4_Pos) /*!< 0x00000010 */
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+#define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk
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+#define DSI_VPCR_VPSIZE5_Pos (5U)
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+#define DSI_VPCR_VPSIZE5_Msk (0x1UL << DSI_VPCR_VPSIZE5_Pos) /*!< 0x00000020 */
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+#define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk
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+#define DSI_VPCR_VPSIZE6_Pos (6U)
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+#define DSI_VPCR_VPSIZE6_Msk (0x1UL << DSI_VPCR_VPSIZE6_Pos) /*!< 0x00000040 */
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+#define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk
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+#define DSI_VPCR_VPSIZE7_Pos (7U)
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+#define DSI_VPCR_VPSIZE7_Msk (0x1UL << DSI_VPCR_VPSIZE7_Pos) /*!< 0x00000080 */
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+#define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk
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+#define DSI_VPCR_VPSIZE8_Pos (8U)
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+#define DSI_VPCR_VPSIZE8_Msk (0x1UL << DSI_VPCR_VPSIZE8_Pos) /*!< 0x00000100 */
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+#define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk
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+#define DSI_VPCR_VPSIZE9_Pos (9U)
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+#define DSI_VPCR_VPSIZE9_Msk (0x1UL << DSI_VPCR_VPSIZE9_Pos) /*!< 0x00000200 */
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+#define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk
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+#define DSI_VPCR_VPSIZE10_Pos (10U)
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+#define DSI_VPCR_VPSIZE10_Msk (0x1UL << DSI_VPCR_VPSIZE10_Pos) /*!< 0x00000400 */
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+#define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk
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+#define DSI_VPCR_VPSIZE11_Pos (11U)
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+#define DSI_VPCR_VPSIZE11_Msk (0x1UL << DSI_VPCR_VPSIZE11_Pos) /*!< 0x00000800 */
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+#define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk
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+#define DSI_VPCR_VPSIZE12_Pos (12U)
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+#define DSI_VPCR_VPSIZE12_Msk (0x1UL << DSI_VPCR_VPSIZE12_Pos) /*!< 0x00001000 */
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+#define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk
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+#define DSI_VPCR_VPSIZE13_Pos (13U)
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+#define DSI_VPCR_VPSIZE13_Msk (0x1UL << DSI_VPCR_VPSIZE13_Pos) /*!< 0x00002000 */
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+#define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk
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+
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+/******************* Bit definition for DSI_VCCR register ***************/
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+#define DSI_VCCR_NUMC_Pos (0U)
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+#define DSI_VCCR_NUMC_Msk (0x1FFFUL << DSI_VCCR_NUMC_Pos) /*!< 0x00001FFF */
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+#define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk /*!< Number of Chunks */
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+#define DSI_VCCR_NUMC0_Pos (0U)
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+#define DSI_VCCR_NUMC0_Msk (0x1UL << DSI_VCCR_NUMC0_Pos) /*!< 0x00000001 */
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+#define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk
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+#define DSI_VCCR_NUMC1_Pos (1U)
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+#define DSI_VCCR_NUMC1_Msk (0x1UL << DSI_VCCR_NUMC1_Pos) /*!< 0x00000002 */
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+#define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk
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+#define DSI_VCCR_NUMC2_Pos (2U)
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+#define DSI_VCCR_NUMC2_Msk (0x1UL << DSI_VCCR_NUMC2_Pos) /*!< 0x00000004 */
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+#define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk
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+#define DSI_VCCR_NUMC3_Pos (3U)
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+#define DSI_VCCR_NUMC3_Msk (0x1UL << DSI_VCCR_NUMC3_Pos) /*!< 0x00000008 */
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+#define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk
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+#define DSI_VCCR_NUMC4_Pos (4U)
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+#define DSI_VCCR_NUMC4_Msk (0x1UL << DSI_VCCR_NUMC4_Pos) /*!< 0x00000010 */
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+#define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk
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+#define DSI_VCCR_NUMC5_Pos (5U)
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+#define DSI_VCCR_NUMC5_Msk (0x1UL << DSI_VCCR_NUMC5_Pos) /*!< 0x00000020 */
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+#define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk
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+#define DSI_VCCR_NUMC6_Pos (6U)
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+#define DSI_VCCR_NUMC6_Msk (0x1UL << DSI_VCCR_NUMC6_Pos) /*!< 0x00000040 */
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+#define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk
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+#define DSI_VCCR_NUMC7_Pos (7U)
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+#define DSI_VCCR_NUMC7_Msk (0x1UL << DSI_VCCR_NUMC7_Pos) /*!< 0x00000080 */
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+#define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk
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+#define DSI_VCCR_NUMC8_Pos (8U)
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+#define DSI_VCCR_NUMC8_Msk (0x1UL << DSI_VCCR_NUMC8_Pos) /*!< 0x00000100 */
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+#define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk
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+#define DSI_VCCR_NUMC9_Pos (9U)
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+#define DSI_VCCR_NUMC9_Msk (0x1UL << DSI_VCCR_NUMC9_Pos) /*!< 0x00000200 */
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+#define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk
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+#define DSI_VCCR_NUMC10_Pos (10U)
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+#define DSI_VCCR_NUMC10_Msk (0x1UL << DSI_VCCR_NUMC10_Pos) /*!< 0x00000400 */
|
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+#define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk
|
|
|
+#define DSI_VCCR_NUMC11_Pos (11U)
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+#define DSI_VCCR_NUMC11_Msk (0x1UL << DSI_VCCR_NUMC11_Pos) /*!< 0x00000800 */
|
|
|
+#define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk
|
|
|
+#define DSI_VCCR_NUMC12_Pos (12U)
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+#define DSI_VCCR_NUMC12_Msk (0x1UL << DSI_VCCR_NUMC12_Pos) /*!< 0x00001000 */
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|
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+#define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk
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+
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|
|
+/******************* Bit definition for DSI_VNPCR register **************/
|
|
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+#define DSI_VNPCR_NPSIZE_Pos (0U)
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+#define DSI_VNPCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos) /*!< 0x00001FFF */
|
|
|
+#define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk /*!< Null Packet Size */
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+#define DSI_VNPCR_NPSIZE0_Pos (0U)
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+#define DSI_VNPCR_NPSIZE0_Msk (0x1UL << DSI_VNPCR_NPSIZE0_Pos) /*!< 0x00000001 */
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+#define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk
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|
+#define DSI_VNPCR_NPSIZE1_Pos (1U)
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+#define DSI_VNPCR_NPSIZE1_Msk (0x1UL << DSI_VNPCR_NPSIZE1_Pos) /*!< 0x00000002 */
|
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+#define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk
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+#define DSI_VNPCR_NPSIZE2_Pos (2U)
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+#define DSI_VNPCR_NPSIZE2_Msk (0x1UL << DSI_VNPCR_NPSIZE2_Pos) /*!< 0x00000004 */
|
|
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+#define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk
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+#define DSI_VNPCR_NPSIZE3_Pos (3U)
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+#define DSI_VNPCR_NPSIZE3_Msk (0x1UL << DSI_VNPCR_NPSIZE3_Pos) /*!< 0x00000008 */
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|
+#define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk
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|
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+#define DSI_VNPCR_NPSIZE4_Pos (4U)
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+#define DSI_VNPCR_NPSIZE4_Msk (0x1UL << DSI_VNPCR_NPSIZE4_Pos) /*!< 0x00000010 */
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|
+#define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk
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+#define DSI_VNPCR_NPSIZE5_Pos (5U)
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+#define DSI_VNPCR_NPSIZE5_Msk (0x1UL << DSI_VNPCR_NPSIZE5_Pos) /*!< 0x00000020 */
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+#define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk
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+#define DSI_VNPCR_NPSIZE6_Pos (6U)
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+#define DSI_VNPCR_NPSIZE6_Msk (0x1UL << DSI_VNPCR_NPSIZE6_Pos) /*!< 0x00000040 */
|
|
|
+#define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk
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+#define DSI_VNPCR_NPSIZE7_Pos (7U)
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+#define DSI_VNPCR_NPSIZE7_Msk (0x1UL << DSI_VNPCR_NPSIZE7_Pos) /*!< 0x00000080 */
|
|
|
+#define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk
|
|
|
+#define DSI_VNPCR_NPSIZE8_Pos (8U)
|
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+#define DSI_VNPCR_NPSIZE8_Msk (0x1UL << DSI_VNPCR_NPSIZE8_Pos) /*!< 0x00000100 */
|
|
|
+#define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk
|
|
|
+#define DSI_VNPCR_NPSIZE9_Pos (9U)
|
|
|
+#define DSI_VNPCR_NPSIZE9_Msk (0x1UL << DSI_VNPCR_NPSIZE9_Pos) /*!< 0x00000200 */
|
|
|
+#define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk
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|
|
+#define DSI_VNPCR_NPSIZE10_Pos (10U)
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+#define DSI_VNPCR_NPSIZE10_Msk (0x1UL << DSI_VNPCR_NPSIZE10_Pos) /*!< 0x00000400 */
|
|
|
+#define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk
|
|
|
+#define DSI_VNPCR_NPSIZE11_Pos (11U)
|
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|
+#define DSI_VNPCR_NPSIZE11_Msk (0x1UL << DSI_VNPCR_NPSIZE11_Pos) /*!< 0x00000800 */
|
|
|
+#define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk
|
|
|
+#define DSI_VNPCR_NPSIZE12_Pos (12U)
|
|
|
+#define DSI_VNPCR_NPSIZE12_Msk (0x1UL << DSI_VNPCR_NPSIZE12_Pos) /*!< 0x00001000 */
|
|
|
+#define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk
|
|
|
+
|
|
|
+/******************* Bit definition for DSI_VHSACR register *************/
|
|
|
+#define DSI_VHSACR_HSA_Pos (0U)
|
|
|
+#define DSI_VHSACR_HSA_Msk (0xFFFUL << DSI_VHSACR_HSA_Pos) /*!< 0x00000FFF */
|
|
|
+#define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk /*!< Horizontal Synchronism Active duration */
|
|
|
+#define DSI_VHSACR_HSA0_Pos (0U)
|
|
|
+#define DSI_VHSACR_HSA0_Msk (0x1UL << DSI_VHSACR_HSA0_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk
|
|
|
+#define DSI_VHSACR_HSA1_Pos (1U)
|
|
|
+#define DSI_VHSACR_HSA1_Msk (0x1UL << DSI_VHSACR_HSA1_Pos) /*!< 0x00000002 */
|
|
|
+#define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk
|
|
|
+#define DSI_VHSACR_HSA2_Pos (2U)
|
|
|
+#define DSI_VHSACR_HSA2_Msk (0x1UL << DSI_VHSACR_HSA2_Pos) /*!< 0x00000004 */
|
|
|
+#define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk
|
|
|
+#define DSI_VHSACR_HSA3_Pos (3U)
|
|
|
+#define DSI_VHSACR_HSA3_Msk (0x1UL << DSI_VHSACR_HSA3_Pos) /*!< 0x00000008 */
|
|
|
+#define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk
|
|
|
+#define DSI_VHSACR_HSA4_Pos (4U)
|
|
|
+#define DSI_VHSACR_HSA4_Msk (0x1UL << DSI_VHSACR_HSA4_Pos) /*!< 0x00000010 */
|
|
|
+#define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk
|
|
|
+#define DSI_VHSACR_HSA5_Pos (5U)
|
|
|
+#define DSI_VHSACR_HSA5_Msk (0x1UL << DSI_VHSACR_HSA5_Pos) /*!< 0x00000020 */
|
|
|
+#define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk
|
|
|
+#define DSI_VHSACR_HSA6_Pos (6U)
|
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+#define DSI_VHSACR_HSA6_Msk (0x1UL << DSI_VHSACR_HSA6_Pos) /*!< 0x00000040 */
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+#define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk
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+#define DSI_VHSACR_HSA7_Pos (7U)
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+#define DSI_VHSACR_HSA7_Msk (0x1UL << DSI_VHSACR_HSA7_Pos) /*!< 0x00000080 */
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+#define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk
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+#define DSI_VHSACR_HSA8_Pos (8U)
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+#define DSI_VHSACR_HSA8_Msk (0x1UL << DSI_VHSACR_HSA8_Pos) /*!< 0x00000100 */
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+#define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk
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+#define DSI_VHSACR_HSA9_Pos (9U)
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+#define DSI_VHSACR_HSA9_Msk (0x1UL << DSI_VHSACR_HSA9_Pos) /*!< 0x00000200 */
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+#define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk
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+#define DSI_VHSACR_HSA10_Pos (10U)
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+#define DSI_VHSACR_HSA10_Msk (0x1UL << DSI_VHSACR_HSA10_Pos) /*!< 0x00000400 */
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+#define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk
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+#define DSI_VHSACR_HSA11_Pos (11U)
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+#define DSI_VHSACR_HSA11_Msk (0x1UL << DSI_VHSACR_HSA11_Pos) /*!< 0x00000800 */
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+#define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk
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+
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+/******************* Bit definition for DSI_VHBPCR register *************/
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+#define DSI_VHBPCR_HBP_Pos (0U)
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+#define DSI_VHBPCR_HBP_Msk (0xFFFUL << DSI_VHBPCR_HBP_Pos) /*!< 0x00000FFF */
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+#define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk /*!< Horizontal Back-Porch duration */
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+#define DSI_VHBPCR_HBP0_Pos (0U)
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+#define DSI_VHBPCR_HBP0_Msk (0x1UL << DSI_VHBPCR_HBP0_Pos) /*!< 0x00000001 */
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+#define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk
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+#define DSI_VHBPCR_HBP1_Pos (1U)
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+#define DSI_VHBPCR_HBP1_Msk (0x1UL << DSI_VHBPCR_HBP1_Pos) /*!< 0x00000002 */
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+#define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk
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+#define DSI_VHBPCR_HBP2_Pos (2U)
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+#define DSI_VHBPCR_HBP2_Msk (0x1UL << DSI_VHBPCR_HBP2_Pos) /*!< 0x00000004 */
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+#define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk
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+#define DSI_VHBPCR_HBP3_Pos (3U)
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+#define DSI_VHBPCR_HBP3_Msk (0x1UL << DSI_VHBPCR_HBP3_Pos) /*!< 0x00000008 */
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+#define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk
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+#define DSI_VHBPCR_HBP4_Pos (4U)
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+#define DSI_VHBPCR_HBP4_Msk (0x1UL << DSI_VHBPCR_HBP4_Pos) /*!< 0x00000010 */
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+#define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk
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+#define DSI_VHBPCR_HBP5_Pos (5U)
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+#define DSI_VHBPCR_HBP5_Msk (0x1UL << DSI_VHBPCR_HBP5_Pos) /*!< 0x00000020 */
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+#define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk
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+#define DSI_VHBPCR_HBP6_Pos (6U)
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+#define DSI_VHBPCR_HBP6_Msk (0x1UL << DSI_VHBPCR_HBP6_Pos) /*!< 0x00000040 */
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+#define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk
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+#define DSI_VHBPCR_HBP7_Pos (7U)
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+#define DSI_VHBPCR_HBP7_Msk (0x1UL << DSI_VHBPCR_HBP7_Pos) /*!< 0x00000080 */
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+#define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk
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+#define DSI_VHBPCR_HBP8_Pos (8U)
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+#define DSI_VHBPCR_HBP8_Msk (0x1UL << DSI_VHBPCR_HBP8_Pos) /*!< 0x00000100 */
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+#define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk
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+#define DSI_VHBPCR_HBP9_Pos (9U)
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+#define DSI_VHBPCR_HBP9_Msk (0x1UL << DSI_VHBPCR_HBP9_Pos) /*!< 0x00000200 */
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+#define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk
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+#define DSI_VHBPCR_HBP10_Pos (10U)
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+#define DSI_VHBPCR_HBP10_Msk (0x1UL << DSI_VHBPCR_HBP10_Pos) /*!< 0x00000400 */
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+#define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk
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+#define DSI_VHBPCR_HBP11_Pos (11U)
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+#define DSI_VHBPCR_HBP11_Msk (0x1UL << DSI_VHBPCR_HBP11_Pos) /*!< 0x00000800 */
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+#define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk
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+
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+/******************* Bit definition for DSI_VLCR register ***************/
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+#define DSI_VLCR_HLINE_Pos (0U)
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+#define DSI_VLCR_HLINE_Msk (0x7FFFUL << DSI_VLCR_HLINE_Pos) /*!< 0x00007FFF */
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+#define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk /*!< Horizontal Line duration */
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+#define DSI_VLCR_HLINE0_Pos (0U)
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+#define DSI_VLCR_HLINE0_Msk (0x1UL << DSI_VLCR_HLINE0_Pos) /*!< 0x00000001 */
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+#define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk
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+#define DSI_VLCR_HLINE1_Pos (1U)
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+#define DSI_VLCR_HLINE1_Msk (0x1UL << DSI_VLCR_HLINE1_Pos) /*!< 0x00000002 */
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+#define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk
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+#define DSI_VLCR_HLINE2_Pos (2U)
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+#define DSI_VLCR_HLINE2_Msk (0x1UL << DSI_VLCR_HLINE2_Pos) /*!< 0x00000004 */
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+#define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk
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+#define DSI_VLCR_HLINE3_Pos (3U)
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+#define DSI_VLCR_HLINE3_Msk (0x1UL << DSI_VLCR_HLINE3_Pos) /*!< 0x00000008 */
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+#define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk
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+#define DSI_VLCR_HLINE4_Pos (4U)
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+#define DSI_VLCR_HLINE4_Msk (0x1UL << DSI_VLCR_HLINE4_Pos) /*!< 0x00000010 */
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+#define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk
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+#define DSI_VLCR_HLINE5_Pos (5U)
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+#define DSI_VLCR_HLINE5_Msk (0x1UL << DSI_VLCR_HLINE5_Pos) /*!< 0x00000020 */
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+#define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk
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+#define DSI_VLCR_HLINE6_Pos (6U)
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+#define DSI_VLCR_HLINE6_Msk (0x1UL << DSI_VLCR_HLINE6_Pos) /*!< 0x00000040 */
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+#define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk
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+#define DSI_VLCR_HLINE7_Pos (7U)
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+#define DSI_VLCR_HLINE7_Msk (0x1UL << DSI_VLCR_HLINE7_Pos) /*!< 0x00000080 */
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+#define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk
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+#define DSI_VLCR_HLINE8_Pos (8U)
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+#define DSI_VLCR_HLINE8_Msk (0x1UL << DSI_VLCR_HLINE8_Pos) /*!< 0x00000100 */
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+#define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk
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+#define DSI_VLCR_HLINE9_Pos (9U)
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+#define DSI_VLCR_HLINE9_Msk (0x1UL << DSI_VLCR_HLINE9_Pos) /*!< 0x00000200 */
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+#define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk
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+#define DSI_VLCR_HLINE10_Pos (10U)
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+#define DSI_VLCR_HLINE10_Msk (0x1UL << DSI_VLCR_HLINE10_Pos) /*!< 0x00000400 */
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+#define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk
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+#define DSI_VLCR_HLINE11_Pos (11U)
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+#define DSI_VLCR_HLINE11_Msk (0x1UL << DSI_VLCR_HLINE11_Pos) /*!< 0x00000800 */
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+#define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk
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+#define DSI_VLCR_HLINE12_Pos (12U)
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+#define DSI_VLCR_HLINE12_Msk (0x1UL << DSI_VLCR_HLINE12_Pos) /*!< 0x00001000 */
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+#define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk
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+#define DSI_VLCR_HLINE13_Pos (13U)
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+#define DSI_VLCR_HLINE13_Msk (0x1UL << DSI_VLCR_HLINE13_Pos) /*!< 0x00002000 */
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+#define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk
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+#define DSI_VLCR_HLINE14_Pos (14U)
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+#define DSI_VLCR_HLINE14_Msk (0x1UL << DSI_VLCR_HLINE14_Pos) /*!< 0x00004000 */
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+#define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk
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+
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+/******************* Bit definition for DSI_VVSACR register *************/
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+#define DSI_VVSACR_VSA_Pos (0U)
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+#define DSI_VVSACR_VSA_Msk (0x3FFUL << DSI_VVSACR_VSA_Pos) /*!< 0x000003FF */
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+#define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk /*!< Vertical Synchronism Active duration */
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+#define DSI_VVSACR_VSA0_Pos (0U)
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+#define DSI_VVSACR_VSA0_Msk (0x1UL << DSI_VVSACR_VSA0_Pos) /*!< 0x00000001 */
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+#define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk
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+#define DSI_VVSACR_VSA1_Pos (1U)
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+#define DSI_VVSACR_VSA1_Msk (0x1UL << DSI_VVSACR_VSA1_Pos) /*!< 0x00000002 */
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+#define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk
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+#define DSI_VVSACR_VSA2_Pos (2U)
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+#define DSI_VVSACR_VSA2_Msk (0x1UL << DSI_VVSACR_VSA2_Pos) /*!< 0x00000004 */
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+#define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk
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+#define DSI_VVSACR_VSA3_Pos (3U)
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+#define DSI_VVSACR_VSA3_Msk (0x1UL << DSI_VVSACR_VSA3_Pos) /*!< 0x00000008 */
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+#define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk
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+#define DSI_VVSACR_VSA4_Pos (4U)
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+#define DSI_VVSACR_VSA4_Msk (0x1UL << DSI_VVSACR_VSA4_Pos) /*!< 0x00000010 */
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+#define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk
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+#define DSI_VVSACR_VSA5_Pos (5U)
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+#define DSI_VVSACR_VSA5_Msk (0x1UL << DSI_VVSACR_VSA5_Pos) /*!< 0x00000020 */
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+#define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk
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+#define DSI_VVSACR_VSA6_Pos (6U)
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+#define DSI_VVSACR_VSA6_Msk (0x1UL << DSI_VVSACR_VSA6_Pos) /*!< 0x00000040 */
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+#define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk
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+#define DSI_VVSACR_VSA7_Pos (7U)
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+#define DSI_VVSACR_VSA7_Msk (0x1UL << DSI_VVSACR_VSA7_Pos) /*!< 0x00000080 */
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+#define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk
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+#define DSI_VVSACR_VSA8_Pos (8U)
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+#define DSI_VVSACR_VSA8_Msk (0x1UL << DSI_VVSACR_VSA8_Pos) /*!< 0x00000100 */
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+#define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk
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|
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+#define DSI_VVSACR_VSA9_Pos (9U)
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+#define DSI_VVSACR_VSA9_Msk (0x1UL << DSI_VVSACR_VSA9_Pos) /*!< 0x00000200 */
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+#define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk
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+
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|
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+/******************* Bit definition for DSI_VVBPCR register *************/
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+#define DSI_VVBPCR_VBP_Pos (0U)
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+#define DSI_VVBPCR_VBP_Msk (0x3FFUL << DSI_VVBPCR_VBP_Pos) /*!< 0x000003FF */
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+#define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk /*!< Vertical Back-Porch duration */
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+#define DSI_VVBPCR_VBP0_Pos (0U)
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+#define DSI_VVBPCR_VBP0_Msk (0x1UL << DSI_VVBPCR_VBP0_Pos) /*!< 0x00000001 */
|
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+#define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk
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+#define DSI_VVBPCR_VBP1_Pos (1U)
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+#define DSI_VVBPCR_VBP1_Msk (0x1UL << DSI_VVBPCR_VBP1_Pos) /*!< 0x00000002 */
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|
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+#define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk
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|
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+#define DSI_VVBPCR_VBP2_Pos (2U)
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+#define DSI_VVBPCR_VBP2_Msk (0x1UL << DSI_VVBPCR_VBP2_Pos) /*!< 0x00000004 */
|
|
|
+#define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk
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+#define DSI_VVBPCR_VBP3_Pos (3U)
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+#define DSI_VVBPCR_VBP3_Msk (0x1UL << DSI_VVBPCR_VBP3_Pos) /*!< 0x00000008 */
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+#define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk
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+#define DSI_VVBPCR_VBP4_Pos (4U)
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+#define DSI_VVBPCR_VBP4_Msk (0x1UL << DSI_VVBPCR_VBP4_Pos) /*!< 0x00000010 */
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+#define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk
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|
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+#define DSI_VVBPCR_VBP5_Pos (5U)
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+#define DSI_VVBPCR_VBP5_Msk (0x1UL << DSI_VVBPCR_VBP5_Pos) /*!< 0x00000020 */
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+#define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk
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+#define DSI_VVBPCR_VBP6_Pos (6U)
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+#define DSI_VVBPCR_VBP6_Msk (0x1UL << DSI_VVBPCR_VBP6_Pos) /*!< 0x00000040 */
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|
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+#define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk
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|
|
+#define DSI_VVBPCR_VBP7_Pos (7U)
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+#define DSI_VVBPCR_VBP7_Msk (0x1UL << DSI_VVBPCR_VBP7_Pos) /*!< 0x00000080 */
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+#define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk
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+#define DSI_VVBPCR_VBP8_Pos (8U)
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+#define DSI_VVBPCR_VBP8_Msk (0x1UL << DSI_VVBPCR_VBP8_Pos) /*!< 0x00000100 */
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|
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+#define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk
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|
+#define DSI_VVBPCR_VBP9_Pos (9U)
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+#define DSI_VVBPCR_VBP9_Msk (0x1UL << DSI_VVBPCR_VBP9_Pos) /*!< 0x00000200 */
|
|
|
+#define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk
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|
+
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+/******************* Bit definition for DSI_VVFPCR register *************/
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+#define DSI_VVFPCR_VFP_Pos (0U)
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+#define DSI_VVFPCR_VFP_Msk (0x3FFUL << DSI_VVFPCR_VFP_Pos) /*!< 0x000003FF */
|
|
|
+#define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk /*!< Vertical Front-Porch duration */
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|
|
+#define DSI_VVFPCR_VFP0_Pos (0U)
|
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|
+#define DSI_VVFPCR_VFP0_Msk (0x1UL << DSI_VVFPCR_VFP0_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk
|
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+#define DSI_VVFPCR_VFP1_Pos (1U)
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+#define DSI_VVFPCR_VFP1_Msk (0x1UL << DSI_VVFPCR_VFP1_Pos) /*!< 0x00000002 */
|
|
|
+#define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk
|
|
|
+#define DSI_VVFPCR_VFP2_Pos (2U)
|
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+#define DSI_VVFPCR_VFP2_Msk (0x1UL << DSI_VVFPCR_VFP2_Pos) /*!< 0x00000004 */
|
|
|
+#define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk
|
|
|
+#define DSI_VVFPCR_VFP3_Pos (3U)
|
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|
+#define DSI_VVFPCR_VFP3_Msk (0x1UL << DSI_VVFPCR_VFP3_Pos) /*!< 0x00000008 */
|
|
|
+#define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk
|
|
|
+#define DSI_VVFPCR_VFP4_Pos (4U)
|
|
|
+#define DSI_VVFPCR_VFP4_Msk (0x1UL << DSI_VVFPCR_VFP4_Pos) /*!< 0x00000010 */
|
|
|
+#define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk
|
|
|
+#define DSI_VVFPCR_VFP5_Pos (5U)
|
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|
+#define DSI_VVFPCR_VFP5_Msk (0x1UL << DSI_VVFPCR_VFP5_Pos) /*!< 0x00000020 */
|
|
|
+#define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk
|
|
|
+#define DSI_VVFPCR_VFP6_Pos (6U)
|
|
|
+#define DSI_VVFPCR_VFP6_Msk (0x1UL << DSI_VVFPCR_VFP6_Pos) /*!< 0x00000040 */
|
|
|
+#define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk
|
|
|
+#define DSI_VVFPCR_VFP7_Pos (7U)
|
|
|
+#define DSI_VVFPCR_VFP7_Msk (0x1UL << DSI_VVFPCR_VFP7_Pos) /*!< 0x00000080 */
|
|
|
+#define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk
|
|
|
+#define DSI_VVFPCR_VFP8_Pos (8U)
|
|
|
+#define DSI_VVFPCR_VFP8_Msk (0x1UL << DSI_VVFPCR_VFP8_Pos) /*!< 0x00000100 */
|
|
|
+#define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk
|
|
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+#define DSI_VVFPCR_VFP9_Pos (9U)
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+#define DSI_VVFPCR_VFP9_Msk (0x1UL << DSI_VVFPCR_VFP9_Pos) /*!< 0x00000200 */
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+#define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk
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+
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+/******************* Bit definition for DSI_VVACR register **************/
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+#define DSI_VVACR_VA_Pos (0U)
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+#define DSI_VVACR_VA_Msk (0x3FFFUL << DSI_VVACR_VA_Pos) /*!< 0x00003FFF */
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+#define DSI_VVACR_VA DSI_VVACR_VA_Msk /*!< Vertical Active duration */
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+#define DSI_VVACR_VA0_Pos (0U)
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+#define DSI_VVACR_VA0_Msk (0x1UL << DSI_VVACR_VA0_Pos) /*!< 0x00000001 */
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+#define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk
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+#define DSI_VVACR_VA1_Pos (1U)
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+#define DSI_VVACR_VA1_Msk (0x1UL << DSI_VVACR_VA1_Pos) /*!< 0x00000002 */
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+#define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk
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+#define DSI_VVACR_VA2_Pos (2U)
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+#define DSI_VVACR_VA2_Msk (0x1UL << DSI_VVACR_VA2_Pos) /*!< 0x00000004 */
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+#define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk
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+#define DSI_VVACR_VA3_Pos (3U)
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+#define DSI_VVACR_VA3_Msk (0x1UL << DSI_VVACR_VA3_Pos) /*!< 0x00000008 */
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+#define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk
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+#define DSI_VVACR_VA4_Pos (4U)
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+#define DSI_VVACR_VA4_Msk (0x1UL << DSI_VVACR_VA4_Pos) /*!< 0x00000010 */
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+#define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk
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+#define DSI_VVACR_VA5_Pos (5U)
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+#define DSI_VVACR_VA5_Msk (0x1UL << DSI_VVACR_VA5_Pos) /*!< 0x00000020 */
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+#define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk
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+#define DSI_VVACR_VA6_Pos (6U)
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+#define DSI_VVACR_VA6_Msk (0x1UL << DSI_VVACR_VA6_Pos) /*!< 0x00000040 */
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+#define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk
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+#define DSI_VVACR_VA7_Pos (7U)
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+#define DSI_VVACR_VA7_Msk (0x1UL << DSI_VVACR_VA7_Pos) /*!< 0x00000080 */
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+#define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk
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+#define DSI_VVACR_VA8_Pos (8U)
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+#define DSI_VVACR_VA8_Msk (0x1UL << DSI_VVACR_VA8_Pos) /*!< 0x00000100 */
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+#define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk
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+#define DSI_VVACR_VA9_Pos (9U)
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+#define DSI_VVACR_VA9_Msk (0x1UL << DSI_VVACR_VA9_Pos) /*!< 0x00000200 */
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+#define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk
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+#define DSI_VVACR_VA10_Pos (10U)
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+#define DSI_VVACR_VA10_Msk (0x1UL << DSI_VVACR_VA10_Pos) /*!< 0x00000400 */
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+#define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk
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+#define DSI_VVACR_VA11_Pos (11U)
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+#define DSI_VVACR_VA11_Msk (0x1UL << DSI_VVACR_VA11_Pos) /*!< 0x00000800 */
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+#define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk
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+#define DSI_VVACR_VA12_Pos (12U)
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+#define DSI_VVACR_VA12_Msk (0x1UL << DSI_VVACR_VA12_Pos) /*!< 0x00001000 */
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+#define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk
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+#define DSI_VVACR_VA13_Pos (13U)
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+#define DSI_VVACR_VA13_Msk (0x1UL << DSI_VVACR_VA13_Pos) /*!< 0x00002000 */
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+#define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk
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+
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|
|
+/******************* Bit definition for DSI_LCCR register ***************/
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+#define DSI_LCCR_CMDSIZE_Pos (0U)
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+#define DSI_LCCR_CMDSIZE_Msk (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos) /*!< 0x0000FFFF */
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+#define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk /*!< Command Size */
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+#define DSI_LCCR_CMDSIZE0_Pos (0U)
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+#define DSI_LCCR_CMDSIZE0_Msk (0x1UL << DSI_LCCR_CMDSIZE0_Pos) /*!< 0x00000001 */
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+#define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk
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+#define DSI_LCCR_CMDSIZE1_Pos (1U)
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+#define DSI_LCCR_CMDSIZE1_Msk (0x1UL << DSI_LCCR_CMDSIZE1_Pos) /*!< 0x00000002 */
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+#define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk
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+#define DSI_LCCR_CMDSIZE2_Pos (2U)
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+#define DSI_LCCR_CMDSIZE2_Msk (0x1UL << DSI_LCCR_CMDSIZE2_Pos) /*!< 0x00000004 */
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+#define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk
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+#define DSI_LCCR_CMDSIZE3_Pos (3U)
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+#define DSI_LCCR_CMDSIZE3_Msk (0x1UL << DSI_LCCR_CMDSIZE3_Pos) /*!< 0x00000008 */
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+#define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk
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+#define DSI_LCCR_CMDSIZE4_Pos (4U)
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+#define DSI_LCCR_CMDSIZE4_Msk (0x1UL << DSI_LCCR_CMDSIZE4_Pos) /*!< 0x00000010 */
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+#define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk
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+#define DSI_LCCR_CMDSIZE5_Pos (5U)
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+#define DSI_LCCR_CMDSIZE5_Msk (0x1UL << DSI_LCCR_CMDSIZE5_Pos) /*!< 0x00000020 */
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+#define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk
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+#define DSI_LCCR_CMDSIZE6_Pos (6U)
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+#define DSI_LCCR_CMDSIZE6_Msk (0x1UL << DSI_LCCR_CMDSIZE6_Pos) /*!< 0x00000040 */
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+#define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk
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+#define DSI_LCCR_CMDSIZE7_Pos (7U)
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+#define DSI_LCCR_CMDSIZE7_Msk (0x1UL << DSI_LCCR_CMDSIZE7_Pos) /*!< 0x00000080 */
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+#define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk
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+#define DSI_LCCR_CMDSIZE8_Pos (8U)
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+#define DSI_LCCR_CMDSIZE8_Msk (0x1UL << DSI_LCCR_CMDSIZE8_Pos) /*!< 0x00000100 */
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+#define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk
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+#define DSI_LCCR_CMDSIZE9_Pos (9U)
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+#define DSI_LCCR_CMDSIZE9_Msk (0x1UL << DSI_LCCR_CMDSIZE9_Pos) /*!< 0x00000200 */
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+#define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk
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+#define DSI_LCCR_CMDSIZE10_Pos (10U)
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+#define DSI_LCCR_CMDSIZE10_Msk (0x1UL << DSI_LCCR_CMDSIZE10_Pos) /*!< 0x00000400 */
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+#define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk
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+#define DSI_LCCR_CMDSIZE11_Pos (11U)
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+#define DSI_LCCR_CMDSIZE11_Msk (0x1UL << DSI_LCCR_CMDSIZE11_Pos) /*!< 0x00000800 */
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+#define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk
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+#define DSI_LCCR_CMDSIZE12_Pos (12U)
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+#define DSI_LCCR_CMDSIZE12_Msk (0x1UL << DSI_LCCR_CMDSIZE12_Pos) /*!< 0x00001000 */
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+#define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk
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+#define DSI_LCCR_CMDSIZE13_Pos (13U)
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+#define DSI_LCCR_CMDSIZE13_Msk (0x1UL << DSI_LCCR_CMDSIZE13_Pos) /*!< 0x00002000 */
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+#define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk
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+#define DSI_LCCR_CMDSIZE14_Pos (14U)
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+#define DSI_LCCR_CMDSIZE14_Msk (0x1UL << DSI_LCCR_CMDSIZE14_Pos) /*!< 0x00004000 */
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+#define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk
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+#define DSI_LCCR_CMDSIZE15_Pos (15U)
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+#define DSI_LCCR_CMDSIZE15_Msk (0x1UL << DSI_LCCR_CMDSIZE15_Pos) /*!< 0x00008000 */
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+#define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk
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+
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+/******************* Bit definition for DSI_CMCR register ***************/
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+#define DSI_CMCR_TEARE_Pos (0U)
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+#define DSI_CMCR_TEARE_Msk (0x1UL << DSI_CMCR_TEARE_Pos) /*!< 0x00000001 */
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+#define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk /*!< Tearing Effect Acknowledge Request Enable */
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+#define DSI_CMCR_ARE_Pos (1U)
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+#define DSI_CMCR_ARE_Msk (0x1UL << DSI_CMCR_ARE_Pos) /*!< 0x00000002 */
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+#define DSI_CMCR_ARE DSI_CMCR_ARE_Msk /*!< Acknowledge Request Enable */
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+#define DSI_CMCR_GSW0TX_Pos (8U)
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+#define DSI_CMCR_GSW0TX_Msk (0x1UL << DSI_CMCR_GSW0TX_Pos) /*!< 0x00000100 */
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+#define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk /*!< Generic Short Write Zero parameters Transmission */
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+#define DSI_CMCR_GSW1TX_Pos (9U)
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+#define DSI_CMCR_GSW1TX_Msk (0x1UL << DSI_CMCR_GSW1TX_Pos) /*!< 0x00000200 */
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+#define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk /*!< Generic Short Write One parameters Transmission */
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+#define DSI_CMCR_GSW2TX_Pos (10U)
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+#define DSI_CMCR_GSW2TX_Msk (0x1UL << DSI_CMCR_GSW2TX_Pos) /*!< 0x00000400 */
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+#define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk /*!< Generic Short Write Two parameters Transmission */
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+#define DSI_CMCR_GSR0TX_Pos (11U)
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+#define DSI_CMCR_GSR0TX_Msk (0x1UL << DSI_CMCR_GSR0TX_Pos) /*!< 0x00000800 */
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+#define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk /*!< Generic Short Read Zero parameters Transmission */
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+#define DSI_CMCR_GSR1TX_Pos (12U)
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+#define DSI_CMCR_GSR1TX_Msk (0x1UL << DSI_CMCR_GSR1TX_Pos) /*!< 0x00001000 */
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+#define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk /*!< Generic Short Read One parameters Transmission */
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+#define DSI_CMCR_GSR2TX_Pos (13U)
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+#define DSI_CMCR_GSR2TX_Msk (0x1UL << DSI_CMCR_GSR2TX_Pos) /*!< 0x00002000 */
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+#define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk /*!< Generic Short Read Two parameters Transmission */
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+#define DSI_CMCR_GLWTX_Pos (14U)
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+#define DSI_CMCR_GLWTX_Msk (0x1UL << DSI_CMCR_GLWTX_Pos) /*!< 0x00004000 */
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+#define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk /*!< Generic Long Write Transmission */
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+#define DSI_CMCR_DSW0TX_Pos (16U)
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+#define DSI_CMCR_DSW0TX_Msk (0x1UL << DSI_CMCR_DSW0TX_Pos) /*!< 0x00010000 */
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+#define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk /*!< DCS Short Write Zero parameter Transmission */
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+#define DSI_CMCR_DSW1TX_Pos (17U)
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+#define DSI_CMCR_DSW1TX_Msk (0x1UL << DSI_CMCR_DSW1TX_Pos) /*!< 0x00020000 */
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+#define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk /*!< DCS Short Read One parameter Transmission */
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+#define DSI_CMCR_DSR0TX_Pos (18U)
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+#define DSI_CMCR_DSR0TX_Msk (0x1UL << DSI_CMCR_DSR0TX_Pos) /*!< 0x00040000 */
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+#define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk /*!< DCS Short Read Zero parameter Transmission */
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+#define DSI_CMCR_DLWTX_Pos (19U)
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+#define DSI_CMCR_DLWTX_Msk (0x1UL << DSI_CMCR_DLWTX_Pos) /*!< 0x00080000 */
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+#define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk /*!< DCS Long Write Transmission */
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+#define DSI_CMCR_MRDPS_Pos (24U)
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+#define DSI_CMCR_MRDPS_Msk (0x1UL << DSI_CMCR_MRDPS_Pos) /*!< 0x01000000 */
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+#define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk /*!< Maximum Read Packet Size */
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+
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+/******************* Bit definition for DSI_GHCR register ***************/
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+#define DSI_GHCR_DT_Pos (0U)
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+#define DSI_GHCR_DT_Msk (0x3FUL << DSI_GHCR_DT_Pos) /*!< 0x0000003F */
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+#define DSI_GHCR_DT DSI_GHCR_DT_Msk /*!< Type */
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+#define DSI_GHCR_DT0_Pos (0U)
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+#define DSI_GHCR_DT0_Msk (0x1UL << DSI_GHCR_DT0_Pos) /*!< 0x00000001 */
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+#define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk
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+#define DSI_GHCR_DT1_Pos (1U)
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+#define DSI_GHCR_DT1_Msk (0x1UL << DSI_GHCR_DT1_Pos) /*!< 0x00000002 */
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+#define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk
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+#define DSI_GHCR_DT2_Pos (2U)
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+#define DSI_GHCR_DT2_Msk (0x1UL << DSI_GHCR_DT2_Pos) /*!< 0x00000004 */
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+#define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk
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+#define DSI_GHCR_DT3_Pos (3U)
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+#define DSI_GHCR_DT3_Msk (0x1UL << DSI_GHCR_DT3_Pos) /*!< 0x00000008 */
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+#define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk
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+#define DSI_GHCR_DT4_Pos (4U)
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+#define DSI_GHCR_DT4_Msk (0x1UL << DSI_GHCR_DT4_Pos) /*!< 0x00000010 */
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+#define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk
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+#define DSI_GHCR_DT5_Pos (5U)
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+#define DSI_GHCR_DT5_Msk (0x1UL << DSI_GHCR_DT5_Pos) /*!< 0x00000020 */
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+#define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk
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+
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+#define DSI_GHCR_VCID_Pos (6U)
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+#define DSI_GHCR_VCID_Msk (0x3UL << DSI_GHCR_VCID_Pos) /*!< 0x000000C0 */
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+#define DSI_GHCR_VCID DSI_GHCR_VCID_Msk /*!< Channel */
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+#define DSI_GHCR_VCID0_Pos (6U)
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+#define DSI_GHCR_VCID0_Msk (0x1UL << DSI_GHCR_VCID0_Pos) /*!< 0x00000040 */
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+#define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk
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+#define DSI_GHCR_VCID1_Pos (7U)
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+#define DSI_GHCR_VCID1_Msk (0x1UL << DSI_GHCR_VCID1_Pos) /*!< 0x00000080 */
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+#define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk
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+
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+#define DSI_GHCR_WCLSB_Pos (8U)
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+#define DSI_GHCR_WCLSB_Msk (0xFFUL << DSI_GHCR_WCLSB_Pos) /*!< 0x0000FF00 */
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+#define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk /*!< WordCount LSB */
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+#define DSI_GHCR_WCLSB0_Pos (8U)
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+#define DSI_GHCR_WCLSB0_Msk (0x1UL << DSI_GHCR_WCLSB0_Pos) /*!< 0x00000100 */
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+#define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk
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+#define DSI_GHCR_WCLSB1_Pos (9U)
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+#define DSI_GHCR_WCLSB1_Msk (0x1UL << DSI_GHCR_WCLSB1_Pos) /*!< 0x00000200 */
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+#define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk
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+#define DSI_GHCR_WCLSB2_Pos (10U)
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+#define DSI_GHCR_WCLSB2_Msk (0x1UL << DSI_GHCR_WCLSB2_Pos) /*!< 0x00000400 */
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+#define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk
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|
+#define DSI_GHCR_WCLSB3_Pos (11U)
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+#define DSI_GHCR_WCLSB3_Msk (0x1UL << DSI_GHCR_WCLSB3_Pos) /*!< 0x00000800 */
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+#define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk
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+#define DSI_GHCR_WCLSB4_Pos (12U)
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+#define DSI_GHCR_WCLSB4_Msk (0x1UL << DSI_GHCR_WCLSB4_Pos) /*!< 0x00001000 */
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|
+#define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk
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|
+#define DSI_GHCR_WCLSB5_Pos (13U)
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+#define DSI_GHCR_WCLSB5_Msk (0x1UL << DSI_GHCR_WCLSB5_Pos) /*!< 0x00002000 */
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|
+#define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk
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+#define DSI_GHCR_WCLSB6_Pos (14U)
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+#define DSI_GHCR_WCLSB6_Msk (0x1UL << DSI_GHCR_WCLSB6_Pos) /*!< 0x00004000 */
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|
+#define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk
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|
+#define DSI_GHCR_WCLSB7_Pos (15U)
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|
+#define DSI_GHCR_WCLSB7_Msk (0x1UL << DSI_GHCR_WCLSB7_Pos) /*!< 0x00008000 */
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|
+#define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk
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+
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|
+#define DSI_GHCR_WCMSB_Pos (16U)
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+#define DSI_GHCR_WCMSB_Msk (0xFFUL << DSI_GHCR_WCMSB_Pos) /*!< 0x00FF0000 */
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|
+#define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk /*!< WordCount MSB */
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|
+#define DSI_GHCR_WCMSB0_Pos (16U)
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|
+#define DSI_GHCR_WCMSB0_Msk (0x1UL << DSI_GHCR_WCMSB0_Pos) /*!< 0x00010000 */
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|
+#define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk
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|
+#define DSI_GHCR_WCMSB1_Pos (17U)
|
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+#define DSI_GHCR_WCMSB1_Msk (0x1UL << DSI_GHCR_WCMSB1_Pos) /*!< 0x00020000 */
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+#define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk
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+#define DSI_GHCR_WCMSB2_Pos (18U)
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+#define DSI_GHCR_WCMSB2_Msk (0x1UL << DSI_GHCR_WCMSB2_Pos) /*!< 0x00040000 */
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+#define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk
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+#define DSI_GHCR_WCMSB3_Pos (19U)
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+#define DSI_GHCR_WCMSB3_Msk (0x1UL << DSI_GHCR_WCMSB3_Pos) /*!< 0x00080000 */
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+#define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk
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+#define DSI_GHCR_WCMSB4_Pos (20U)
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+#define DSI_GHCR_WCMSB4_Msk (0x1UL << DSI_GHCR_WCMSB4_Pos) /*!< 0x00100000 */
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+#define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk
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+#define DSI_GHCR_WCMSB5_Pos (21U)
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+#define DSI_GHCR_WCMSB5_Msk (0x1UL << DSI_GHCR_WCMSB5_Pos) /*!< 0x00200000 */
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+#define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk
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+#define DSI_GHCR_WCMSB6_Pos (22U)
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+#define DSI_GHCR_WCMSB6_Msk (0x1UL << DSI_GHCR_WCMSB6_Pos) /*!< 0x00400000 */
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+#define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk
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+#define DSI_GHCR_WCMSB7_Pos (23U)
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+#define DSI_GHCR_WCMSB7_Msk (0x1UL << DSI_GHCR_WCMSB7_Pos) /*!< 0x00800000 */
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+#define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk
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+
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+/******************* Bit definition for DSI_GPDR register ***************/
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+#define DSI_GPDR_DATA1_Pos (0U)
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+#define DSI_GPDR_DATA1_Msk (0xFFUL << DSI_GPDR_DATA1_Pos) /*!< 0x000000FF */
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+#define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk /*!< Payload Byte 1 */
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+#define DSI_GPDR_DATA1_0 (0x01UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000001 */
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+#define DSI_GPDR_DATA1_1 (0x02UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000002 */
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+#define DSI_GPDR_DATA1_2 (0x04UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000004 */
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+#define DSI_GPDR_DATA1_3 (0x08UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000008 */
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+#define DSI_GPDR_DATA1_4 (0x10UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000010 */
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+#define DSI_GPDR_DATA1_5 (0x20UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000020 */
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+#define DSI_GPDR_DATA1_6 (0x40UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000040 */
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+#define DSI_GPDR_DATA1_7 (0x80UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000080 */
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+
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+#define DSI_GPDR_DATA2_Pos (8U)
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+#define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
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+#define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk /*!< Payload Byte 2 */
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+#define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
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+#define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
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+#define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
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+#define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
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+#define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
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+#define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
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+#define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
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+#define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
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+
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+#define DSI_GPDR_DATA3_Pos (16U)
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+#define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
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+#define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk /*!< Payload Byte 3 */
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+#define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
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+#define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
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+#define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
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+#define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
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+#define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
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+#define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
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+#define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
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+#define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
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+
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+#define DSI_GPDR_DATA4_Pos (24U)
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+#define DSI_GPDR_DATA4_Msk (0xFFUL << DSI_GPDR_DATA4_Pos) /*!< 0xFF000000 */
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+#define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk /*!< Payload Byte 4 */
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+#define DSI_GPDR_DATA4_0 (0x01UL << DSI_GPDR_DATA4_Pos) /*!< 0x01000000 */
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+#define DSI_GPDR_DATA4_1 (0x02UL << DSI_GPDR_DATA4_Pos) /*!< 0x02000000 */
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+#define DSI_GPDR_DATA4_2 (0x04UL << DSI_GPDR_DATA4_Pos) /*!< 0x04000000 */
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+#define DSI_GPDR_DATA4_3 (0x08UL << DSI_GPDR_DATA4_Pos) /*!< 0x08000000 */
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+#define DSI_GPDR_DATA4_4 (0x10UL << DSI_GPDR_DATA4_Pos) /*!< 0x10000000 */
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+#define DSI_GPDR_DATA4_5 (0x20UL << DSI_GPDR_DATA4_Pos) /*!< 0x20000000 */
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+#define DSI_GPDR_DATA4_6 (0x40UL << DSI_GPDR_DATA4_Pos) /*!< 0x40000000 */
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+#define DSI_GPDR_DATA4_7 (0x80UL << DSI_GPDR_DATA4_Pos) /*!< 0x80000000 */
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+
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+/******************* Bit definition for DSI_GPSR register ***************/
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+#define DSI_GPSR_CMDFE_Pos (0U)
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+#define DSI_GPSR_CMDFE_Msk (0x1UL << DSI_GPSR_CMDFE_Pos) /*!< 0x00000001 */
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+#define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk /*!< Command FIFO Empty */
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+#define DSI_GPSR_CMDFF_Pos (1U)
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+#define DSI_GPSR_CMDFF_Msk (0x1UL << DSI_GPSR_CMDFF_Pos) /*!< 0x00000002 */
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+#define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk /*!< Command FIFO Full */
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+#define DSI_GPSR_PWRFE_Pos (2U)
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+#define DSI_GPSR_PWRFE_Msk (0x1UL << DSI_GPSR_PWRFE_Pos) /*!< 0x00000004 */
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+#define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk /*!< Payload Write FIFO Empty */
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+#define DSI_GPSR_PWRFF_Pos (3U)
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+#define DSI_GPSR_PWRFF_Msk (0x1UL << DSI_GPSR_PWRFF_Pos) /*!< 0x00000008 */
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+#define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk /*!< Payload Write FIFO Full */
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+#define DSI_GPSR_PRDFE_Pos (4U)
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+#define DSI_GPSR_PRDFE_Msk (0x1UL << DSI_GPSR_PRDFE_Pos) /*!< 0x00000010 */
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+#define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk /*!< Payload Read FIFO Empty */
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+#define DSI_GPSR_PRDFF_Pos (5U)
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+#define DSI_GPSR_PRDFF_Msk (0x1UL << DSI_GPSR_PRDFF_Pos) /*!< 0x00000020 */
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+#define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk /*!< Payload Read FIFO Full */
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+#define DSI_GPSR_RCB_Pos (6U)
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+#define DSI_GPSR_RCB_Msk (0x1UL << DSI_GPSR_RCB_Pos) /*!< 0x00000040 */
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+#define DSI_GPSR_RCB DSI_GPSR_RCB_Msk /*!< Read Command Busy */
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+
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+/******************* Bit definition for DSI_TCCR0register **************/
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+#define DSI_TCCR0_LPRX_TOCNT_Pos (0U)
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+#define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos) /*!< 0x0000FFFF */
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+#define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk /*!< Low-power Reception Timeout Counter */
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+#define DSI_TCCR0_LPRX_TOCNT0_Pos (0U)
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+#define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos) /*!< 0x00000001 */
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+#define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk
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+#define DSI_TCCR0_LPRX_TOCNT1_Pos (1U)
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+#define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos) /*!< 0x00000002 */
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+#define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk
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+#define DSI_TCCR0_LPRX_TOCNT2_Pos (2U)
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+#define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos) /*!< 0x00000004 */
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+#define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk
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+#define DSI_TCCR0_LPRX_TOCNT3_Pos (3U)
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+#define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos) /*!< 0x00000008 */
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+#define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk
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+#define DSI_TCCR0_LPRX_TOCNT4_Pos (4U)
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+#define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos) /*!< 0x00000010 */
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+#define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk
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+#define DSI_TCCR0_LPRX_TOCNT5_Pos (5U)
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+#define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos) /*!< 0x00000020 */
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+#define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk
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+#define DSI_TCCR0_LPRX_TOCNT6_Pos (6U)
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+#define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos) /*!< 0x00000040 */
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+#define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk
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+#define DSI_TCCR0_LPRX_TOCNT7_Pos (7U)
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+#define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos) /*!< 0x00000080 */
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+#define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk
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+#define DSI_TCCR0_LPRX_TOCNT8_Pos (8U)
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+#define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos) /*!< 0x00000100 */
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+#define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk
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+#define DSI_TCCR0_LPRX_TOCNT9_Pos (9U)
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+#define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos) /*!< 0x00000200 */
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+#define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk
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+#define DSI_TCCR0_LPRX_TOCNT10_Pos (10U)
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+#define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos) /*!< 0x00000400 */
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+#define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk
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+#define DSI_TCCR0_LPRX_TOCNT11_Pos (11U)
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+#define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos) /*!< 0x00000800 */
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+#define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk
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+#define DSI_TCCR0_LPRX_TOCNT12_Pos (12U)
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+#define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos) /*!< 0x00001000 */
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+#define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk
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+#define DSI_TCCR0_LPRX_TOCNT13_Pos (13U)
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+#define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos) /*!< 0x00002000 */
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+#define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk
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+#define DSI_TCCR0_LPRX_TOCNT14_Pos (14U)
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+#define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos) /*!< 0x00004000 */
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+#define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk
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+#define DSI_TCCR0_LPRX_TOCNT15_Pos (15U)
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+#define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos) /*!< 0x00008000 */
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+#define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk
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+
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+#define DSI_TCCR0_HSTX_TOCNT_Pos (16U)
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+#define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos) /*!< 0xFFFF0000 */
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+#define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk /*!< High-Speed Transmission Timeout Counter */
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+#define DSI_TCCR0_HSTX_TOCNT0_Pos (16U)
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+#define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos) /*!< 0x00010000 */
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+#define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk
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+#define DSI_TCCR0_HSTX_TOCNT1_Pos (17U)
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+#define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos) /*!< 0x00020000 */
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+#define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk
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+#define DSI_TCCR0_HSTX_TOCNT2_Pos (18U)
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+#define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos) /*!< 0x00040000 */
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+#define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk
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+#define DSI_TCCR0_HSTX_TOCNT3_Pos (19U)
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+#define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos) /*!< 0x00080000 */
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+#define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk
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+#define DSI_TCCR0_HSTX_TOCNT4_Pos (20U)
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+#define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos) /*!< 0x00100000 */
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+#define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk
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+#define DSI_TCCR0_HSTX_TOCNT5_Pos (21U)
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+#define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos) /*!< 0x00200000 */
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+#define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk
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+#define DSI_TCCR0_HSTX_TOCNT6_Pos (22U)
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+#define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos) /*!< 0x00400000 */
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+#define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk
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+#define DSI_TCCR0_HSTX_TOCNT7_Pos (23U)
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+#define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos) /*!< 0x00800000 */
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+#define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk
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+#define DSI_TCCR0_HSTX_TOCNT8_Pos (24U)
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+#define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos) /*!< 0x01000000 */
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+#define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk
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+#define DSI_TCCR0_HSTX_TOCNT9_Pos (25U)
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+#define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos) /*!< 0x02000000 */
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+#define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk
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+#define DSI_TCCR0_HSTX_TOCNT10_Pos (26U)
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+#define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos) /*!< 0x04000000 */
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+#define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk
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+#define DSI_TCCR0_HSTX_TOCNT11_Pos (27U)
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+#define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos) /*!< 0x08000000 */
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+#define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk
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+#define DSI_TCCR0_HSTX_TOCNT12_Pos (28U)
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+#define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos) /*!< 0x10000000 */
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+#define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk
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+#define DSI_TCCR0_HSTX_TOCNT13_Pos (29U)
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+#define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos) /*!< 0x20000000 */
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+#define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk
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+#define DSI_TCCR0_HSTX_TOCNT14_Pos (30U)
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+#define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos) /*!< 0x40000000 */
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+#define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk
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+#define DSI_TCCR0_HSTX_TOCNT15_Pos (31U)
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+#define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos) /*!< 0x80000000 */
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+#define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk
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+
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+/******************* Bit definition for DSI_TCCR1register **************/
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+#define DSI_TCCR1_HSRD_TOCNT_Pos (0U)
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+#define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos) /*!< 0x0000FFFF */
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+#define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk /*!< High-Speed Read Timeout Counter */
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+#define DSI_TCCR1_HSRD_TOCNT0_Pos (0U)
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+#define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos) /*!< 0x00000001 */
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+#define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk
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+#define DSI_TCCR1_HSRD_TOCNT1_Pos (1U)
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+#define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos) /*!< 0x00000002 */
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+#define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk
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+#define DSI_TCCR1_HSRD_TOCNT2_Pos (2U)
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+#define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos) /*!< 0x00000004 */
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+#define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk
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+#define DSI_TCCR1_HSRD_TOCNT3_Pos (3U)
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+#define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos) /*!< 0x00000008 */
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+#define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk
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+#define DSI_TCCR1_HSRD_TOCNT4_Pos (4U)
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+#define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos) /*!< 0x00000010 */
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+#define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk
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+#define DSI_TCCR1_HSRD_TOCNT5_Pos (5U)
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+#define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos) /*!< 0x00000020 */
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+#define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk
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+#define DSI_TCCR1_HSRD_TOCNT6_Pos (6U)
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+#define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos) /*!< 0x00000040 */
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+#define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk
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+#define DSI_TCCR1_HSRD_TOCNT7_Pos (7U)
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+#define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos) /*!< 0x00000080 */
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+#define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk
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+#define DSI_TCCR1_HSRD_TOCNT8_Pos (8U)
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+#define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos) /*!< 0x00000100 */
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+#define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk
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+#define DSI_TCCR1_HSRD_TOCNT9_Pos (9U)
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+#define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos) /*!< 0x00000200 */
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+#define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk
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+#define DSI_TCCR1_HSRD_TOCNT10_Pos (10U)
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+#define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos) /*!< 0x00000400 */
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+#define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk
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+#define DSI_TCCR1_HSRD_TOCNT11_Pos (11U)
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+#define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos) /*!< 0x00000800 */
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+#define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk
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+#define DSI_TCCR1_HSRD_TOCNT12_Pos (12U)
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+#define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos) /*!< 0x00001000 */
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+#define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk
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+#define DSI_TCCR1_HSRD_TOCNT13_Pos (13U)
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+#define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos) /*!< 0x00002000 */
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+#define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk
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+#define DSI_TCCR1_HSRD_TOCNT14_Pos (14U)
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+#define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos) /*!< 0x00004000 */
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+#define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk
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+#define DSI_TCCR1_HSRD_TOCNT15_Pos (15U)
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+#define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos) /*!< 0x00008000 */
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+#define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk
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+
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+/******************* Bit definition for DSI_TCCR2 register **************/
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+#define DSI_TCCR2_LPRD_TOCNT_Pos (0U)
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+#define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos) /*!< 0x0000FFFF */
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+#define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk /*!< Low-Power Read Timeout Counter */
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+#define DSI_TCCR2_LPRD_TOCNT0_Pos (0U)
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+#define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos) /*!< 0x00000001 */
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+#define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk
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+#define DSI_TCCR2_LPRD_TOCNT1_Pos (1U)
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+#define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos) /*!< 0x00000002 */
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+#define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk
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+#define DSI_TCCR2_LPRD_TOCNT2_Pos (2U)
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+#define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos) /*!< 0x00000004 */
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+#define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk
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+#define DSI_TCCR2_LPRD_TOCNT3_Pos (3U)
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+#define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos) /*!< 0x00000008 */
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+#define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk
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+#define DSI_TCCR2_LPRD_TOCNT4_Pos (4U)
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+#define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos) /*!< 0x00000010 */
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+#define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk
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+#define DSI_TCCR2_LPRD_TOCNT5_Pos (5U)
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+#define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos) /*!< 0x00000020 */
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+#define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk
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+#define DSI_TCCR2_LPRD_TOCNT6_Pos (6U)
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+#define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos) /*!< 0x00000040 */
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+#define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk
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+#define DSI_TCCR2_LPRD_TOCNT7_Pos (7U)
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+#define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos) /*!< 0x00000080 */
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+#define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk
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+#define DSI_TCCR2_LPRD_TOCNT8_Pos (8U)
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+#define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos) /*!< 0x00000100 */
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+#define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk
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+#define DSI_TCCR2_LPRD_TOCNT9_Pos (9U)
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+#define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos) /*!< 0x00000200 */
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+#define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk
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+#define DSI_TCCR2_LPRD_TOCNT10_Pos (10U)
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+#define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos) /*!< 0x00000400 */
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+#define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk
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+#define DSI_TCCR2_LPRD_TOCNT11_Pos (11U)
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+#define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos) /*!< 0x00000800 */
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+#define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk
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+#define DSI_TCCR2_LPRD_TOCNT12_Pos (12U)
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+#define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos) /*!< 0x00001000 */
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+#define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk
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+#define DSI_TCCR2_LPRD_TOCNT13_Pos (13U)
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+#define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos) /*!< 0x00002000 */
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+#define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk
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+#define DSI_TCCR2_LPRD_TOCNT14_Pos (14U)
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+#define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos) /*!< 0x00004000 */
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+#define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk
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+#define DSI_TCCR2_LPRD_TOCNT15_Pos (15U)
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+#define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos) /*!< 0x00008000 */
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+#define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk
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+
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+/******************* Bit definition for DSI_TCCR3 register **************/
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+#define DSI_TCCR3_HSWR_TOCNT_Pos (0U)
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+#define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos) /*!< 0x0000FFFF */
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+#define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk /*!< High-Speed Write Timeout Counter */
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+#define DSI_TCCR3_HSWR_TOCNT0_Pos (0U)
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+#define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos) /*!< 0x00000001 */
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+#define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk
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+#define DSI_TCCR3_HSWR_TOCNT1_Pos (1U)
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+#define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos) /*!< 0x00000002 */
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+#define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk
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+#define DSI_TCCR3_HSWR_TOCNT2_Pos (2U)
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+#define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos) /*!< 0x00000004 */
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+#define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk
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+#define DSI_TCCR3_HSWR_TOCNT3_Pos (3U)
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+#define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos) /*!< 0x00000008 */
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+#define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk
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+#define DSI_TCCR3_HSWR_TOCNT4_Pos (4U)
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+#define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos) /*!< 0x00000010 */
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+#define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk
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+#define DSI_TCCR3_HSWR_TOCNT5_Pos (5U)
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+#define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos) /*!< 0x00000020 */
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+#define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk
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+#define DSI_TCCR3_HSWR_TOCNT6_Pos (6U)
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+#define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos) /*!< 0x00000040 */
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+#define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk
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+#define DSI_TCCR3_HSWR_TOCNT7_Pos (7U)
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+#define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos) /*!< 0x00000080 */
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+#define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk
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+#define DSI_TCCR3_HSWR_TOCNT8_Pos (8U)
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+#define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos) /*!< 0x00000100 */
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+#define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk
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+#define DSI_TCCR3_HSWR_TOCNT9_Pos (9U)
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+#define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos) /*!< 0x00000200 */
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+#define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk
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+#define DSI_TCCR3_HSWR_TOCNT10_Pos (10U)
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+#define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos) /*!< 0x00000400 */
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+#define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk
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+#define DSI_TCCR3_HSWR_TOCNT11_Pos (11U)
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+#define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos) /*!< 0x00000800 */
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+#define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk
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+#define DSI_TCCR3_HSWR_TOCNT12_Pos (12U)
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+#define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos) /*!< 0x00001000 */
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+#define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk
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+#define DSI_TCCR3_HSWR_TOCNT13_Pos (13U)
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+#define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos) /*!< 0x00002000 */
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+#define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk
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+#define DSI_TCCR3_HSWR_TOCNT14_Pos (14U)
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+#define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos) /*!< 0x00004000 */
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+#define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk
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+#define DSI_TCCR3_HSWR_TOCNT15_Pos (15U)
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+#define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos) /*!< 0x00008000 */
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+#define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk
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+
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+#define DSI_TCCR3_PM_Pos (24U)
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+#define DSI_TCCR3_PM_Msk (0x1UL << DSI_TCCR3_PM_Pos) /*!< 0x01000000 */
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+#define DSI_TCCR3_PM DSI_TCCR3_PM_Msk /*!< Presp Mode */
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+
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+/******************* Bit definition for DSI_TCCR4 register **************/
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+#define DSI_TCCR4_LPWR_TOCNT_Pos (0U)
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+#define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos) /*!< 0x0000FFFF */
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+#define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk /*!< Low-Power Write Timeout Counter */
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+#define DSI_TCCR4_LPWR_TOCNT0_Pos (0U)
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+#define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos) /*!< 0x00000001 */
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+#define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk
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+#define DSI_TCCR4_LPWR_TOCNT1_Pos (1U)
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+#define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos) /*!< 0x00000002 */
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+#define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk
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+#define DSI_TCCR4_LPWR_TOCNT2_Pos (2U)
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+#define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos) /*!< 0x00000004 */
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+#define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk
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+#define DSI_TCCR4_LPWR_TOCNT3_Pos (3U)
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+#define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos) /*!< 0x00000008 */
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+#define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk
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+#define DSI_TCCR4_LPWR_TOCNT4_Pos (4U)
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+#define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos) /*!< 0x00000010 */
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+#define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk
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+#define DSI_TCCR4_LPWR_TOCNT5_Pos (5U)
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+#define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos) /*!< 0x00000020 */
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+#define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk
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+#define DSI_TCCR4_LPWR_TOCNT6_Pos (6U)
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+#define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos) /*!< 0x00000040 */
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+#define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk
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+#define DSI_TCCR4_LPWR_TOCNT7_Pos (7U)
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+#define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos) /*!< 0x00000080 */
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+#define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk
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+#define DSI_TCCR4_LPWR_TOCNT8_Pos (8U)
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+#define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos) /*!< 0x00000100 */
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+#define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk
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+#define DSI_TCCR4_LPWR_TOCNT9_Pos (9U)
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+#define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos) /*!< 0x00000200 */
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+#define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk
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+#define DSI_TCCR4_LPWR_TOCNT10_Pos (10U)
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+#define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos) /*!< 0x00000400 */
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+#define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk
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+#define DSI_TCCR4_LPWR_TOCNT11_Pos (11U)
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+#define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos) /*!< 0x00000800 */
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+#define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk
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+#define DSI_TCCR4_LPWR_TOCNT12_Pos (12U)
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+#define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos) /*!< 0x00001000 */
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+#define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk
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+#define DSI_TCCR4_LPWR_TOCNT13_Pos (13U)
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+#define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos) /*!< 0x00002000 */
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+#define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk
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+#define DSI_TCCR4_LPWR_TOCNT14_Pos (14U)
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+#define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos) /*!< 0x00004000 */
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+#define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk
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+#define DSI_TCCR4_LPWR_TOCNT15_Pos (15U)
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+#define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos) /*!< 0x00008000 */
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+#define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk
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+
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+/******************* Bit definition for DSI_TCCR5register **************/
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+#define DSI_TCCR5_BTA_TOCNT_Pos (0U)
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+#define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos) /*!< 0x0000FFFF */
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+#define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk /*!< Bus-Turn-Around Timeout Counter */
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+#define DSI_TCCR5_BTA_TOCNT0_Pos (0U)
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+#define DSI_TCCR5_BTA_TOCNT0_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos) /*!< 0x00000001 */
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+#define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk
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+#define DSI_TCCR5_BTA_TOCNT1_Pos (1U)
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+#define DSI_TCCR5_BTA_TOCNT1_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos) /*!< 0x00000002 */
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+#define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk
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+#define DSI_TCCR5_BTA_TOCNT2_Pos (2U)
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+#define DSI_TCCR5_BTA_TOCNT2_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos) /*!< 0x00000004 */
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+#define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk
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+#define DSI_TCCR5_BTA_TOCNT3_Pos (3U)
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+#define DSI_TCCR5_BTA_TOCNT3_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos) /*!< 0x00000008 */
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+#define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk
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+#define DSI_TCCR5_BTA_TOCNT4_Pos (4U)
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+#define DSI_TCCR5_BTA_TOCNT4_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos) /*!< 0x00000010 */
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+#define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk
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+#define DSI_TCCR5_BTA_TOCNT5_Pos (5U)
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+#define DSI_TCCR5_BTA_TOCNT5_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos) /*!< 0x00000020 */
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+#define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk
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+#define DSI_TCCR5_BTA_TOCNT6_Pos (6U)
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+#define DSI_TCCR5_BTA_TOCNT6_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos) /*!< 0x00000040 */
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+#define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk
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+#define DSI_TCCR5_BTA_TOCNT7_Pos (7U)
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+#define DSI_TCCR5_BTA_TOCNT7_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos) /*!< 0x00000080 */
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+#define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk
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+#define DSI_TCCR5_BTA_TOCNT8_Pos (8U)
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+#define DSI_TCCR5_BTA_TOCNT8_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos) /*!< 0x00000100 */
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+#define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk
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+#define DSI_TCCR5_BTA_TOCNT9_Pos (9U)
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+#define DSI_TCCR5_BTA_TOCNT9_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos) /*!< 0x00000200 */
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+#define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk
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+#define DSI_TCCR5_BTA_TOCNT10_Pos (10U)
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+#define DSI_TCCR5_BTA_TOCNT10_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos) /*!< 0x00000400 */
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+#define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk
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+#define DSI_TCCR5_BTA_TOCNT11_Pos (11U)
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+#define DSI_TCCR5_BTA_TOCNT11_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos) /*!< 0x00000800 */
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+#define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk
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+#define DSI_TCCR5_BTA_TOCNT12_Pos (12U)
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+#define DSI_TCCR5_BTA_TOCNT12_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos) /*!< 0x00001000 */
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+#define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk
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+#define DSI_TCCR5_BTA_TOCNT13_Pos (13U)
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+#define DSI_TCCR5_BTA_TOCNT13_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos) /*!< 0x00002000 */
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+#define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk
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+#define DSI_TCCR5_BTA_TOCNT14_Pos (14U)
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+#define DSI_TCCR5_BTA_TOCNT14_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos) /*!< 0x00004000 */
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+#define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk
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+#define DSI_TCCR5_BTA_TOCNT15_Pos (15U)
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+#define DSI_TCCR5_BTA_TOCNT15_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos) /*!< 0x00008000 */
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+#define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
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+
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+/******************* Bit definition for DSI_TDCR register ***************/
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+#define DSI_TDCR_3DM 0x00000003U /*!< 3D Mode */
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+#define DSI_TDCR_3DM0 0x00000001U
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+#define DSI_TDCR_3DM1 0x00000002U
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+
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+#define DSI_TDCR_3DF 0x0000000CU /*!< 3D Format */
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+#define DSI_TDCR_3DF0 0x00000004U
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+#define DSI_TDCR_3DF1 0x00000008U
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+
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+#define DSI_TDCR_SVS_Pos (4U)
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+#define DSI_TDCR_SVS_Msk (0x1UL << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */
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+#define DSI_TDCR_SVS DSI_TDCR_SVS_Msk /*!< Second VSYNC */
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+#define DSI_TDCR_RF_Pos (5U)
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+#define DSI_TDCR_RF_Msk (0x1UL << DSI_TDCR_RF_Pos) /*!< 0x00000020 */
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+#define DSI_TDCR_RF DSI_TDCR_RF_Msk /*!< Right First */
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+#define DSI_TDCR_S3DC_Pos (16U)
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+#define DSI_TDCR_S3DC_Msk (0x1UL << DSI_TDCR_S3DC_Pos) /*!< 0x00010000 */
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+#define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk /*!< Send 3D Control */
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+
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+/******************* Bit definition for DSI_CLCR register ***************/
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+#define DSI_CLCR_DPCC_Pos (0U)
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+#define DSI_CLCR_DPCC_Msk (0x1UL << DSI_CLCR_DPCC_Pos) /*!< 0x00000001 */
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+#define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk /*!< D-PHY Clock Control */
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+#define DSI_CLCR_ACR_Pos (1U)
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+#define DSI_CLCR_ACR_Msk (0x1UL << DSI_CLCR_ACR_Pos) /*!< 0x00000002 */
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+#define DSI_CLCR_ACR DSI_CLCR_ACR_Msk /*!< Automatic Clocklane Control */
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+
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+/******************* Bit definition for DSI_CLTCR register **************/
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+#define DSI_CLTCR_LP2HS_TIME_Pos (0U)
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+#define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos) /*!< 0x000003FF */
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+#define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk /*!< Low-Power to High-Speed Time */
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+#define DSI_CLTCR_LP2HS_TIME0_Pos (0U)
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+#define DSI_CLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos) /*!< 0x00000001 */
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+#define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk
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+#define DSI_CLTCR_LP2HS_TIME1_Pos (1U)
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+#define DSI_CLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos) /*!< 0x00000002 */
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+#define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk
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+#define DSI_CLTCR_LP2HS_TIME2_Pos (2U)
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+#define DSI_CLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos) /*!< 0x00000004 */
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+#define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk
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+#define DSI_CLTCR_LP2HS_TIME3_Pos (3U)
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+#define DSI_CLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos) /*!< 0x00000008 */
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+#define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk
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+#define DSI_CLTCR_LP2HS_TIME4_Pos (4U)
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+#define DSI_CLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos) /*!< 0x00000010 */
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+#define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk
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+#define DSI_CLTCR_LP2HS_TIME5_Pos (5U)
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+#define DSI_CLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos) /*!< 0x00000020 */
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+#define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk
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+#define DSI_CLTCR_LP2HS_TIME6_Pos (6U)
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+#define DSI_CLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos) /*!< 0x00000040 */
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+#define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk
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+#define DSI_CLTCR_LP2HS_TIME7_Pos (7U)
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+#define DSI_CLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos) /*!< 0x00000080 */
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+#define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk
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+#define DSI_CLTCR_LP2HS_TIME8_Pos (8U)
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+#define DSI_CLTCR_LP2HS_TIME8_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos) /*!< 0x00000100 */
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+#define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk
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+#define DSI_CLTCR_LP2HS_TIME9_Pos (9U)
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+#define DSI_CLTCR_LP2HS_TIME9_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos) /*!< 0x00000200 */
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+#define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk
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+
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+#define DSI_CLTCR_HS2LP_TIME_Pos (16U)
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+#define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos) /*!< 0x03FF0000 */
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+#define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk /*!< High-Speed to Low-Power Time */
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+#define DSI_CLTCR_HS2LP_TIME0_Pos (16U)
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+#define DSI_CLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos) /*!< 0x00010000 */
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+#define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk
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+#define DSI_CLTCR_HS2LP_TIME1_Pos (17U)
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+#define DSI_CLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos) /*!< 0x00020000 */
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+#define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk
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+#define DSI_CLTCR_HS2LP_TIME2_Pos (18U)
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+#define DSI_CLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos) /*!< 0x00040000 */
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+#define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk
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+#define DSI_CLTCR_HS2LP_TIME3_Pos (19U)
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+#define DSI_CLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos) /*!< 0x00080000 */
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+#define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk
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+#define DSI_CLTCR_HS2LP_TIME4_Pos (20U)
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+#define DSI_CLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos) /*!< 0x00100000 */
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+#define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk
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+#define DSI_CLTCR_HS2LP_TIME5_Pos (21U)
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+#define DSI_CLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos) /*!< 0x00200000 */
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+#define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk
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+#define DSI_CLTCR_HS2LP_TIME6_Pos (22U)
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+#define DSI_CLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos) /*!< 0x00400000 */
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+#define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk
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+#define DSI_CLTCR_HS2LP_TIME7_Pos (23U)
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+#define DSI_CLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos) /*!< 0x00800000 */
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|
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+#define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk
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+#define DSI_CLTCR_HS2LP_TIME8_Pos (24U)
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+#define DSI_CLTCR_HS2LP_TIME8_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos) /*!< 0x01000000 */
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+#define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk
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+#define DSI_CLTCR_HS2LP_TIME9_Pos (25U)
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+#define DSI_CLTCR_HS2LP_TIME9_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos) /*!< 0x02000000 */
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+#define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk
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+
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+/******************* Bit definition for DSI_DLTCR register **************/
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+#define DSI_DLTCR_MRD_TIME_Pos (0U)
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+#define DSI_DLTCR_MRD_TIME_Msk (0x7FFFUL << DSI_DLTCR_MRD_TIME_Pos) /*!< 0x00007FFF */
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+#define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk /*!< Maximum Read Time */
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+#define DSI_DLTCR_MRD_TIME0_Pos (0U)
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+#define DSI_DLTCR_MRD_TIME0_Msk (0x1UL << DSI_DLTCR_MRD_TIME0_Pos) /*!< 0x00000001 */
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+#define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk
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+#define DSI_DLTCR_MRD_TIME1_Pos (1U)
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+#define DSI_DLTCR_MRD_TIME1_Msk (0x1UL << DSI_DLTCR_MRD_TIME1_Pos) /*!< 0x00000002 */
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+#define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk
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+#define DSI_DLTCR_MRD_TIME2_Pos (2U)
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+#define DSI_DLTCR_MRD_TIME2_Msk (0x1UL << DSI_DLTCR_MRD_TIME2_Pos) /*!< 0x00000004 */
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+#define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk
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+#define DSI_DLTCR_MRD_TIME3_Pos (3U)
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+#define DSI_DLTCR_MRD_TIME3_Msk (0x1UL << DSI_DLTCR_MRD_TIME3_Pos) /*!< 0x00000008 */
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+#define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk
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+#define DSI_DLTCR_MRD_TIME4_Pos (4U)
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+#define DSI_DLTCR_MRD_TIME4_Msk (0x1UL << DSI_DLTCR_MRD_TIME4_Pos) /*!< 0x00000010 */
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+#define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk
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+#define DSI_DLTCR_MRD_TIME5_Pos (5U)
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+#define DSI_DLTCR_MRD_TIME5_Msk (0x1UL << DSI_DLTCR_MRD_TIME5_Pos) /*!< 0x00000020 */
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+#define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk
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+#define DSI_DLTCR_MRD_TIME6_Pos (6U)
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+#define DSI_DLTCR_MRD_TIME6_Msk (0x1UL << DSI_DLTCR_MRD_TIME6_Pos) /*!< 0x00000040 */
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+#define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk
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+#define DSI_DLTCR_MRD_TIME7_Pos (7U)
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+#define DSI_DLTCR_MRD_TIME7_Msk (0x1UL << DSI_DLTCR_MRD_TIME7_Pos) /*!< 0x00000080 */
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+#define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk
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+#define DSI_DLTCR_MRD_TIME8_Pos (8U)
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+#define DSI_DLTCR_MRD_TIME8_Msk (0x1UL << DSI_DLTCR_MRD_TIME8_Pos) /*!< 0x00000100 */
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+#define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk
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+#define DSI_DLTCR_MRD_TIME9_Pos (9U)
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+#define DSI_DLTCR_MRD_TIME9_Msk (0x1UL << DSI_DLTCR_MRD_TIME9_Pos) /*!< 0x00000200 */
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+#define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk
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+#define DSI_DLTCR_MRD_TIME10_Pos (10U)
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+#define DSI_DLTCR_MRD_TIME10_Msk (0x1UL << DSI_DLTCR_MRD_TIME10_Pos) /*!< 0x00000400 */
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+#define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk
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+#define DSI_DLTCR_MRD_TIME11_Pos (11U)
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+#define DSI_DLTCR_MRD_TIME11_Msk (0x1UL << DSI_DLTCR_MRD_TIME11_Pos) /*!< 0x00000800 */
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+#define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk
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+#define DSI_DLTCR_MRD_TIME12_Pos (12U)
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+#define DSI_DLTCR_MRD_TIME12_Msk (0x1UL << DSI_DLTCR_MRD_TIME12_Pos) /*!< 0x00001000 */
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+#define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk
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+#define DSI_DLTCR_MRD_TIME13_Pos (13U)
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+#define DSI_DLTCR_MRD_TIME13_Msk (0x1UL << DSI_DLTCR_MRD_TIME13_Pos) /*!< 0x00002000 */
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+#define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk
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+#define DSI_DLTCR_MRD_TIME14_Pos (14U)
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+#define DSI_DLTCR_MRD_TIME14_Msk (0x1UL << DSI_DLTCR_MRD_TIME14_Pos) /*!< 0x00004000 */
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+#define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk
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+
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+#define DSI_DLTCR_LP2HS_TIME_Pos (16U)
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+#define DSI_DLTCR_LP2HS_TIME_Msk (0xFFUL << DSI_DLTCR_LP2HS_TIME_Pos) /*!< 0x00FF0000 */
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+#define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk /*!< Low-Power To High-Speed Time */
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+#define DSI_DLTCR_LP2HS_TIME0_Pos (16U)
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+#define DSI_DLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos) /*!< 0x00010000 */
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+#define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk
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+#define DSI_DLTCR_LP2HS_TIME1_Pos (17U)
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+#define DSI_DLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos) /*!< 0x00020000 */
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+#define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk
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+#define DSI_DLTCR_LP2HS_TIME2_Pos (18U)
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+#define DSI_DLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos) /*!< 0x00040000 */
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+#define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk
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+#define DSI_DLTCR_LP2HS_TIME3_Pos (19U)
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|
+#define DSI_DLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos) /*!< 0x00080000 */
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|
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+#define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk
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+#define DSI_DLTCR_LP2HS_TIME4_Pos (20U)
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+#define DSI_DLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos) /*!< 0x00100000 */
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+#define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk
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+#define DSI_DLTCR_LP2HS_TIME5_Pos (21U)
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+#define DSI_DLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos) /*!< 0x00200000 */
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|
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+#define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk
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|
+#define DSI_DLTCR_LP2HS_TIME6_Pos (22U)
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+#define DSI_DLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos) /*!< 0x00400000 */
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|
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+#define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk
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|
+#define DSI_DLTCR_LP2HS_TIME7_Pos (23U)
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+#define DSI_DLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos) /*!< 0x00800000 */
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+#define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk
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+
|
|
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+#define DSI_DLTCR_HS2LP_TIME_Pos (24U)
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+#define DSI_DLTCR_HS2LP_TIME_Msk (0xFFUL << DSI_DLTCR_HS2LP_TIME_Pos) /*!< 0xFF000000 */
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+#define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk /*!< High-Speed To Low-Power Time */
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+#define DSI_DLTCR_HS2LP_TIME0_Pos (24U)
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+#define DSI_DLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos) /*!< 0x01000000 */
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+#define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk
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+#define DSI_DLTCR_HS2LP_TIME1_Pos (25U)
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+#define DSI_DLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos) /*!< 0x02000000 */
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+#define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk
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+#define DSI_DLTCR_HS2LP_TIME2_Pos (26U)
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+#define DSI_DLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos) /*!< 0x04000000 */
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+#define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk
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+#define DSI_DLTCR_HS2LP_TIME3_Pos (27U)
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+#define DSI_DLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos) /*!< 0x08000000 */
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+#define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk
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+#define DSI_DLTCR_HS2LP_TIME4_Pos (28U)
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+#define DSI_DLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos) /*!< 0x10000000 */
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+#define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk
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+#define DSI_DLTCR_HS2LP_TIME5_Pos (29U)
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+#define DSI_DLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos) /*!< 0x20000000 */
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+#define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk
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+#define DSI_DLTCR_HS2LP_TIME6_Pos (30U)
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+#define DSI_DLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos) /*!< 0x40000000 */
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+#define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk
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+#define DSI_DLTCR_HS2LP_TIME7_Pos (31U)
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+#define DSI_DLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos) /*!< 0x80000000 */
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+#define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk
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+
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|
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+/******************* Bit definition for DSI_PCTLRregister **************/
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|
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+#define DSI_PCTLR_DEN_Pos (1U)
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+#define DSI_PCTLR_DEN_Msk (0x1UL << DSI_PCTLR_DEN_Pos) /*!< 0x00000002 */
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+#define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk /*!< Digital Enable */
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+#define DSI_PCTLR_CKE_Pos (2U)
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+#define DSI_PCTLR_CKE_Msk (0x1UL << DSI_PCTLR_CKE_Pos) /*!< 0x00000004 */
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+#define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk /*!< Clock Enable */
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+
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|
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+/******************* Bit definition for DSI_PCONFR register *************/
|
|
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+#define DSI_PCONFR_NL_Pos (0U)
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+#define DSI_PCONFR_NL_Msk (0x3UL << DSI_PCONFR_NL_Pos) /*!< 0x00000003 */
|
|
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+#define DSI_PCONFR_NL DSI_PCONFR_NL_Msk /*!< Number of Lanes */
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+#define DSI_PCONFR_NL0_Pos (0U)
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+#define DSI_PCONFR_NL0_Msk (0x1UL << DSI_PCONFR_NL0_Pos) /*!< 0x00000001 */
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+#define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk
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+#define DSI_PCONFR_NL1_Pos (1U)
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+#define DSI_PCONFR_NL1_Msk (0x1UL << DSI_PCONFR_NL1_Pos) /*!< 0x00000002 */
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|
|
+#define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk
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|
|
+
|
|
|
+#define DSI_PCONFR_SW_TIME_Pos (8U)
|
|
|
+#define DSI_PCONFR_SW_TIME_Msk (0xFFUL << DSI_PCONFR_SW_TIME_Pos) /*!< 0x0000FF00 */
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|
|
+#define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk /*!< Stop Wait Time */
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|
|
+#define DSI_PCONFR_SW_TIME0_Pos (8U)
|
|
|
+#define DSI_PCONFR_SW_TIME0_Msk (0x1UL << DSI_PCONFR_SW_TIME0_Pos) /*!< 0x00000100 */
|
|
|
+#define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk
|
|
|
+#define DSI_PCONFR_SW_TIME1_Pos (9U)
|
|
|
+#define DSI_PCONFR_SW_TIME1_Msk (0x1UL << DSI_PCONFR_SW_TIME1_Pos) /*!< 0x00000200 */
|
|
|
+#define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk
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+#define DSI_PCONFR_SW_TIME2_Pos (10U)
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+#define DSI_PCONFR_SW_TIME2_Msk (0x1UL << DSI_PCONFR_SW_TIME2_Pos) /*!< 0x00000400 */
|
|
|
+#define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk
|
|
|
+#define DSI_PCONFR_SW_TIME3_Pos (11U)
|
|
|
+#define DSI_PCONFR_SW_TIME3_Msk (0x1UL << DSI_PCONFR_SW_TIME3_Pos) /*!< 0x00000800 */
|
|
|
+#define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk
|
|
|
+#define DSI_PCONFR_SW_TIME4_Pos (12U)
|
|
|
+#define DSI_PCONFR_SW_TIME4_Msk (0x1UL << DSI_PCONFR_SW_TIME4_Pos) /*!< 0x00001000 */
|
|
|
+#define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk
|
|
|
+#define DSI_PCONFR_SW_TIME5_Pos (13U)
|
|
|
+#define DSI_PCONFR_SW_TIME5_Msk (0x1UL << DSI_PCONFR_SW_TIME5_Pos) /*!< 0x00002000 */
|
|
|
+#define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk
|
|
|
+#define DSI_PCONFR_SW_TIME6_Pos (14U)
|
|
|
+#define DSI_PCONFR_SW_TIME6_Msk (0x1UL << DSI_PCONFR_SW_TIME6_Pos) /*!< 0x00004000 */
|
|
|
+#define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk
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|
|
+#define DSI_PCONFR_SW_TIME7_Pos (15U)
|
|
|
+#define DSI_PCONFR_SW_TIME7_Msk (0x1UL << DSI_PCONFR_SW_TIME7_Pos) /*!< 0x00008000 */
|
|
|
+#define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk
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|
|
+
|
|
|
+/******************* Bit definition for DSI_PUCR register ***************/
|
|
|
+#define DSI_PUCR_URCL_Pos (0U)
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|
+#define DSI_PUCR_URCL_Msk (0x1UL << DSI_PUCR_URCL_Pos) /*!< 0x00000001 */
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|
|
+#define DSI_PUCR_URCL DSI_PUCR_URCL_Msk /*!< ULPS Request on Clock Lane */
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|
|
+#define DSI_PUCR_UECL_Pos (1U)
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|
|
+#define DSI_PUCR_UECL_Msk (0x1UL << DSI_PUCR_UECL_Pos) /*!< 0x00000002 */
|
|
|
+#define DSI_PUCR_UECL DSI_PUCR_UECL_Msk /*!< ULPS Exit on Clock Lane */
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|
|
+#define DSI_PUCR_URDL_Pos (2U)
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|
|
+#define DSI_PUCR_URDL_Msk (0x1UL << DSI_PUCR_URDL_Pos) /*!< 0x00000004 */
|
|
|
+#define DSI_PUCR_URDL DSI_PUCR_URDL_Msk /*!< ULPS Request on Data Lane */
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|
+#define DSI_PUCR_UEDL_Pos (3U)
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|
+#define DSI_PUCR_UEDL_Msk (0x1UL << DSI_PUCR_UEDL_Pos) /*!< 0x00000008 */
|
|
|
+#define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk /*!< ULPS Exit on Data Lane */
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|
+
|
|
|
+/******************* Bit definition for DSI_PTTCRregister **************/
|
|
|
+#define DSI_PTTCR_TX_TRIG_Pos (0U)
|
|
|
+#define DSI_PTTCR_TX_TRIG_Msk (0xFUL << DSI_PTTCR_TX_TRIG_Pos) /*!< 0x0000000F */
|
|
|
+#define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk /*!< Transmission Trigger */
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|
|
+#define DSI_PTTCR_TX_TRIG0_Pos (0U)
|
|
|
+#define DSI_PTTCR_TX_TRIG0_Msk (0x1UL << DSI_PTTCR_TX_TRIG0_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk
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|
+#define DSI_PTTCR_TX_TRIG1_Pos (1U)
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|
+#define DSI_PTTCR_TX_TRIG1_Msk (0x1UL << DSI_PTTCR_TX_TRIG1_Pos) /*!< 0x00000002 */
|
|
|
+#define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk
|
|
|
+#define DSI_PTTCR_TX_TRIG2_Pos (2U)
|
|
|
+#define DSI_PTTCR_TX_TRIG2_Msk (0x1UL << DSI_PTTCR_TX_TRIG2_Pos) /*!< 0x00000004 */
|
|
|
+#define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk
|
|
|
+#define DSI_PTTCR_TX_TRIG3_Pos (3U)
|
|
|
+#define DSI_PTTCR_TX_TRIG3_Msk (0x1UL << DSI_PTTCR_TX_TRIG3_Pos) /*!< 0x00000008 */
|
|
|
+#define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk
|
|
|
+
|
|
|
+/******************* Bit definition for DSI_PSR register ****************/
|
|
|
+#define DSI_PSR_PD_Pos (1U)
|
|
|
+#define DSI_PSR_PD_Msk (0x1UL << DSI_PSR_PD_Pos) /*!< 0x00000002 */
|
|
|
+#define DSI_PSR_PD DSI_PSR_PD_Msk /*!< PHY Direction */
|
|
|
+#define DSI_PSR_PSSC_Pos (2U)
|
|
|
+#define DSI_PSR_PSSC_Msk (0x1UL << DSI_PSR_PSSC_Pos) /*!< 0x00000004 */
|
|
|
+#define DSI_PSR_PSSC DSI_PSR_PSSC_Msk /*!< PHY Stop State Clock lane */
|
|
|
+#define DSI_PSR_UANC_Pos (3U)
|
|
|
+#define DSI_PSR_UANC_Msk (0x1UL << DSI_PSR_UANC_Pos) /*!< 0x00000008 */
|
|
|
+#define DSI_PSR_UANC DSI_PSR_UANC_Msk /*!< ULPS Active Not Clock lane */
|
|
|
+#define DSI_PSR_PSS0_Pos (4U)
|
|
|
+#define DSI_PSR_PSS0_Msk (0x1UL << DSI_PSR_PSS0_Pos) /*!< 0x00000010 */
|
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+#define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk /*!< PHY Stop State lane 0 */
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+#define DSI_PSR_UAN0_Pos (5U)
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+#define DSI_PSR_UAN0_Msk (0x1UL << DSI_PSR_UAN0_Pos) /*!< 0x00000020 */
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+#define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk /*!< ULPS Active Not lane 0 */
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+#define DSI_PSR_RUE0_Pos (6U)
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+#define DSI_PSR_RUE0_Msk (0x1UL << DSI_PSR_RUE0_Pos) /*!< 0x00000040 */
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+#define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk /*!< RX ULPS Escape lane 0 */
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+#define DSI_PSR_PSS1_Pos (7U)
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+#define DSI_PSR_PSS1_Msk (0x1UL << DSI_PSR_PSS1_Pos) /*!< 0x00000080 */
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+#define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk /*!< PHY Stop State lane 1 */
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+#define DSI_PSR_UAN1_Pos (8U)
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+#define DSI_PSR_UAN1_Msk (0x1UL << DSI_PSR_UAN1_Pos) /*!< 0x00000100 */
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+#define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk /*!< ULPS Active Not lane 1 */
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+
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+/******************* Bit definition for DSI_ISR0 register ***************/
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+#define DSI_ISR0_AE0_Pos (0U)
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+#define DSI_ISR0_AE0_Msk (0x1UL << DSI_ISR0_AE0_Pos) /*!< 0x00000001 */
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+#define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk /*!< Acknowledge Error 0 */
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+#define DSI_ISR0_AE1_Pos (1U)
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+#define DSI_ISR0_AE1_Msk (0x1UL << DSI_ISR0_AE1_Pos) /*!< 0x00000002 */
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+#define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk /*!< Acknowledge Error 1 */
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+#define DSI_ISR0_AE2_Pos (2U)
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+#define DSI_ISR0_AE2_Msk (0x1UL << DSI_ISR0_AE2_Pos) /*!< 0x00000004 */
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+#define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk /*!< Acknowledge Error 2 */
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+#define DSI_ISR0_AE3_Pos (3U)
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+#define DSI_ISR0_AE3_Msk (0x1UL << DSI_ISR0_AE3_Pos) /*!< 0x00000008 */
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+#define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk /*!< Acknowledge Error 3 */
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+#define DSI_ISR0_AE4_Pos (4U)
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+#define DSI_ISR0_AE4_Msk (0x1UL << DSI_ISR0_AE4_Pos) /*!< 0x00000010 */
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+#define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk /*!< Acknowledge Error 4 */
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+#define DSI_ISR0_AE5_Pos (5U)
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+#define DSI_ISR0_AE5_Msk (0x1UL << DSI_ISR0_AE5_Pos) /*!< 0x00000020 */
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+#define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk /*!< Acknowledge Error 5 */
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+#define DSI_ISR0_AE6_Pos (6U)
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+#define DSI_ISR0_AE6_Msk (0x1UL << DSI_ISR0_AE6_Pos) /*!< 0x00000040 */
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+#define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk /*!< Acknowledge Error 6 */
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+#define DSI_ISR0_AE7_Pos (7U)
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+#define DSI_ISR0_AE7_Msk (0x1UL << DSI_ISR0_AE7_Pos) /*!< 0x00000080 */
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+#define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk /*!< Acknowledge Error 7 */
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+#define DSI_ISR0_AE8_Pos (8U)
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+#define DSI_ISR0_AE8_Msk (0x1UL << DSI_ISR0_AE8_Pos) /*!< 0x00000100 */
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+#define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk /*!< Acknowledge Error 8 */
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+#define DSI_ISR0_AE9_Pos (9U)
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+#define DSI_ISR0_AE9_Msk (0x1UL << DSI_ISR0_AE9_Pos) /*!< 0x00000200 */
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+#define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk /*!< Acknowledge Error 9 */
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+#define DSI_ISR0_AE10_Pos (10U)
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+#define DSI_ISR0_AE10_Msk (0x1UL << DSI_ISR0_AE10_Pos) /*!< 0x00000400 */
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+#define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk /*!< Acknowledge Error 10 */
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+#define DSI_ISR0_AE11_Pos (11U)
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+#define DSI_ISR0_AE11_Msk (0x1UL << DSI_ISR0_AE11_Pos) /*!< 0x00000800 */
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+#define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk /*!< Acknowledge Error 11 */
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+#define DSI_ISR0_AE12_Pos (12U)
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+#define DSI_ISR0_AE12_Msk (0x1UL << DSI_ISR0_AE12_Pos) /*!< 0x00001000 */
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+#define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk /*!< Acknowledge Error 12 */
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+#define DSI_ISR0_AE13_Pos (13U)
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+#define DSI_ISR0_AE13_Msk (0x1UL << DSI_ISR0_AE13_Pos) /*!< 0x00002000 */
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+#define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk /*!< Acknowledge Error 13 */
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+#define DSI_ISR0_AE14_Pos (14U)
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+#define DSI_ISR0_AE14_Msk (0x1UL << DSI_ISR0_AE14_Pos) /*!< 0x00004000 */
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+#define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk /*!< Acknowledge Error 14 */
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+#define DSI_ISR0_AE15_Pos (15U)
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+#define DSI_ISR0_AE15_Msk (0x1UL << DSI_ISR0_AE15_Pos) /*!< 0x00008000 */
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+#define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk /*!< Acknowledge Error 15 */
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+#define DSI_ISR0_PE0_Pos (16U)
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+#define DSI_ISR0_PE0_Msk (0x1UL << DSI_ISR0_PE0_Pos) /*!< 0x00010000 */
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+#define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk /*!< PHY Error 0 */
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+#define DSI_ISR0_PE1_Pos (17U)
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+#define DSI_ISR0_PE1_Msk (0x1UL << DSI_ISR0_PE1_Pos) /*!< 0x00020000 */
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+#define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk /*!< PHY Error 1 */
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+#define DSI_ISR0_PE2_Pos (18U)
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+#define DSI_ISR0_PE2_Msk (0x1UL << DSI_ISR0_PE2_Pos) /*!< 0x00040000 */
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+#define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk /*!< PHY Error 2 */
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+#define DSI_ISR0_PE3_Pos (19U)
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+#define DSI_ISR0_PE3_Msk (0x1UL << DSI_ISR0_PE3_Pos) /*!< 0x00080000 */
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+#define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk /*!< PHY Error 3 */
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+#define DSI_ISR0_PE4_Pos (20U)
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+#define DSI_ISR0_PE4_Msk (0x1UL << DSI_ISR0_PE4_Pos) /*!< 0x00100000 */
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+#define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk /*!< PHY Error 4 */
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+
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+/******************* Bit definition for DSI_ISR1 register ***************/
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+#define DSI_ISR1_TOHSTX_Pos (0U)
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+#define DSI_ISR1_TOHSTX_Msk (0x1UL << DSI_ISR1_TOHSTX_Pos) /*!< 0x00000001 */
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+#define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk /*!< Timeout High-Speed Transmission */
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+#define DSI_ISR1_TOLPRX_Pos (1U)
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+#define DSI_ISR1_TOLPRX_Msk (0x1UL << DSI_ISR1_TOLPRX_Pos) /*!< 0x00000002 */
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+#define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk /*!< Timeout Low-Power Reception */
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+#define DSI_ISR1_ECCSE_Pos (2U)
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+#define DSI_ISR1_ECCSE_Msk (0x1UL << DSI_ISR1_ECCSE_Pos) /*!< 0x00000004 */
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+#define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk /*!< ECC Single-bit Error */
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+#define DSI_ISR1_ECCME_Pos (3U)
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+#define DSI_ISR1_ECCME_Msk (0x1UL << DSI_ISR1_ECCME_Pos) /*!< 0x00000008 */
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+#define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk /*!< ECC Multi-bit Error */
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+#define DSI_ISR1_CRCE_Pos (4U)
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+#define DSI_ISR1_CRCE_Msk (0x1UL << DSI_ISR1_CRCE_Pos) /*!< 0x00000010 */
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+#define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk /*!< CRC Error */
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+#define DSI_ISR1_PSE_Pos (5U)
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+#define DSI_ISR1_PSE_Msk (0x1UL << DSI_ISR1_PSE_Pos) /*!< 0x00000020 */
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+#define DSI_ISR1_PSE DSI_ISR1_PSE_Msk /*!< Packet Size Error */
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+#define DSI_ISR1_EOTPE_Pos (6U)
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+#define DSI_ISR1_EOTPE_Msk (0x1UL << DSI_ISR1_EOTPE_Pos) /*!< 0x00000040 */
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+#define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk /*!< EoTp Error */
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+#define DSI_ISR1_LPWRE_Pos (7U)
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+#define DSI_ISR1_LPWRE_Msk (0x1UL << DSI_ISR1_LPWRE_Pos) /*!< 0x00000080 */
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+#define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk /*!< LTDC Payload Write Error */
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+#define DSI_ISR1_GCWRE_Pos (8U)
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+#define DSI_ISR1_GCWRE_Msk (0x1UL << DSI_ISR1_GCWRE_Pos) /*!< 0x00000100 */
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+#define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk /*!< Generic Command Write Error */
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+#define DSI_ISR1_GPWRE_Pos (9U)
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+#define DSI_ISR1_GPWRE_Msk (0x1UL << DSI_ISR1_GPWRE_Pos) /*!< 0x00000200 */
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+#define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk /*!< Generic Payload Write Error */
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+#define DSI_ISR1_GPTXE_Pos (10U)
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+#define DSI_ISR1_GPTXE_Msk (0x1UL << DSI_ISR1_GPTXE_Pos) /*!< 0x00000400 */
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+#define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk /*!< Generic Payload Transmit Error */
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+#define DSI_ISR1_GPRDE_Pos (11U)
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+#define DSI_ISR1_GPRDE_Msk (0x1UL << DSI_ISR1_GPRDE_Pos) /*!< 0x00000800 */
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+#define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk /*!< Generic Payload Read Error */
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+#define DSI_ISR1_GPRXE_Pos (12U)
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+#define DSI_ISR1_GPRXE_Msk (0x1UL << DSI_ISR1_GPRXE_Pos) /*!< 0x00001000 */
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+#define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk /*!< Generic Payload Receive Error */
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+
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+/******************* Bit definition for DSI_IER0 register ***************/
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+#define DSI_IER0_AE0IE_Pos (0U)
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+#define DSI_IER0_AE0IE_Msk (0x1UL << DSI_IER0_AE0IE_Pos) /*!< 0x00000001 */
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+#define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk /*!< Acknowledge Error 0 Interrupt Enable */
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+#define DSI_IER0_AE1IE_Pos (1U)
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+#define DSI_IER0_AE1IE_Msk (0x1UL << DSI_IER0_AE1IE_Pos) /*!< 0x00000002 */
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+#define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk /*!< Acknowledge Error 1 Interrupt Enable */
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+#define DSI_IER0_AE2IE_Pos (2U)
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+#define DSI_IER0_AE2IE_Msk (0x1UL << DSI_IER0_AE2IE_Pos) /*!< 0x00000004 */
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+#define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk /*!< Acknowledge Error 2 Interrupt Enable */
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+#define DSI_IER0_AE3IE_Pos (3U)
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+#define DSI_IER0_AE3IE_Msk (0x1UL << DSI_IER0_AE3IE_Pos) /*!< 0x00000008 */
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+#define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk /*!< Acknowledge Error 3 Interrupt Enable */
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+#define DSI_IER0_AE4IE_Pos (4U)
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+#define DSI_IER0_AE4IE_Msk (0x1UL << DSI_IER0_AE4IE_Pos) /*!< 0x00000010 */
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+#define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk /*!< Acknowledge Error 4 Interrupt Enable */
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+#define DSI_IER0_AE5IE_Pos (5U)
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+#define DSI_IER0_AE5IE_Msk (0x1UL << DSI_IER0_AE5IE_Pos) /*!< 0x00000020 */
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+#define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk /*!< Acknowledge Error 5 Interrupt Enable */
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+#define DSI_IER0_AE6IE_Pos (6U)
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+#define DSI_IER0_AE6IE_Msk (0x1UL << DSI_IER0_AE6IE_Pos) /*!< 0x00000040 */
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+#define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk /*!< Acknowledge Error 6 Interrupt Enable */
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+#define DSI_IER0_AE7IE_Pos (7U)
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+#define DSI_IER0_AE7IE_Msk (0x1UL << DSI_IER0_AE7IE_Pos) /*!< 0x00000080 */
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+#define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk /*!< Acknowledge Error 7 Interrupt Enable */
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+#define DSI_IER0_AE8IE_Pos (8U)
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+#define DSI_IER0_AE8IE_Msk (0x1UL << DSI_IER0_AE8IE_Pos) /*!< 0x00000100 */
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+#define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk /*!< Acknowledge Error 8 Interrupt Enable */
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+#define DSI_IER0_AE9IE_Pos (9U)
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+#define DSI_IER0_AE9IE_Msk (0x1UL << DSI_IER0_AE9IE_Pos) /*!< 0x00000200 */
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+#define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk /*!< Acknowledge Error 9 Interrupt Enable */
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+#define DSI_IER0_AE10IE_Pos (10U)
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+#define DSI_IER0_AE10IE_Msk (0x1UL << DSI_IER0_AE10IE_Pos) /*!< 0x00000400 */
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+#define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk /*!< Acknowledge Error 10 Interrupt Enable */
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+#define DSI_IER0_AE11IE_Pos (11U)
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+#define DSI_IER0_AE11IE_Msk (0x1UL << DSI_IER0_AE11IE_Pos) /*!< 0x00000800 */
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+#define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk /*!< Acknowledge Error 11 Interrupt Enable */
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+#define DSI_IER0_AE12IE_Pos (12U)
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+#define DSI_IER0_AE12IE_Msk (0x1UL << DSI_IER0_AE12IE_Pos) /*!< 0x00001000 */
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+#define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk /*!< Acknowledge Error 12 Interrupt Enable */
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+#define DSI_IER0_AE13IE_Pos (13U)
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+#define DSI_IER0_AE13IE_Msk (0x1UL << DSI_IER0_AE13IE_Pos) /*!< 0x00002000 */
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+#define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk /*!< Acknowledge Error 13 Interrupt Enable */
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+#define DSI_IER0_AE14IE_Pos (14U)
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+#define DSI_IER0_AE14IE_Msk (0x1UL << DSI_IER0_AE14IE_Pos) /*!< 0x00004000 */
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+#define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk /*!< Acknowledge Error 14 Interrupt Enable */
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+#define DSI_IER0_AE15IE_Pos (15U)
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+#define DSI_IER0_AE15IE_Msk (0x1UL << DSI_IER0_AE15IE_Pos) /*!< 0x00008000 */
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+#define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk /*!< Acknowledge Error 15 Interrupt Enable */
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+#define DSI_IER0_PE0IE_Pos (16U)
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+#define DSI_IER0_PE0IE_Msk (0x1UL << DSI_IER0_PE0IE_Pos) /*!< 0x00010000 */
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+#define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk /*!< PHY Error 0 Interrupt Enable */
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+#define DSI_IER0_PE1IE_Pos (17U)
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+#define DSI_IER0_PE1IE_Msk (0x1UL << DSI_IER0_PE1IE_Pos) /*!< 0x00020000 */
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+#define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk /*!< PHY Error 1 Interrupt Enable */
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+#define DSI_IER0_PE2IE_Pos (18U)
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+#define DSI_IER0_PE2IE_Msk (0x1UL << DSI_IER0_PE2IE_Pos) /*!< 0x00040000 */
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+#define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk /*!< PHY Error 2 Interrupt Enable */
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+#define DSI_IER0_PE3IE_Pos (19U)
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+#define DSI_IER0_PE3IE_Msk (0x1UL << DSI_IER0_PE3IE_Pos) /*!< 0x00080000 */
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+#define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk /*!< PHY Error 3 Interrupt Enable */
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+#define DSI_IER0_PE4IE_Pos (20U)
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+#define DSI_IER0_PE4IE_Msk (0x1UL << DSI_IER0_PE4IE_Pos) /*!< 0x00100000 */
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+#define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk /*!< PHY Error 4 Interrupt Enable */
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+
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+/******************* Bit definition for DSI_IER1 register ***************/
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+#define DSI_IER1_TOHSTXIE_Pos (0U)
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+#define DSI_IER1_TOHSTXIE_Msk (0x1UL << DSI_IER1_TOHSTXIE_Pos) /*!< 0x00000001 */
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+#define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk /*!< Timeout High-Speed Transmission Interrupt Enable */
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+#define DSI_IER1_TOLPRXIE_Pos (1U)
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+#define DSI_IER1_TOLPRXIE_Msk (0x1UL << DSI_IER1_TOLPRXIE_Pos) /*!< 0x00000002 */
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+#define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk /*!< Timeout Low-Power Reception Interrupt Enable */
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+#define DSI_IER1_ECCSEIE_Pos (2U)
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+#define DSI_IER1_ECCSEIE_Msk (0x1UL << DSI_IER1_ECCSEIE_Pos) /*!< 0x00000004 */
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+#define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk /*!< ECC Single-bit Error Interrupt Enable */
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+#define DSI_IER1_ECCMEIE_Pos (3U)
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+#define DSI_IER1_ECCMEIE_Msk (0x1UL << DSI_IER1_ECCMEIE_Pos) /*!< 0x00000008 */
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+#define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk /*!< ECC Multi-bit Error Interrupt Enable */
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+#define DSI_IER1_CRCEIE_Pos (4U)
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+#define DSI_IER1_CRCEIE_Msk (0x1UL << DSI_IER1_CRCEIE_Pos) /*!< 0x00000010 */
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+#define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk /*!< CRC Error Interrupt Enable */
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+#define DSI_IER1_PSEIE_Pos (5U)
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+#define DSI_IER1_PSEIE_Msk (0x1UL << DSI_IER1_PSEIE_Pos) /*!< 0x00000020 */
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+#define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk /*!< Packet Size Error Interrupt Enable */
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+#define DSI_IER1_EOTPEIE_Pos (6U)
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+#define DSI_IER1_EOTPEIE_Msk (0x1UL << DSI_IER1_EOTPEIE_Pos) /*!< 0x00000040 */
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+#define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk /*!< EoTp Error Interrupt Enable */
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+#define DSI_IER1_LPWREIE_Pos (7U)
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+#define DSI_IER1_LPWREIE_Msk (0x1UL << DSI_IER1_LPWREIE_Pos) /*!< 0x00000080 */
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+#define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk /*!< LTDC Payload Write Error Interrupt Enable */
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+#define DSI_IER1_GCWREIE_Pos (8U)
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+#define DSI_IER1_GCWREIE_Msk (0x1UL << DSI_IER1_GCWREIE_Pos) /*!< 0x00000100 */
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+#define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk /*!< Generic Command Write Error Interrupt Enable */
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+#define DSI_IER1_GPWREIE_Pos (9U)
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+#define DSI_IER1_GPWREIE_Msk (0x1UL << DSI_IER1_GPWREIE_Pos) /*!< 0x00000200 */
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+#define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk /*!< Generic Payload Write Error Interrupt Enable */
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+#define DSI_IER1_GPTXEIE_Pos (10U)
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+#define DSI_IER1_GPTXEIE_Msk (0x1UL << DSI_IER1_GPTXEIE_Pos) /*!< 0x00000400 */
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+#define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk /*!< Generic Payload Transmit Error Interrupt Enable */
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+#define DSI_IER1_GPRDEIE_Pos (11U)
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+#define DSI_IER1_GPRDEIE_Msk (0x1UL << DSI_IER1_GPRDEIE_Pos) /*!< 0x00000800 */
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+#define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk /*!< Generic Payload Read Error Interrupt Enable */
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+#define DSI_IER1_GPRXEIE_Pos (12U)
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+#define DSI_IER1_GPRXEIE_Msk (0x1UL << DSI_IER1_GPRXEIE_Pos) /*!< 0x00001000 */
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+#define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk /*!< Generic Payload Receive Error Interrupt Enable */
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+
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+/******************* Bit definition for DSI_FIR0 register ***************/
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+#define DSI_FIR0_FAE0_Pos (0U)
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+#define DSI_FIR0_FAE0_Msk (0x1UL << DSI_FIR0_FAE0_Pos) /*!< 0x00000001 */
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+#define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk /*!< Force Acknowledge Error 0 */
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+#define DSI_FIR0_FAE1_Pos (1U)
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+#define DSI_FIR0_FAE1_Msk (0x1UL << DSI_FIR0_FAE1_Pos) /*!< 0x00000002 */
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+#define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk /*!< Force Acknowledge Error 1 */
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+#define DSI_FIR0_FAE2_Pos (2U)
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+#define DSI_FIR0_FAE2_Msk (0x1UL << DSI_FIR0_FAE2_Pos) /*!< 0x00000004 */
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+#define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk /*!< Force Acknowledge Error 2 */
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+#define DSI_FIR0_FAE3_Pos (3U)
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+#define DSI_FIR0_FAE3_Msk (0x1UL << DSI_FIR0_FAE3_Pos) /*!< 0x00000008 */
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+#define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk /*!< Force Acknowledge Error 3 */
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+#define DSI_FIR0_FAE4_Pos (4U)
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+#define DSI_FIR0_FAE4_Msk (0x1UL << DSI_FIR0_FAE4_Pos) /*!< 0x00000010 */
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+#define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk /*!< Force Acknowledge Error 4 */
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+#define DSI_FIR0_FAE5_Pos (5U)
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+#define DSI_FIR0_FAE5_Msk (0x1UL << DSI_FIR0_FAE5_Pos) /*!< 0x00000020 */
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+#define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk /*!< Force Acknowledge Error 5 */
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+#define DSI_FIR0_FAE6_Pos (6U)
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+#define DSI_FIR0_FAE6_Msk (0x1UL << DSI_FIR0_FAE6_Pos) /*!< 0x00000040 */
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+#define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk /*!< Force Acknowledge Error 6 */
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+#define DSI_FIR0_FAE7_Pos (7U)
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+#define DSI_FIR0_FAE7_Msk (0x1UL << DSI_FIR0_FAE7_Pos) /*!< 0x00000080 */
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+#define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk /*!< Force Acknowledge Error 7 */
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+#define DSI_FIR0_FAE8_Pos (8U)
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+#define DSI_FIR0_FAE8_Msk (0x1UL << DSI_FIR0_FAE8_Pos) /*!< 0x00000100 */
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+#define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk /*!< Force Acknowledge Error 8 */
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+#define DSI_FIR0_FAE9_Pos (9U)
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+#define DSI_FIR0_FAE9_Msk (0x1UL << DSI_FIR0_FAE9_Pos) /*!< 0x00000200 */
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+#define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk /*!< Force Acknowledge Error 9 */
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+#define DSI_FIR0_FAE10_Pos (10U)
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+#define DSI_FIR0_FAE10_Msk (0x1UL << DSI_FIR0_FAE10_Pos) /*!< 0x00000400 */
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+#define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk /*!< Force Acknowledge Error 10 */
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+#define DSI_FIR0_FAE11_Pos (11U)
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+#define DSI_FIR0_FAE11_Msk (0x1UL << DSI_FIR0_FAE11_Pos) /*!< 0x00000800 */
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+#define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk /*!< Force Acknowledge Error 11 */
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+#define DSI_FIR0_FAE12_Pos (12U)
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+#define DSI_FIR0_FAE12_Msk (0x1UL << DSI_FIR0_FAE12_Pos) /*!< 0x00001000 */
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+#define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk /*!< Force Acknowledge Error 12 */
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+#define DSI_FIR0_FAE13_Pos (13U)
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+#define DSI_FIR0_FAE13_Msk (0x1UL << DSI_FIR0_FAE13_Pos) /*!< 0x00002000 */
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+#define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk /*!< Force Acknowledge Error 13 */
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+#define DSI_FIR0_FAE14_Pos (14U)
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+#define DSI_FIR0_FAE14_Msk (0x1UL << DSI_FIR0_FAE14_Pos) /*!< 0x00004000 */
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+#define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk /*!< Force Acknowledge Error 14 */
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+#define DSI_FIR0_FAE15_Pos (15U)
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+#define DSI_FIR0_FAE15_Msk (0x1UL << DSI_FIR0_FAE15_Pos) /*!< 0x00008000 */
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+#define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk /*!< Force Acknowledge Error 15 */
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+#define DSI_FIR0_FPE0_Pos (16U)
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+#define DSI_FIR0_FPE0_Msk (0x1UL << DSI_FIR0_FPE0_Pos) /*!< 0x00010000 */
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+#define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk /*!< Force PHY Error 0 */
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+#define DSI_FIR0_FPE1_Pos (17U)
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+#define DSI_FIR0_FPE1_Msk (0x1UL << DSI_FIR0_FPE1_Pos) /*!< 0x00020000 */
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+#define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk /*!< Force PHY Error 1 */
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+#define DSI_FIR0_FPE2_Pos (18U)
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+#define DSI_FIR0_FPE2_Msk (0x1UL << DSI_FIR0_FPE2_Pos) /*!< 0x00040000 */
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+#define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk /*!< Force PHY Error 2 */
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+#define DSI_FIR0_FPE3_Pos (19U)
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+#define DSI_FIR0_FPE3_Msk (0x1UL << DSI_FIR0_FPE3_Pos) /*!< 0x00080000 */
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+#define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk /*!< Force PHY Error 3 */
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+#define DSI_FIR0_FPE4_Pos (20U)
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+#define DSI_FIR0_FPE4_Msk (0x1UL << DSI_FIR0_FPE4_Pos) /*!< 0x00100000 */
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+#define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk /*!< Force PHY Error 4 */
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+
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+/******************* Bit definition for DSI_FIR1 register ***************/
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+#define DSI_FIR1_FTOHSTX_Pos (0U)
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+#define DSI_FIR1_FTOHSTX_Msk (0x1UL << DSI_FIR1_FTOHSTX_Pos) /*!< 0x00000001 */
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+#define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk /*!< Force Timeout High-Speed Transmission */
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+#define DSI_FIR1_FTOLPRX_Pos (1U)
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+#define DSI_FIR1_FTOLPRX_Msk (0x1UL << DSI_FIR1_FTOLPRX_Pos) /*!< 0x00000002 */
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+#define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk /*!< Force Timeout Low-Power Reception */
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+#define DSI_FIR1_FECCSE_Pos (2U)
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+#define DSI_FIR1_FECCSE_Msk (0x1UL << DSI_FIR1_FECCSE_Pos) /*!< 0x00000004 */
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+#define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk /*!< Force ECC Single-bit Error */
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+#define DSI_FIR1_FECCME_Pos (3U)
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+#define DSI_FIR1_FECCME_Msk (0x1UL << DSI_FIR1_FECCME_Pos) /*!< 0x00000008 */
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+#define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk /*!< Force ECC Multi-bit Error */
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+#define DSI_FIR1_FCRCE_Pos (4U)
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+#define DSI_FIR1_FCRCE_Msk (0x1UL << DSI_FIR1_FCRCE_Pos) /*!< 0x00000010 */
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+#define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk /*!< Force CRC Error */
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+#define DSI_FIR1_FPSE_Pos (5U)
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+#define DSI_FIR1_FPSE_Msk (0x1UL << DSI_FIR1_FPSE_Pos) /*!< 0x00000020 */
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+#define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk /*!< Force Packet Size Error */
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+#define DSI_FIR1_FEOTPE_Pos (6U)
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+#define DSI_FIR1_FEOTPE_Msk (0x1UL << DSI_FIR1_FEOTPE_Pos) /*!< 0x00000040 */
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+#define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk /*!< Force EoTp Error */
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+#define DSI_FIR1_FLPWRE_Pos (7U)
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+#define DSI_FIR1_FLPWRE_Msk (0x1UL << DSI_FIR1_FLPWRE_Pos) /*!< 0x00000080 */
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+#define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk /*!< Force LTDC Payload Write Error */
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+#define DSI_FIR1_FGCWRE_Pos (8U)
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+#define DSI_FIR1_FGCWRE_Msk (0x1UL << DSI_FIR1_FGCWRE_Pos) /*!< 0x00000100 */
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+#define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk /*!< Force Generic Command Write Error */
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+#define DSI_FIR1_FGPWRE_Pos (9U)
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+#define DSI_FIR1_FGPWRE_Msk (0x1UL << DSI_FIR1_FGPWRE_Pos) /*!< 0x00000200 */
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+#define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk /*!< Force Generic Payload Write Error */
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+#define DSI_FIR1_FGPTXE_Pos (10U)
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+#define DSI_FIR1_FGPTXE_Msk (0x1UL << DSI_FIR1_FGPTXE_Pos) /*!< 0x00000400 */
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+#define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk /*!< Force Generic Payload Transmit Error */
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+#define DSI_FIR1_FGPRDE_Pos (11U)
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+#define DSI_FIR1_FGPRDE_Msk (0x1UL << DSI_FIR1_FGPRDE_Pos) /*!< 0x00000800 */
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+#define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk /*!< Force Generic Payload Read Error */
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+#define DSI_FIR1_FGPRXE_Pos (12U)
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+#define DSI_FIR1_FGPRXE_Msk (0x1UL << DSI_FIR1_FGPRXE_Pos) /*!< 0x00001000 */
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+#define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk /*!< Force Generic Payload Receive Error */
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+
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+/******************* Bit definition for DSI_VSCR register ***************/
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+#define DSI_VSCR_EN_Pos (0U)
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+#define DSI_VSCR_EN_Msk (0x1UL << DSI_VSCR_EN_Pos) /*!< 0x00000001 */
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+#define DSI_VSCR_EN DSI_VSCR_EN_Msk /*!< Enable */
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+#define DSI_VSCR_UR_Pos (8U)
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+#define DSI_VSCR_UR_Msk (0x1UL << DSI_VSCR_UR_Pos) /*!< 0x00000100 */
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+#define DSI_VSCR_UR DSI_VSCR_UR_Msk /*!< Update Register */
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+
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+/******************* Bit definition for DSI_LCVCIDR register ************/
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+#define DSI_LCVCIDR_VCID_Pos (0U)
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+#define DSI_LCVCIDR_VCID_Msk (0x3UL << DSI_LCVCIDR_VCID_Pos) /*!< 0x00000003 */
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+#define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk /*!< Virtual Channel ID */
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+#define DSI_LCVCIDR_VCID0_Pos (0U)
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+#define DSI_LCVCIDR_VCID0_Msk (0x1UL << DSI_LCVCIDR_VCID0_Pos) /*!< 0x00000001 */
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+#define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk
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+#define DSI_LCVCIDR_VCID1_Pos (1U)
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+#define DSI_LCVCIDR_VCID1_Msk (0x1UL << DSI_LCVCIDR_VCID1_Pos) /*!< 0x00000002 */
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+#define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk
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+
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+/******************* Bit definition for DSI_LCCCR register **************/
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+#define DSI_LCCCR_COLC_Pos (0U)
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+#define DSI_LCCCR_COLC_Msk (0xFUL << DSI_LCCCR_COLC_Pos) /*!< 0x0000000F */
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+#define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk /*!< Color Coding */
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+#define DSI_LCCCR_COLC0_Pos (0U)
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+#define DSI_LCCCR_COLC0_Msk (0x1UL << DSI_LCCCR_COLC0_Pos) /*!< 0x00000001 */
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+#define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk
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+#define DSI_LCCCR_COLC1_Pos (1U)
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+#define DSI_LCCCR_COLC1_Msk (0x1UL << DSI_LCCCR_COLC1_Pos) /*!< 0x00000002 */
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+#define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk
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+#define DSI_LCCCR_COLC2_Pos (2U)
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+#define DSI_LCCCR_COLC2_Msk (0x1UL << DSI_LCCCR_COLC2_Pos) /*!< 0x00000004 */
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+#define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk
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+#define DSI_LCCCR_COLC3_Pos (3U)
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+#define DSI_LCCCR_COLC3_Msk (0x1UL << DSI_LCCCR_COLC3_Pos) /*!< 0x00000008 */
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+#define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk
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+
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+#define DSI_LCCCR_LPE_Pos (8U)
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+#define DSI_LCCCR_LPE_Msk (0x1UL << DSI_LCCCR_LPE_Pos) /*!< 0x00000100 */
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+#define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk /*!< Loosely Packed Enable */
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+
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+/******************* Bit definition for DSI_LPMCCR register *************/
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+#define DSI_LPMCCR_VLPSIZE_Pos (0U)
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+#define DSI_LPMCCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos) /*!< 0x000000FF */
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+#define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
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+#define DSI_LPMCCR_VLPSIZE0_Pos (0U)
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+#define DSI_LPMCCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos) /*!< 0x00000001 */
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+#define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk
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+#define DSI_LPMCCR_VLPSIZE1_Pos (1U)
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+#define DSI_LPMCCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos) /*!< 0x00000002 */
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+#define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk
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+#define DSI_LPMCCR_VLPSIZE2_Pos (2U)
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+#define DSI_LPMCCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos) /*!< 0x00000004 */
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+#define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk
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+#define DSI_LPMCCR_VLPSIZE3_Pos (3U)
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+#define DSI_LPMCCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos) /*!< 0x00000008 */
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+#define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk
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+#define DSI_LPMCCR_VLPSIZE4_Pos (4U)
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+#define DSI_LPMCCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos) /*!< 0x00000010 */
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+#define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk
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+#define DSI_LPMCCR_VLPSIZE5_Pos (5U)
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+#define DSI_LPMCCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos) /*!< 0x00000020 */
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+#define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk
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+#define DSI_LPMCCR_VLPSIZE6_Pos (6U)
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+#define DSI_LPMCCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos) /*!< 0x00000040 */
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+#define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk
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+#define DSI_LPMCCR_VLPSIZE7_Pos (7U)
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+#define DSI_LPMCCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos) /*!< 0x00000080 */
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+#define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk
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+
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+#define DSI_LPMCCR_LPSIZE_Pos (16U)
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+#define DSI_LPMCCR_LPSIZE_Msk (0xFFUL << DSI_LPMCCR_LPSIZE_Pos) /*!< 0x00FF0000 */
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+#define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk /*!< Largest Packet Size */
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+#define DSI_LPMCCR_LPSIZE0_Pos (16U)
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+#define DSI_LPMCCR_LPSIZE0_Msk (0x1UL << DSI_LPMCCR_LPSIZE0_Pos) /*!< 0x00010000 */
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+#define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk
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+#define DSI_LPMCCR_LPSIZE1_Pos (17U)
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+#define DSI_LPMCCR_LPSIZE1_Msk (0x1UL << DSI_LPMCCR_LPSIZE1_Pos) /*!< 0x00020000 */
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+#define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk
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+#define DSI_LPMCCR_LPSIZE2_Pos (18U)
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+#define DSI_LPMCCR_LPSIZE2_Msk (0x1UL << DSI_LPMCCR_LPSIZE2_Pos) /*!< 0x00040000 */
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+#define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk
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+#define DSI_LPMCCR_LPSIZE3_Pos (19U)
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+#define DSI_LPMCCR_LPSIZE3_Msk (0x1UL << DSI_LPMCCR_LPSIZE3_Pos) /*!< 0x00080000 */
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+#define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk
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+#define DSI_LPMCCR_LPSIZE4_Pos (20U)
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+#define DSI_LPMCCR_LPSIZE4_Msk (0x1UL << DSI_LPMCCR_LPSIZE4_Pos) /*!< 0x00100000 */
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+#define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk
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+#define DSI_LPMCCR_LPSIZE5_Pos (21U)
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+#define DSI_LPMCCR_LPSIZE5_Msk (0x1UL << DSI_LPMCCR_LPSIZE5_Pos) /*!< 0x00200000 */
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+#define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk
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+#define DSI_LPMCCR_LPSIZE6_Pos (22U)
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+#define DSI_LPMCCR_LPSIZE6_Msk (0x1UL << DSI_LPMCCR_LPSIZE6_Pos) /*!< 0x00400000 */
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+#define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk
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+#define DSI_LPMCCR_LPSIZE7_Pos (23U)
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+#define DSI_LPMCCR_LPSIZE7_Msk (0x1UL << DSI_LPMCCR_LPSIZE7_Pos) /*!< 0x00800000 */
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+#define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk
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+
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+/******************* Bit definition for DSI_VMCCR register **************/
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+#define DSI_VMCCR_VMT_Pos (0U)
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+#define DSI_VMCCR_VMT_Msk (0x3UL << DSI_VMCCR_VMT_Pos) /*!< 0x00000003 */
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+#define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk /*!< Video Mode Type */
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+#define DSI_VMCCR_VMT0_Pos (0U)
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+#define DSI_VMCCR_VMT0_Msk (0x1UL << DSI_VMCCR_VMT0_Pos) /*!< 0x00000001 */
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+#define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk
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+#define DSI_VMCCR_VMT1_Pos (1U)
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+#define DSI_VMCCR_VMT1_Msk (0x1UL << DSI_VMCCR_VMT1_Pos) /*!< 0x00000002 */
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+#define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk
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+
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+#define DSI_VMCCR_LPVSAE_Pos (8U)
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+#define DSI_VMCCR_LPVSAE_Msk (0x1UL << DSI_VMCCR_LPVSAE_Pos) /*!< 0x00000100 */
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+#define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk /*!< Low-power Vertical Sync time Enable */
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+#define DSI_VMCCR_LPVBPE_Pos (9U)
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+#define DSI_VMCCR_LPVBPE_Msk (0x1UL << DSI_VMCCR_LPVBPE_Pos) /*!< 0x00000200 */
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+#define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk /*!< Low-power Vertical Back-porch Enable */
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+#define DSI_VMCCR_LPVFPE_Pos (10U)
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+#define DSI_VMCCR_LPVFPE_Msk (0x1UL << DSI_VMCCR_LPVFPE_Pos) /*!< 0x00000400 */
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+#define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
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+#define DSI_VMCCR_LPVAE_Pos (11U)
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+#define DSI_VMCCR_LPVAE_Msk (0x1UL << DSI_VMCCR_LPVAE_Pos) /*!< 0x00000800 */
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+#define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk /*!< Low-power Vertical Active Enable */
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+#define DSI_VMCCR_LPHBPE_Pos (12U)
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+#define DSI_VMCCR_LPHBPE_Msk (0x1UL << DSI_VMCCR_LPHBPE_Pos) /*!< 0x00001000 */
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+#define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk /*!< Low-power Horizontal Back-porch Enable */
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+#define DSI_VMCCR_LPHFE_Pos (13U)
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+#define DSI_VMCCR_LPHFE_Msk (0x1UL << DSI_VMCCR_LPHFE_Pos) /*!< 0x00002000 */
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+#define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk /*!< Low-power Horizontal Front-porch Enable */
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+#define DSI_VMCCR_FBTAAE_Pos (14U)
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+#define DSI_VMCCR_FBTAAE_Msk (0x1UL << DSI_VMCCR_FBTAAE_Pos) /*!< 0x00004000 */
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+#define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk /*!< Frame BTA Acknowledge Enable */
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+#define DSI_VMCCR_LPCE_Pos (15U)
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+#define DSI_VMCCR_LPCE_Msk (0x1UL << DSI_VMCCR_LPCE_Pos) /*!< 0x00008000 */
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+#define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk /*!< Low-power Command Enable */
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+
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+/******************* Bit definition for DSI_VPCCR register **************/
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+#define DSI_VPCCR_VPSIZE_Pos (0U)
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+#define DSI_VPCCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos) /*!< 0x00003FFF */
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+#define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk /*!< Video Packet Size */
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+#define DSI_VPCCR_VPSIZE0_Pos (0U)
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+#define DSI_VPCCR_VPSIZE0_Msk (0x1UL << DSI_VPCCR_VPSIZE0_Pos) /*!< 0x00000001 */
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+#define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk
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+#define DSI_VPCCR_VPSIZE1_Pos (1U)
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+#define DSI_VPCCR_VPSIZE1_Msk (0x1UL << DSI_VPCCR_VPSIZE1_Pos) /*!< 0x00000002 */
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+#define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk
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+#define DSI_VPCCR_VPSIZE2_Pos (2U)
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+#define DSI_VPCCR_VPSIZE2_Msk (0x1UL << DSI_VPCCR_VPSIZE2_Pos) /*!< 0x00000004 */
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+#define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk
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+#define DSI_VPCCR_VPSIZE3_Pos (3U)
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+#define DSI_VPCCR_VPSIZE3_Msk (0x1UL << DSI_VPCCR_VPSIZE3_Pos) /*!< 0x00000008 */
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+#define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk
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+#define DSI_VPCCR_VPSIZE4_Pos (4U)
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+#define DSI_VPCCR_VPSIZE4_Msk (0x1UL << DSI_VPCCR_VPSIZE4_Pos) /*!< 0x00000010 */
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+#define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk
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+#define DSI_VPCCR_VPSIZE5_Pos (5U)
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+#define DSI_VPCCR_VPSIZE5_Msk (0x1UL << DSI_VPCCR_VPSIZE5_Pos) /*!< 0x00000020 */
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+#define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk
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+#define DSI_VPCCR_VPSIZE6_Pos (6U)
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+#define DSI_VPCCR_VPSIZE6_Msk (0x1UL << DSI_VPCCR_VPSIZE6_Pos) /*!< 0x00000040 */
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+#define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk
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+#define DSI_VPCCR_VPSIZE7_Pos (7U)
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+#define DSI_VPCCR_VPSIZE7_Msk (0x1UL << DSI_VPCCR_VPSIZE7_Pos) /*!< 0x00000080 */
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+#define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk
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+#define DSI_VPCCR_VPSIZE8_Pos (8U)
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+#define DSI_VPCCR_VPSIZE8_Msk (0x1UL << DSI_VPCCR_VPSIZE8_Pos) /*!< 0x00000100 */
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+#define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk
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+#define DSI_VPCCR_VPSIZE9_Pos (9U)
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+#define DSI_VPCCR_VPSIZE9_Msk (0x1UL << DSI_VPCCR_VPSIZE9_Pos) /*!< 0x00000200 */
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+#define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk
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+#define DSI_VPCCR_VPSIZE10_Pos (10U)
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+#define DSI_VPCCR_VPSIZE10_Msk (0x1UL << DSI_VPCCR_VPSIZE10_Pos) /*!< 0x00000400 */
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+#define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk
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+#define DSI_VPCCR_VPSIZE11_Pos (11U)
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+#define DSI_VPCCR_VPSIZE11_Msk (0x1UL << DSI_VPCCR_VPSIZE11_Pos) /*!< 0x00000800 */
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+#define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk
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+#define DSI_VPCCR_VPSIZE12_Pos (12U)
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+#define DSI_VPCCR_VPSIZE12_Msk (0x1UL << DSI_VPCCR_VPSIZE12_Pos) /*!< 0x00001000 */
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+#define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk
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+#define DSI_VPCCR_VPSIZE13_Pos (13U)
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+#define DSI_VPCCR_VPSIZE13_Msk (0x1UL << DSI_VPCCR_VPSIZE13_Pos) /*!< 0x00002000 */
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+#define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk
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+
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+/******************* Bit definition for DSI_VCCCR register **************/
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+#define DSI_VCCCR_NUMC_Pos (0U)
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+#define DSI_VCCCR_NUMC_Msk (0x1FFFUL << DSI_VCCCR_NUMC_Pos) /*!< 0x00001FFF */
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+#define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk /*!< Number of Chunks */
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+#define DSI_VCCCR_NUMC0_Pos (0U)
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+#define DSI_VCCCR_NUMC0_Msk (0x1UL << DSI_VCCCR_NUMC0_Pos) /*!< 0x00000001 */
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+#define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk
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+#define DSI_VCCCR_NUMC1_Pos (1U)
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+#define DSI_VCCCR_NUMC1_Msk (0x1UL << DSI_VCCCR_NUMC1_Pos) /*!< 0x00000002 */
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+#define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk
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+#define DSI_VCCCR_NUMC2_Pos (2U)
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+#define DSI_VCCCR_NUMC2_Msk (0x1UL << DSI_VCCCR_NUMC2_Pos) /*!< 0x00000004 */
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+#define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk
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+#define DSI_VCCCR_NUMC3_Pos (3U)
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+#define DSI_VCCCR_NUMC3_Msk (0x1UL << DSI_VCCCR_NUMC3_Pos) /*!< 0x00000008 */
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+#define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk
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+#define DSI_VCCCR_NUMC4_Pos (4U)
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+#define DSI_VCCCR_NUMC4_Msk (0x1UL << DSI_VCCCR_NUMC4_Pos) /*!< 0x00000010 */
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+#define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk
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+#define DSI_VCCCR_NUMC5_Pos (5U)
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+#define DSI_VCCCR_NUMC5_Msk (0x1UL << DSI_VCCCR_NUMC5_Pos) /*!< 0x00000020 */
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+#define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk
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+#define DSI_VCCCR_NUMC6_Pos (6U)
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+#define DSI_VCCCR_NUMC6_Msk (0x1UL << DSI_VCCCR_NUMC6_Pos) /*!< 0x00000040 */
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+#define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk
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+#define DSI_VCCCR_NUMC7_Pos (7U)
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+#define DSI_VCCCR_NUMC7_Msk (0x1UL << DSI_VCCCR_NUMC7_Pos) /*!< 0x00000080 */
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+#define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk
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+#define DSI_VCCCR_NUMC8_Pos (8U)
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+#define DSI_VCCCR_NUMC8_Msk (0x1UL << DSI_VCCCR_NUMC8_Pos) /*!< 0x00000100 */
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|
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+#define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk
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|
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+#define DSI_VCCCR_NUMC9_Pos (9U)
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+#define DSI_VCCCR_NUMC9_Msk (0x1UL << DSI_VCCCR_NUMC9_Pos) /*!< 0x00000200 */
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+#define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk
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+#define DSI_VCCCR_NUMC10_Pos (10U)
|
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+#define DSI_VCCCR_NUMC10_Msk (0x1UL << DSI_VCCCR_NUMC10_Pos) /*!< 0x00000400 */
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|
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+#define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk
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+#define DSI_VCCCR_NUMC11_Pos (11U)
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+#define DSI_VCCCR_NUMC11_Msk (0x1UL << DSI_VCCCR_NUMC11_Pos) /*!< 0x00000800 */
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|
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+#define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk
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+#define DSI_VCCCR_NUMC12_Pos (12U)
|
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+#define DSI_VCCCR_NUMC12_Msk (0x1UL << DSI_VCCCR_NUMC12_Pos) /*!< 0x00001000 */
|
|
|
+#define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk
|
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+
|
|
|
+/******************* Bit definition for DSI_VNPCCR register *************/
|
|
|
+#define DSI_VNPCCR_NPSIZE_Pos (0U)
|
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|
+#define DSI_VNPCCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos) /*!< 0x00001FFF */
|
|
|
+#define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk /*!< Number of Chunks */
|
|
|
+#define DSI_VNPCCR_NPSIZE0_Pos (0U)
|
|
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+#define DSI_VNPCCR_NPSIZE0_Msk (0x1UL << DSI_VNPCCR_NPSIZE0_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk
|
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|
+#define DSI_VNPCCR_NPSIZE1_Pos (1U)
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+#define DSI_VNPCCR_NPSIZE1_Msk (0x1UL << DSI_VNPCCR_NPSIZE1_Pos) /*!< 0x00000002 */
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+#define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk
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|
+#define DSI_VNPCCR_NPSIZE2_Pos (2U)
|
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+#define DSI_VNPCCR_NPSIZE2_Msk (0x1UL << DSI_VNPCCR_NPSIZE2_Pos) /*!< 0x00000004 */
|
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+#define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk
|
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+#define DSI_VNPCCR_NPSIZE3_Pos (3U)
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+#define DSI_VNPCCR_NPSIZE3_Msk (0x1UL << DSI_VNPCCR_NPSIZE3_Pos) /*!< 0x00000008 */
|
|
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+#define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk
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+#define DSI_VNPCCR_NPSIZE4_Pos (4U)
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+#define DSI_VNPCCR_NPSIZE4_Msk (0x1UL << DSI_VNPCCR_NPSIZE4_Pos) /*!< 0x00000010 */
|
|
|
+#define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk
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|
+#define DSI_VNPCCR_NPSIZE5_Pos (5U)
|
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+#define DSI_VNPCCR_NPSIZE5_Msk (0x1UL << DSI_VNPCCR_NPSIZE5_Pos) /*!< 0x00000020 */
|
|
|
+#define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk
|
|
|
+#define DSI_VNPCCR_NPSIZE6_Pos (6U)
|
|
|
+#define DSI_VNPCCR_NPSIZE6_Msk (0x1UL << DSI_VNPCCR_NPSIZE6_Pos) /*!< 0x00000040 */
|
|
|
+#define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk
|
|
|
+#define DSI_VNPCCR_NPSIZE7_Pos (7U)
|
|
|
+#define DSI_VNPCCR_NPSIZE7_Msk (0x1UL << DSI_VNPCCR_NPSIZE7_Pos) /*!< 0x00000080 */
|
|
|
+#define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk
|
|
|
+#define DSI_VNPCCR_NPSIZE8_Pos (8U)
|
|
|
+#define DSI_VNPCCR_NPSIZE8_Msk (0x1UL << DSI_VNPCCR_NPSIZE8_Pos) /*!< 0x00000100 */
|
|
|
+#define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk
|
|
|
+#define DSI_VNPCCR_NPSIZE9_Pos (9U)
|
|
|
+#define DSI_VNPCCR_NPSIZE9_Msk (0x1UL << DSI_VNPCCR_NPSIZE9_Pos) /*!< 0x00000200 */
|
|
|
+#define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk
|
|
|
+#define DSI_VNPCCR_NPSIZE10_Pos (10U)
|
|
|
+#define DSI_VNPCCR_NPSIZE10_Msk (0x1UL << DSI_VNPCCR_NPSIZE10_Pos) /*!< 0x00000400 */
|
|
|
+#define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk
|
|
|
+#define DSI_VNPCCR_NPSIZE11_Pos (11U)
|
|
|
+#define DSI_VNPCCR_NPSIZE11_Msk (0x1UL << DSI_VNPCCR_NPSIZE11_Pos) /*!< 0x00000800 */
|
|
|
+#define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk
|
|
|
+#define DSI_VNPCCR_NPSIZE12_Pos (12U)
|
|
|
+#define DSI_VNPCCR_NPSIZE12_Msk (0x1UL << DSI_VNPCCR_NPSIZE12_Pos) /*!< 0x00001000 */
|
|
|
+#define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk
|
|
|
+
|
|
|
+/******************* Bit definition for DSI_VHSACCR register ************/
|
|
|
+#define DSI_VHSACCR_HSA_Pos (0U)
|
|
|
+#define DSI_VHSACCR_HSA_Msk (0xFFFUL << DSI_VHSACCR_HSA_Pos) /*!< 0x00000FFF */
|
|
|
+#define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk /*!< Horizontal Synchronism Active duration */
|
|
|
+#define DSI_VHSACCR_HSA0_Pos (0U)
|
|
|
+#define DSI_VHSACCR_HSA0_Msk (0x1UL << DSI_VHSACCR_HSA0_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk
|
|
|
+#define DSI_VHSACCR_HSA1_Pos (1U)
|
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+#define DSI_VHSACCR_HSA1_Msk (0x1UL << DSI_VHSACCR_HSA1_Pos) /*!< 0x00000002 */
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+#define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk
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+#define DSI_VHSACCR_HSA2_Pos (2U)
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+#define DSI_VHSACCR_HSA2_Msk (0x1UL << DSI_VHSACCR_HSA2_Pos) /*!< 0x00000004 */
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+#define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk
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+#define DSI_VHSACCR_HSA3_Pos (3U)
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+#define DSI_VHSACCR_HSA3_Msk (0x1UL << DSI_VHSACCR_HSA3_Pos) /*!< 0x00000008 */
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+#define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk
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+#define DSI_VHSACCR_HSA4_Pos (4U)
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+#define DSI_VHSACCR_HSA4_Msk (0x1UL << DSI_VHSACCR_HSA4_Pos) /*!< 0x00000010 */
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+#define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk
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+#define DSI_VHSACCR_HSA5_Pos (5U)
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+#define DSI_VHSACCR_HSA5_Msk (0x1UL << DSI_VHSACCR_HSA5_Pos) /*!< 0x00000020 */
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+#define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk
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+#define DSI_VHSACCR_HSA6_Pos (6U)
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+#define DSI_VHSACCR_HSA6_Msk (0x1UL << DSI_VHSACCR_HSA6_Pos) /*!< 0x00000040 */
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+#define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk
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+#define DSI_VHSACCR_HSA7_Pos (7U)
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+#define DSI_VHSACCR_HSA7_Msk (0x1UL << DSI_VHSACCR_HSA7_Pos) /*!< 0x00000080 */
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+#define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk
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+#define DSI_VHSACCR_HSA8_Pos (8U)
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+#define DSI_VHSACCR_HSA8_Msk (0x1UL << DSI_VHSACCR_HSA8_Pos) /*!< 0x00000100 */
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+#define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk
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+#define DSI_VHSACCR_HSA9_Pos (9U)
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+#define DSI_VHSACCR_HSA9_Msk (0x1UL << DSI_VHSACCR_HSA9_Pos) /*!< 0x00000200 */
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+#define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk
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+#define DSI_VHSACCR_HSA10_Pos (10U)
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+#define DSI_VHSACCR_HSA10_Msk (0x1UL << DSI_VHSACCR_HSA10_Pos) /*!< 0x00000400 */
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+#define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk
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+#define DSI_VHSACCR_HSA11_Pos (11U)
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+#define DSI_VHSACCR_HSA11_Msk (0x1UL << DSI_VHSACCR_HSA11_Pos) /*!< 0x00000800 */
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+#define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk
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+
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+/******************* Bit definition for DSI_VHBPCCR register ************/
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+#define DSI_VHBPCCR_HBP_Pos (0U)
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+#define DSI_VHBPCCR_HBP_Msk (0xFFFUL << DSI_VHBPCCR_HBP_Pos) /*!< 0x00000FFF */
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+#define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk /*!< Horizontal Back-Porch duration */
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+#define DSI_VHBPCCR_HBP0_Pos (0U)
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+#define DSI_VHBPCCR_HBP0_Msk (0x1UL << DSI_VHBPCCR_HBP0_Pos) /*!< 0x00000001 */
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+#define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk
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+#define DSI_VHBPCCR_HBP1_Pos (1U)
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+#define DSI_VHBPCCR_HBP1_Msk (0x1UL << DSI_VHBPCCR_HBP1_Pos) /*!< 0x00000002 */
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+#define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk
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+#define DSI_VHBPCCR_HBP2_Pos (2U)
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+#define DSI_VHBPCCR_HBP2_Msk (0x1UL << DSI_VHBPCCR_HBP2_Pos) /*!< 0x00000004 */
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+#define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk
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+#define DSI_VHBPCCR_HBP3_Pos (3U)
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+#define DSI_VHBPCCR_HBP3_Msk (0x1UL << DSI_VHBPCCR_HBP3_Pos) /*!< 0x00000008 */
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+#define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk
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+#define DSI_VHBPCCR_HBP4_Pos (4U)
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+#define DSI_VHBPCCR_HBP4_Msk (0x1UL << DSI_VHBPCCR_HBP4_Pos) /*!< 0x00000010 */
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+#define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk
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+#define DSI_VHBPCCR_HBP5_Pos (5U)
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+#define DSI_VHBPCCR_HBP5_Msk (0x1UL << DSI_VHBPCCR_HBP5_Pos) /*!< 0x00000020 */
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+#define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk
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+#define DSI_VHBPCCR_HBP6_Pos (6U)
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+#define DSI_VHBPCCR_HBP6_Msk (0x1UL << DSI_VHBPCCR_HBP6_Pos) /*!< 0x00000040 */
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+#define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk
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+#define DSI_VHBPCCR_HBP7_Pos (7U)
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+#define DSI_VHBPCCR_HBP7_Msk (0x1UL << DSI_VHBPCCR_HBP7_Pos) /*!< 0x00000080 */
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+#define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk
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+#define DSI_VHBPCCR_HBP8_Pos (8U)
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+#define DSI_VHBPCCR_HBP8_Msk (0x1UL << DSI_VHBPCCR_HBP8_Pos) /*!< 0x00000100 */
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+#define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk
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+#define DSI_VHBPCCR_HBP9_Pos (9U)
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+#define DSI_VHBPCCR_HBP9_Msk (0x1UL << DSI_VHBPCCR_HBP9_Pos) /*!< 0x00000200 */
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+#define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk
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+#define DSI_VHBPCCR_HBP10_Pos (10U)
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+#define DSI_VHBPCCR_HBP10_Msk (0x1UL << DSI_VHBPCCR_HBP10_Pos) /*!< 0x00000400 */
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+#define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk
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+#define DSI_VHBPCCR_HBP11_Pos (11U)
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+#define DSI_VHBPCCR_HBP11_Msk (0x1UL << DSI_VHBPCCR_HBP11_Pos) /*!< 0x00000800 */
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+#define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk
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+
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+/******************* Bit definition for DSI_VLCCR register **************/
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+#define DSI_VLCCR_HLINE_Pos (0U)
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+#define DSI_VLCCR_HLINE_Msk (0x7FFFUL << DSI_VLCCR_HLINE_Pos) /*!< 0x00007FFF */
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+#define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk /*!< Horizontal Line duration */
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+#define DSI_VLCCR_HLINE0_Pos (0U)
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+#define DSI_VLCCR_HLINE0_Msk (0x1UL << DSI_VLCCR_HLINE0_Pos) /*!< 0x00000001 */
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+#define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk
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+#define DSI_VLCCR_HLINE1_Pos (1U)
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+#define DSI_VLCCR_HLINE1_Msk (0x1UL << DSI_VLCCR_HLINE1_Pos) /*!< 0x00000002 */
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+#define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk
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+#define DSI_VLCCR_HLINE2_Pos (2U)
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+#define DSI_VLCCR_HLINE2_Msk (0x1UL << DSI_VLCCR_HLINE2_Pos) /*!< 0x00000004 */
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+#define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk
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+#define DSI_VLCCR_HLINE3_Pos (3U)
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+#define DSI_VLCCR_HLINE3_Msk (0x1UL << DSI_VLCCR_HLINE3_Pos) /*!< 0x00000008 */
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+#define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk
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+#define DSI_VLCCR_HLINE4_Pos (4U)
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+#define DSI_VLCCR_HLINE4_Msk (0x1UL << DSI_VLCCR_HLINE4_Pos) /*!< 0x00000010 */
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+#define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk
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+#define DSI_VLCCR_HLINE5_Pos (5U)
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+#define DSI_VLCCR_HLINE5_Msk (0x1UL << DSI_VLCCR_HLINE5_Pos) /*!< 0x00000020 */
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+#define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk
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+#define DSI_VLCCR_HLINE6_Pos (6U)
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+#define DSI_VLCCR_HLINE6_Msk (0x1UL << DSI_VLCCR_HLINE6_Pos) /*!< 0x00000040 */
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+#define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk
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+#define DSI_VLCCR_HLINE7_Pos (7U)
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+#define DSI_VLCCR_HLINE7_Msk (0x1UL << DSI_VLCCR_HLINE7_Pos) /*!< 0x00000080 */
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+#define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk
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+#define DSI_VLCCR_HLINE8_Pos (8U)
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+#define DSI_VLCCR_HLINE8_Msk (0x1UL << DSI_VLCCR_HLINE8_Pos) /*!< 0x00000100 */
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+#define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk
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+#define DSI_VLCCR_HLINE9_Pos (9U)
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+#define DSI_VLCCR_HLINE9_Msk (0x1UL << DSI_VLCCR_HLINE9_Pos) /*!< 0x00000200 */
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+#define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk
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+#define DSI_VLCCR_HLINE10_Pos (10U)
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+#define DSI_VLCCR_HLINE10_Msk (0x1UL << DSI_VLCCR_HLINE10_Pos) /*!< 0x00000400 */
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+#define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk
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+#define DSI_VLCCR_HLINE11_Pos (11U)
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+#define DSI_VLCCR_HLINE11_Msk (0x1UL << DSI_VLCCR_HLINE11_Pos) /*!< 0x00000800 */
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+#define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk
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+#define DSI_VLCCR_HLINE12_Pos (12U)
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+#define DSI_VLCCR_HLINE12_Msk (0x1UL << DSI_VLCCR_HLINE12_Pos) /*!< 0x00001000 */
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+#define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk
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+#define DSI_VLCCR_HLINE13_Pos (13U)
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+#define DSI_VLCCR_HLINE13_Msk (0x1UL << DSI_VLCCR_HLINE13_Pos) /*!< 0x00002000 */
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+#define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk
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+#define DSI_VLCCR_HLINE14_Pos (14U)
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+#define DSI_VLCCR_HLINE14_Msk (0x1UL << DSI_VLCCR_HLINE14_Pos) /*!< 0x00004000 */
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+#define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk
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+
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+/******************* Bit definition for DSI_VVSACCR register ***************/
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+#define DSI_VVSACCR_VSA_Pos (0U)
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+#define DSI_VVSACCR_VSA_Msk (0x3FFUL << DSI_VVSACCR_VSA_Pos) /*!< 0x000003FF */
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+#define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk /*!< Vertical Synchronism Active duration */
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+#define DSI_VVSACCR_VSA0_Pos (0U)
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+#define DSI_VVSACCR_VSA0_Msk (0x1UL << DSI_VVSACCR_VSA0_Pos) /*!< 0x00000001 */
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+#define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk
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+#define DSI_VVSACCR_VSA1_Pos (1U)
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+#define DSI_VVSACCR_VSA1_Msk (0x1UL << DSI_VVSACCR_VSA1_Pos) /*!< 0x00000002 */
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+#define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk
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+#define DSI_VVSACCR_VSA2_Pos (2U)
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+#define DSI_VVSACCR_VSA2_Msk (0x1UL << DSI_VVSACCR_VSA2_Pos) /*!< 0x00000004 */
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+#define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk
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+#define DSI_VVSACCR_VSA3_Pos (3U)
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+#define DSI_VVSACCR_VSA3_Msk (0x1UL << DSI_VVSACCR_VSA3_Pos) /*!< 0x00000008 */
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+#define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk
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+#define DSI_VVSACCR_VSA4_Pos (4U)
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+#define DSI_VVSACCR_VSA4_Msk (0x1UL << DSI_VVSACCR_VSA4_Pos) /*!< 0x00000010 */
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+#define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk
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+#define DSI_VVSACCR_VSA5_Pos (5U)
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+#define DSI_VVSACCR_VSA5_Msk (0x1UL << DSI_VVSACCR_VSA5_Pos) /*!< 0x00000020 */
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+#define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk
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+#define DSI_VVSACCR_VSA6_Pos (6U)
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+#define DSI_VVSACCR_VSA6_Msk (0x1UL << DSI_VVSACCR_VSA6_Pos) /*!< 0x00000040 */
|
|
|
+#define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk
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+#define DSI_VVSACCR_VSA7_Pos (7U)
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+#define DSI_VVSACCR_VSA7_Msk (0x1UL << DSI_VVSACCR_VSA7_Pos) /*!< 0x00000080 */
|
|
|
+#define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk
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|
+#define DSI_VVSACCR_VSA8_Pos (8U)
|
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+#define DSI_VVSACCR_VSA8_Msk (0x1UL << DSI_VVSACCR_VSA8_Pos) /*!< 0x00000100 */
|
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+#define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk
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+#define DSI_VVSACCR_VSA9_Pos (9U)
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+#define DSI_VVSACCR_VSA9_Msk (0x1UL << DSI_VVSACCR_VSA9_Pos) /*!< 0x00000200 */
|
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|
+#define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk
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+
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|
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+/******************* Bit definition for DSI_VVBPCCR register ************/
|
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+#define DSI_VVBPCCR_VBP_Pos (0U)
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+#define DSI_VVBPCCR_VBP_Msk (0x3FFUL << DSI_VVBPCCR_VBP_Pos) /*!< 0x000003FF */
|
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|
+#define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk /*!< Vertical Back-Porch duration */
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+#define DSI_VVBPCCR_VBP0_Pos (0U)
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+#define DSI_VVBPCCR_VBP0_Msk (0x1UL << DSI_VVBPCCR_VBP0_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk
|
|
|
+#define DSI_VVBPCCR_VBP1_Pos (1U)
|
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+#define DSI_VVBPCCR_VBP1_Msk (0x1UL << DSI_VVBPCCR_VBP1_Pos) /*!< 0x00000002 */
|
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|
+#define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk
|
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+#define DSI_VVBPCCR_VBP2_Pos (2U)
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|
+#define DSI_VVBPCCR_VBP2_Msk (0x1UL << DSI_VVBPCCR_VBP2_Pos) /*!< 0x00000004 */
|
|
|
+#define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk
|
|
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+#define DSI_VVBPCCR_VBP3_Pos (3U)
|
|
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+#define DSI_VVBPCCR_VBP3_Msk (0x1UL << DSI_VVBPCCR_VBP3_Pos) /*!< 0x00000008 */
|
|
|
+#define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk
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+#define DSI_VVBPCCR_VBP4_Pos (4U)
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|
+#define DSI_VVBPCCR_VBP4_Msk (0x1UL << DSI_VVBPCCR_VBP4_Pos) /*!< 0x00000010 */
|
|
|
+#define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk
|
|
|
+#define DSI_VVBPCCR_VBP5_Pos (5U)
|
|
|
+#define DSI_VVBPCCR_VBP5_Msk (0x1UL << DSI_VVBPCCR_VBP5_Pos) /*!< 0x00000020 */
|
|
|
+#define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk
|
|
|
+#define DSI_VVBPCCR_VBP6_Pos (6U)
|
|
|
+#define DSI_VVBPCCR_VBP6_Msk (0x1UL << DSI_VVBPCCR_VBP6_Pos) /*!< 0x00000040 */
|
|
|
+#define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk
|
|
|
+#define DSI_VVBPCCR_VBP7_Pos (7U)
|
|
|
+#define DSI_VVBPCCR_VBP7_Msk (0x1UL << DSI_VVBPCCR_VBP7_Pos) /*!< 0x00000080 */
|
|
|
+#define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk
|
|
|
+#define DSI_VVBPCCR_VBP8_Pos (8U)
|
|
|
+#define DSI_VVBPCCR_VBP8_Msk (0x1UL << DSI_VVBPCCR_VBP8_Pos) /*!< 0x00000100 */
|
|
|
+#define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk
|
|
|
+#define DSI_VVBPCCR_VBP9_Pos (9U)
|
|
|
+#define DSI_VVBPCCR_VBP9_Msk (0x1UL << DSI_VVBPCCR_VBP9_Pos) /*!< 0x00000200 */
|
|
|
+#define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk
|
|
|
+
|
|
|
+/******************* Bit definition for DSI_VVFPCCR register ************/
|
|
|
+#define DSI_VVFPCCR_VFP_Pos (0U)
|
|
|
+#define DSI_VVFPCCR_VFP_Msk (0x3FFUL << DSI_VVFPCCR_VFP_Pos) /*!< 0x000003FF */
|
|
|
+#define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk /*!< Vertical Front-Porch duration */
|
|
|
+#define DSI_VVFPCCR_VFP0_Pos (0U)
|
|
|
+#define DSI_VVFPCCR_VFP0_Msk (0x1UL << DSI_VVFPCCR_VFP0_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk
|
|
|
+#define DSI_VVFPCCR_VFP1_Pos (1U)
|
|
|
+#define DSI_VVFPCCR_VFP1_Msk (0x1UL << DSI_VVFPCCR_VFP1_Pos) /*!< 0x00000002 */
|
|
|
+#define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk
|
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+#define DSI_VVFPCCR_VFP2_Pos (2U)
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+#define DSI_VVFPCCR_VFP2_Msk (0x1UL << DSI_VVFPCCR_VFP2_Pos) /*!< 0x00000004 */
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+#define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk
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+#define DSI_VVFPCCR_VFP3_Pos (3U)
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+#define DSI_VVFPCCR_VFP3_Msk (0x1UL << DSI_VVFPCCR_VFP3_Pos) /*!< 0x00000008 */
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+#define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk
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+#define DSI_VVFPCCR_VFP4_Pos (4U)
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+#define DSI_VVFPCCR_VFP4_Msk (0x1UL << DSI_VVFPCCR_VFP4_Pos) /*!< 0x00000010 */
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+#define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk
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+#define DSI_VVFPCCR_VFP5_Pos (5U)
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+#define DSI_VVFPCCR_VFP5_Msk (0x1UL << DSI_VVFPCCR_VFP5_Pos) /*!< 0x00000020 */
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+#define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk
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+#define DSI_VVFPCCR_VFP6_Pos (6U)
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+#define DSI_VVFPCCR_VFP6_Msk (0x1UL << DSI_VVFPCCR_VFP6_Pos) /*!< 0x00000040 */
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+#define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk
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+#define DSI_VVFPCCR_VFP7_Pos (7U)
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+#define DSI_VVFPCCR_VFP7_Msk (0x1UL << DSI_VVFPCCR_VFP7_Pos) /*!< 0x00000080 */
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+#define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk
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+#define DSI_VVFPCCR_VFP8_Pos (8U)
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+#define DSI_VVFPCCR_VFP8_Msk (0x1UL << DSI_VVFPCCR_VFP8_Pos) /*!< 0x00000100 */
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+#define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk
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+#define DSI_VVFPCCR_VFP9_Pos (9U)
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+#define DSI_VVFPCCR_VFP9_Msk (0x1UL << DSI_VVFPCCR_VFP9_Pos) /*!< 0x00000200 */
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+#define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk
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+
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+/******************* Bit definition for DSI_VVACCR register *************/
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+#define DSI_VVACCR_VA_Pos (0U)
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+#define DSI_VVACCR_VA_Msk (0x3FFFUL << DSI_VVACCR_VA_Pos) /*!< 0x00003FFF */
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+#define DSI_VVACCR_VA DSI_VVACCR_VA_Msk /*!< Vertical Active duration */
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+#define DSI_VVACCR_VA0_Pos (0U)
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+#define DSI_VVACCR_VA0_Msk (0x1UL << DSI_VVACCR_VA0_Pos) /*!< 0x00000001 */
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+#define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk
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+#define DSI_VVACCR_VA1_Pos (1U)
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+#define DSI_VVACCR_VA1_Msk (0x1UL << DSI_VVACCR_VA1_Pos) /*!< 0x00000002 */
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+#define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk
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+#define DSI_VVACCR_VA2_Pos (2U)
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+#define DSI_VVACCR_VA2_Msk (0x1UL << DSI_VVACCR_VA2_Pos) /*!< 0x00000004 */
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+#define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk
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+#define DSI_VVACCR_VA3_Pos (3U)
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+#define DSI_VVACCR_VA3_Msk (0x1UL << DSI_VVACCR_VA3_Pos) /*!< 0x00000008 */
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+#define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk
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+#define DSI_VVACCR_VA4_Pos (4U)
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+#define DSI_VVACCR_VA4_Msk (0x1UL << DSI_VVACCR_VA4_Pos) /*!< 0x00000010 */
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+#define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk
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+#define DSI_VVACCR_VA5_Pos (5U)
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+#define DSI_VVACCR_VA5_Msk (0x1UL << DSI_VVACCR_VA5_Pos) /*!< 0x00000020 */
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+#define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk
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+#define DSI_VVACCR_VA6_Pos (6U)
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+#define DSI_VVACCR_VA6_Msk (0x1UL << DSI_VVACCR_VA6_Pos) /*!< 0x00000040 */
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+#define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk
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+#define DSI_VVACCR_VA7_Pos (7U)
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+#define DSI_VVACCR_VA7_Msk (0x1UL << DSI_VVACCR_VA7_Pos) /*!< 0x00000080 */
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+#define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk
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+#define DSI_VVACCR_VA8_Pos (8U)
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+#define DSI_VVACCR_VA8_Msk (0x1UL << DSI_VVACCR_VA8_Pos) /*!< 0x00000100 */
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+#define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk
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+#define DSI_VVACCR_VA9_Pos (9U)
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+#define DSI_VVACCR_VA9_Msk (0x1UL << DSI_VVACCR_VA9_Pos) /*!< 0x00000200 */
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+#define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk
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+#define DSI_VVACCR_VA10_Pos (10U)
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+#define DSI_VVACCR_VA10_Msk (0x1UL << DSI_VVACCR_VA10_Pos) /*!< 0x00000400 */
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+#define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk
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+#define DSI_VVACCR_VA11_Pos (11U)
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+#define DSI_VVACCR_VA11_Msk (0x1UL << DSI_VVACCR_VA11_Pos) /*!< 0x00000800 */
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+#define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk
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+#define DSI_VVACCR_VA12_Pos (12U)
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+#define DSI_VVACCR_VA12_Msk (0x1UL << DSI_VVACCR_VA12_Pos) /*!< 0x00001000 */
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+#define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk
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+#define DSI_VVACCR_VA13_Pos (13U)
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+#define DSI_VVACCR_VA13_Msk (0x1UL << DSI_VVACCR_VA13_Pos) /*!< 0x00002000 */
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+#define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
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+
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+/******************* Bit definition for DSI_TDCCR register **************/
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+#define DSI_TDCCR_3DM 0x00000003U /*!< 3D Mode */
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+#define DSI_TDCCR_3DM0 0x00000001U
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+#define DSI_TDCCR_3DM1 0x00000002U
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+
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+#define DSI_TDCCR_3DF 0x0000000CU /*!< 3D Format */
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+#define DSI_TDCCR_3DF0 0x00000004U
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+#define DSI_TDCCR_3DF1 0x00000008U
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+
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+#define DSI_TDCCR_SVS_Pos (4U)
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+#define DSI_TDCCR_SVS_Msk (0x1UL << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */
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+#define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk /*!< Second VSYNC */
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+#define DSI_TDCCR_RF_Pos (5U)
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+#define DSI_TDCCR_RF_Msk (0x1UL << DSI_TDCCR_RF_Pos) /*!< 0x00000020 */
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+#define DSI_TDCCR_RF DSI_TDCCR_RF_Msk /*!< Right First */
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+#define DSI_TDCCR_S3DC_Pos (16U)
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+#define DSI_TDCCR_S3DC_Msk (0x1UL << DSI_TDCCR_S3DC_Pos) /*!< 0x00010000 */
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+#define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk /*!< Send 3D Control */
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+
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+/******************* Bit definition for DSI_WCFGR register ***************/
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+#define DSI_WCFGR_DSIM_Pos (0U)
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+#define DSI_WCFGR_DSIM_Msk (0x1UL << DSI_WCFGR_DSIM_Pos) /*!< 0x00000001 */
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+#define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk /*!< DSI Mode */
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+#define DSI_WCFGR_COLMUX_Pos (1U)
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+#define DSI_WCFGR_COLMUX_Msk (0x7UL << DSI_WCFGR_COLMUX_Pos) /*!< 0x0000000E */
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+#define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk /*!< Color Multiplexing */
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+#define DSI_WCFGR_COLMUX0_Pos (1U)
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+#define DSI_WCFGR_COLMUX0_Msk (0x1UL << DSI_WCFGR_COLMUX0_Pos) /*!< 0x00000002 */
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+#define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk
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+#define DSI_WCFGR_COLMUX1_Pos (2U)
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+#define DSI_WCFGR_COLMUX1_Msk (0x1UL << DSI_WCFGR_COLMUX1_Pos) /*!< 0x00000004 */
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+#define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk
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+#define DSI_WCFGR_COLMUX2_Pos (3U)
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+#define DSI_WCFGR_COLMUX2_Msk (0x1UL << DSI_WCFGR_COLMUX2_Pos) /*!< 0x00000008 */
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+#define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk
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+
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+#define DSI_WCFGR_TESRC_Pos (4U)
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+#define DSI_WCFGR_TESRC_Msk (0x1UL << DSI_WCFGR_TESRC_Pos) /*!< 0x00000010 */
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+#define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk /*!< Tearing Effect Source */
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+#define DSI_WCFGR_TEPOL_Pos (5U)
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+#define DSI_WCFGR_TEPOL_Msk (0x1UL << DSI_WCFGR_TEPOL_Pos) /*!< 0x00000020 */
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+#define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk /*!< Tearing Effect Polarity */
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+#define DSI_WCFGR_AR_Pos (6U)
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+#define DSI_WCFGR_AR_Msk (0x1UL << DSI_WCFGR_AR_Pos) /*!< 0x00000040 */
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+#define DSI_WCFGR_AR DSI_WCFGR_AR_Msk /*!< Automatic Refresh */
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+#define DSI_WCFGR_VSPOL_Pos (7U)
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+#define DSI_WCFGR_VSPOL_Msk (0x1UL << DSI_WCFGR_VSPOL_Pos) /*!< 0x00000080 */
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+#define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk /*!< VSync Polarity */
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+
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+/******************* Bit definition for DSI_WCR register *****************/
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+#define DSI_WCR_COLM_Pos (0U)
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+#define DSI_WCR_COLM_Msk (0x1UL << DSI_WCR_COLM_Pos) /*!< 0x00000001 */
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+#define DSI_WCR_COLM DSI_WCR_COLM_Msk /*!< Color Mode */
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+#define DSI_WCR_SHTDN_Pos (1U)
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+#define DSI_WCR_SHTDN_Msk (0x1UL << DSI_WCR_SHTDN_Pos) /*!< 0x00000002 */
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+#define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk /*!< Shutdown */
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+#define DSI_WCR_LTDCEN_Pos (2U)
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+#define DSI_WCR_LTDCEN_Msk (0x1UL << DSI_WCR_LTDCEN_Pos) /*!< 0x00000004 */
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+#define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk /*!< LTDC Enable */
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+#define DSI_WCR_DSIEN_Pos (3U)
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+#define DSI_WCR_DSIEN_Msk (0x1UL << DSI_WCR_DSIEN_Pos) /*!< 0x00000008 */
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+#define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk /*!< DSI Enable */
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+
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+/******************* Bit definition for DSI_WIER register ****************/
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+#define DSI_WIER_TEIE_Pos (0U)
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+#define DSI_WIER_TEIE_Msk (0x1UL << DSI_WIER_TEIE_Pos) /*!< 0x00000001 */
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+#define DSI_WIER_TEIE DSI_WIER_TEIE_Msk /*!< Tearing Effect Interrupt Enable */
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+#define DSI_WIER_ERIE_Pos (1U)
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+#define DSI_WIER_ERIE_Msk (0x1UL << DSI_WIER_ERIE_Pos) /*!< 0x00000002 */
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+#define DSI_WIER_ERIE DSI_WIER_ERIE_Msk /*!< End of Refresh Interrupt Enable */
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+#define DSI_WIER_PLLLIE_Pos (9U)
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+#define DSI_WIER_PLLLIE_Msk (0x1UL << DSI_WIER_PLLLIE_Pos) /*!< 0x00000200 */
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+#define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk /*!< PLL Lock Interrupt Enable */
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+#define DSI_WIER_PLLUIE_Pos (10U)
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+#define DSI_WIER_PLLUIE_Msk (0x1UL << DSI_WIER_PLLUIE_Pos) /*!< 0x00000400 */
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+#define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk /*!< PLL Unlock Interrupt Enable */
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+#define DSI_WIER_RRIE_Pos (13U)
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+#define DSI_WIER_RRIE_Msk (0x1UL << DSI_WIER_RRIE_Pos) /*!< 0x00002000 */
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+#define DSI_WIER_RRIE DSI_WIER_RRIE_Msk /*!< Regulator Ready Interrupt Enable */
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+
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+/******************* Bit definition for DSI_WISR register ****************/
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+#define DSI_WISR_TEIF_Pos (0U)
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+#define DSI_WISR_TEIF_Msk (0x1UL << DSI_WISR_TEIF_Pos) /*!< 0x00000001 */
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+#define DSI_WISR_TEIF DSI_WISR_TEIF_Msk /*!< Tearing Effect Interrupt Flag */
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+#define DSI_WISR_ERIF_Pos (1U)
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+#define DSI_WISR_ERIF_Msk (0x1UL << DSI_WISR_ERIF_Pos) /*!< 0x00000002 */
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+#define DSI_WISR_ERIF DSI_WISR_ERIF_Msk /*!< End of Refresh Interrupt Flag */
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+#define DSI_WISR_BUSY_Pos (2U)
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+#define DSI_WISR_BUSY_Msk (0x1UL << DSI_WISR_BUSY_Pos) /*!< 0x00000004 */
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+#define DSI_WISR_BUSY DSI_WISR_BUSY_Msk /*!< Busy Flag */
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+#define DSI_WISR_PLLLS_Pos (8U)
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+#define DSI_WISR_PLLLS_Msk (0x1UL << DSI_WISR_PLLLS_Pos) /*!< 0x00000100 */
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+#define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk /*!< PLL Lock Status */
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+#define DSI_WISR_PLLLIF_Pos (9U)
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+#define DSI_WISR_PLLLIF_Msk (0x1UL << DSI_WISR_PLLLIF_Pos) /*!< 0x00000200 */
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+#define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk /*!< PLL Lock Interrupt Flag */
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+#define DSI_WISR_PLLUIF_Pos (10U)
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+#define DSI_WISR_PLLUIF_Msk (0x1UL << DSI_WISR_PLLUIF_Pos) /*!< 0x00000400 */
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+#define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk /*!< PLL Unlock Interrupt Flag */
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+#define DSI_WISR_RRS_Pos (12U)
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+#define DSI_WISR_RRS_Msk (0x1UL << DSI_WISR_RRS_Pos) /*!< 0x00001000 */
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+#define DSI_WISR_RRS DSI_WISR_RRS_Msk /*!< Regulator Ready Flag */
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+#define DSI_WISR_RRIF_Pos (13U)
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+#define DSI_WISR_RRIF_Msk (0x1UL << DSI_WISR_RRIF_Pos) /*!< 0x00002000 */
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+#define DSI_WISR_RRIF DSI_WISR_RRIF_Msk /*!< Regulator Ready Interrupt Flag */
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+
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+/******************* Bit definition for DSI_WIFCR register ***************/
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+#define DSI_WIFCR_CTEIF_Pos (0U)
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+#define DSI_WIFCR_CTEIF_Msk (0x1UL << DSI_WIFCR_CTEIF_Pos) /*!< 0x00000001 */
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+#define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk /*!< Clear Tearing Effect Interrupt Flag */
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+#define DSI_WIFCR_CERIF_Pos (1U)
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+#define DSI_WIFCR_CERIF_Msk (0x1UL << DSI_WIFCR_CERIF_Pos) /*!< 0x00000002 */
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+#define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk /*!< Clear End of Refresh Interrupt Flag */
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|
+#define DSI_WIFCR_CPLLLIF_Pos (9U)
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+#define DSI_WIFCR_CPLLLIF_Msk (0x1UL << DSI_WIFCR_CPLLLIF_Pos) /*!< 0x00000200 */
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|
+#define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk /*!< Clear PLL Lock Interrupt Flag */
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|
+#define DSI_WIFCR_CPLLUIF_Pos (10U)
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+#define DSI_WIFCR_CPLLUIF_Msk (0x1UL << DSI_WIFCR_CPLLUIF_Pos) /*!< 0x00000400 */
|
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|
+#define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk /*!< Clear PLL Unlock Interrupt Flag */
|
|
|
+#define DSI_WIFCR_CRRIF_Pos (13U)
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|
+#define DSI_WIFCR_CRRIF_Msk (0x1UL << DSI_WIFCR_CRRIF_Pos) /*!< 0x00002000 */
|
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|
+#define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk /*!< Clear Regulator Ready Interrupt Flag */
|
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|
+
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|
|
+/******************* Bit definition for DSI_WPCR0 register ***************/
|
|
|
+#define DSI_WPCR0_UIX4_Pos (0U)
|
|
|
+#define DSI_WPCR0_UIX4_Msk (0x3FUL << DSI_WPCR0_UIX4_Pos) /*!< 0x0000003F */
|
|
|
+#define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk /*!< Unit Interval multiplied by 4 */
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|
+#define DSI_WPCR0_UIX4_0 (0x01UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000001 */
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|
|
+#define DSI_WPCR0_UIX4_1 (0x02UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000002 */
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|
|
+#define DSI_WPCR0_UIX4_2 (0x04UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000004 */
|
|
|
+#define DSI_WPCR0_UIX4_3 (0x08UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000008 */
|
|
|
+#define DSI_WPCR0_UIX4_4 (0x10UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000010 */
|
|
|
+#define DSI_WPCR0_UIX4_5 (0x20UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000020 */
|
|
|
+
|
|
|
+#define DSI_WPCR0_SWCL_Pos (6U)
|
|
|
+#define DSI_WPCR0_SWCL_Msk (0x1UL << DSI_WPCR0_SWCL_Pos) /*!< 0x00000040 */
|
|
|
+#define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk /*!< Swap pins on clock lane */
|
|
|
+#define DSI_WPCR0_SWDL0_Pos (7U)
|
|
|
+#define DSI_WPCR0_SWDL0_Msk (0x1UL << DSI_WPCR0_SWDL0_Pos) /*!< 0x00000080 */
|
|
|
+#define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk /*!< Swap pins on data lane 1 */
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|
|
+#define DSI_WPCR0_SWDL1_Pos (8U)
|
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|
+#define DSI_WPCR0_SWDL1_Msk (0x1UL << DSI_WPCR0_SWDL1_Pos) /*!< 0x00000100 */
|
|
|
+#define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk /*!< Swap pins on data lane 2 */
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+#define DSI_WPCR0_HSICL_Pos (9U)
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+#define DSI_WPCR0_HSICL_Msk (0x1UL << DSI_WPCR0_HSICL_Pos) /*!< 0x00000200 */
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+#define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk /*!< Invert the high-speed data signal on clock lane */
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+#define DSI_WPCR0_HSIDL0_Pos (10U)
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+#define DSI_WPCR0_HSIDL0_Msk (0x1UL << DSI_WPCR0_HSIDL0_Pos) /*!< 0x00000400 */
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+#define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk /*!< Invert the high-speed data signal on lane 1 */
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+#define DSI_WPCR0_HSIDL1_Pos (11U)
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+#define DSI_WPCR0_HSIDL1_Msk (0x1UL << DSI_WPCR0_HSIDL1_Pos) /*!< 0x00000800 */
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+#define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk /*!< Invert the high-speed data signal on lane 2 */
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+#define DSI_WPCR0_FTXSMCL_Pos (12U)
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+#define DSI_WPCR0_FTXSMCL_Msk (0x1UL << DSI_WPCR0_FTXSMCL_Pos) /*!< 0x00001000 */
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+#define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk /*!< Force clock lane in TX stop mode */
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+#define DSI_WPCR0_FTXSMDL_Pos (13U)
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+#define DSI_WPCR0_FTXSMDL_Msk (0x1UL << DSI_WPCR0_FTXSMDL_Pos) /*!< 0x00002000 */
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+#define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk /*!< Force data lanes in TX stop mode */
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+#define DSI_WPCR0_CDOFFDL_Pos (14U)
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+#define DSI_WPCR0_CDOFFDL_Msk (0x1UL << DSI_WPCR0_CDOFFDL_Pos) /*!< 0x00004000 */
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+#define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk /*!< Contention detection OFF */
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+#define DSI_WPCR0_TDDL_Pos (16U)
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+#define DSI_WPCR0_TDDL_Msk (0x1UL << DSI_WPCR0_TDDL_Pos) /*!< 0x00010000 */
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+#define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk /*!< Turn Disable Data Lanes */
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+#define DSI_WPCR0_PDEN_Pos (18U)
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+#define DSI_WPCR0_PDEN_Msk (0x1UL << DSI_WPCR0_PDEN_Pos) /*!< 0x00040000 */
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+#define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk /*!< Pull-Down Enable */
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+#define DSI_WPCR0_TCLKPREPEN_Pos (19U)
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+#define DSI_WPCR0_TCLKPREPEN_Msk (0x1UL << DSI_WPCR0_TCLKPREPEN_Pos) /*!< 0x00080000 */
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+#define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk /*!< Timer for t-CLKPREP Enable */
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+#define DSI_WPCR0_TCLKZEROEN_Pos (20U)
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+#define DSI_WPCR0_TCLKZEROEN_Msk (0x1UL << DSI_WPCR0_TCLKZEROEN_Pos) /*!< 0x00100000 */
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+#define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk /*!< Timer for t-CLKZERO Enable */
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+#define DSI_WPCR0_THSPREPEN_Pos (21U)
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+#define DSI_WPCR0_THSPREPEN_Msk (0x1UL << DSI_WPCR0_THSPREPEN_Pos) /*!< 0x00200000 */
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+#define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk /*!< Timer for t-HSPREP Enable */
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+#define DSI_WPCR0_THSTRAILEN_Pos (22U)
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+#define DSI_WPCR0_THSTRAILEN_Msk (0x1UL << DSI_WPCR0_THSTRAILEN_Pos) /*!< 0x00400000 */
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+#define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk /*!< Timer for t-HSTRAIL Enable */
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+#define DSI_WPCR0_THSZEROEN_Pos (23U)
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+#define DSI_WPCR0_THSZEROEN_Msk (0x1UL << DSI_WPCR0_THSZEROEN_Pos) /*!< 0x00800000 */
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+#define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk /*!< Timer for t-HSZERO Enable */
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+#define DSI_WPCR0_TLPXDEN_Pos (24U)
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+#define DSI_WPCR0_TLPXDEN_Msk (0x1UL << DSI_WPCR0_TLPXDEN_Pos) /*!< 0x01000000 */
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+#define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk /*!< Timer for t-LPXD Enable */
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+#define DSI_WPCR0_THSEXITEN_Pos (25U)
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+#define DSI_WPCR0_THSEXITEN_Msk (0x1UL << DSI_WPCR0_THSEXITEN_Pos) /*!< 0x02000000 */
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+#define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk /*!< Timer for t-HSEXIT Enable */
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+#define DSI_WPCR0_TLPXCEN_Pos (26U)
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+#define DSI_WPCR0_TLPXCEN_Msk (0x1UL << DSI_WPCR0_TLPXCEN_Pos) /*!< 0x04000000 */
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+#define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk /*!< Timer for t-LPXC Enable */
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+#define DSI_WPCR0_TCLKPOSTEN_Pos (27U)
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+#define DSI_WPCR0_TCLKPOSTEN_Msk (0x1UL << DSI_WPCR0_TCLKPOSTEN_Pos) /*!< 0x08000000 */
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+#define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk /*!< Timer for t-CLKPOST Enable */
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+
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+/******************* Bit definition for DSI_WPCR1 register ***************/
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+#define DSI_WPCR1_HSTXDCL_Pos (0U)
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+#define DSI_WPCR1_HSTXDCL_Msk (0x3UL << DSI_WPCR1_HSTXDCL_Pos) /*!< 0x00000003 */
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+#define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
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+#define DSI_WPCR1_HSTXDCL0_Pos (0U)
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+#define DSI_WPCR1_HSTXDCL0_Msk (0x1UL << DSI_WPCR1_HSTXDCL0_Pos) /*!< 0x00000001 */
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+#define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk
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+#define DSI_WPCR1_HSTXDCL1_Pos (1U)
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+#define DSI_WPCR1_HSTXDCL1_Msk (0x1UL << DSI_WPCR1_HSTXDCL1_Pos) /*!< 0x00000002 */
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+#define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk
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+
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+#define DSI_WPCR1_HSTXDDL_Pos (2U)
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+#define DSI_WPCR1_HSTXDDL_Msk (0x3UL << DSI_WPCR1_HSTXDDL_Pos) /*!< 0x0000000C */
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+#define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
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+#define DSI_WPCR1_HSTXDDL0_Pos (2U)
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+#define DSI_WPCR1_HSTXDDL0_Msk (0x1UL << DSI_WPCR1_HSTXDDL0_Pos) /*!< 0x00000004 */
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+#define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk
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+#define DSI_WPCR1_HSTXDDL1_Pos (3U)
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+#define DSI_WPCR1_HSTXDDL1_Msk (0x1UL << DSI_WPCR1_HSTXDDL1_Pos) /*!< 0x00000008 */
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+#define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk
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+
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+#define DSI_WPCR1_LPSRCCL_Pos (6U)
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+#define DSI_WPCR1_LPSRCCL_Msk (0x3UL << DSI_WPCR1_LPSRCCL_Pos) /*!< 0x000000C0 */
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+#define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
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+#define DSI_WPCR1_LPSRCCL0_Pos (6U)
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+#define DSI_WPCR1_LPSRCCL0_Msk (0x1UL << DSI_WPCR1_LPSRCCL0_Pos) /*!< 0x00000040 */
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+#define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk
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+#define DSI_WPCR1_LPSRCCL1_Pos (7U)
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+#define DSI_WPCR1_LPSRCCL1_Msk (0x1UL << DSI_WPCR1_LPSRCCL1_Pos) /*!< 0x00000080 */
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+#define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk
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+
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+#define DSI_WPCR1_LPSRCDL_Pos (8U)
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+#define DSI_WPCR1_LPSRCDL_Msk (0x3UL << DSI_WPCR1_LPSRCDL_Pos) /*!< 0x00000300 */
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+#define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
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+#define DSI_WPCR1_LPSRCDL0_Pos (8U)
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+#define DSI_WPCR1_LPSRCDL0_Msk (0x1UL << DSI_WPCR1_LPSRCDL0_Pos) /*!< 0x00000100 */
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+#define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk
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+#define DSI_WPCR1_LPSRCDL1_Pos (9U)
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+#define DSI_WPCR1_LPSRCDL1_Msk (0x1UL << DSI_WPCR1_LPSRCDL1_Pos) /*!< 0x00000200 */
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+#define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk
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+
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+#define DSI_WPCR1_SDDC_Pos (12U)
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+#define DSI_WPCR1_SDDC_Msk (0x1UL << DSI_WPCR1_SDDC_Pos) /*!< 0x00001000 */
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+#define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk /*!< SDD Control */
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+
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+#define DSI_WPCR1_LPRXVCDL_Pos (14U)
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+#define DSI_WPCR1_LPRXVCDL_Msk (0x3UL << DSI_WPCR1_LPRXVCDL_Pos) /*!< 0x0000C000 */
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+#define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk /*!< Low-Power Reception V-IL Compensation on Data Lanes */
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+#define DSI_WPCR1_LPRXVCDL0_Pos (14U)
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+#define DSI_WPCR1_LPRXVCDL0_Msk (0x1UL << DSI_WPCR1_LPRXVCDL0_Pos) /*!< 0x00004000 */
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+#define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk
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+#define DSI_WPCR1_LPRXVCDL1_Pos (15U)
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+#define DSI_WPCR1_LPRXVCDL1_Msk (0x1UL << DSI_WPCR1_LPRXVCDL1_Pos) /*!< 0x00008000 */
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+#define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk
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+
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+#define DSI_WPCR1_HSTXSRCCL_Pos (16U)
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+#define DSI_WPCR1_HSTXSRCCL_Msk (0x3UL << DSI_WPCR1_HSTXSRCCL_Pos) /*!< 0x00030000 */
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+#define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
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+#define DSI_WPCR1_HSTXSRCCL0_Pos (16U)
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+#define DSI_WPCR1_HSTXSRCCL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL0_Pos) /*!< 0x00010000 */
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+#define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk
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+#define DSI_WPCR1_HSTXSRCCL1_Pos (17U)
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+#define DSI_WPCR1_HSTXSRCCL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL1_Pos) /*!< 0x00020000 */
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+#define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk
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+
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+#define DSI_WPCR1_HSTXSRCDL_Pos (18U)
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+#define DSI_WPCR1_HSTXSRCDL_Msk (0x3UL << DSI_WPCR1_HSTXSRCDL_Pos) /*!< 0x000C0000 */
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+#define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
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+#define DSI_WPCR1_HSTXSRCDL0_Pos (18U)
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+#define DSI_WPCR1_HSTXSRCDL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL0_Pos) /*!< 0x00040000 */
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+#define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk
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+#define DSI_WPCR1_HSTXSRCDL1_Pos (19U)
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+#define DSI_WPCR1_HSTXSRCDL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL1_Pos) /*!< 0x00080000 */
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+#define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk
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+
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+#define DSI_WPCR1_FLPRXLPM_Pos (22U)
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+#define DSI_WPCR1_FLPRXLPM_Msk (0x1UL << DSI_WPCR1_FLPRXLPM_Pos) /*!< 0x00400000 */
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+#define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk /*!< Forces LP Receiver in Low-Power Mode */
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+
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+#define DSI_WPCR1_LPRXFT_Pos (25U)
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+#define DSI_WPCR1_LPRXFT_Msk (0x3UL << DSI_WPCR1_LPRXFT_Pos) /*!< 0x06000000 */
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+#define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk /*!< Low-Power RX low-pass Filtering Tuning */
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+#define DSI_WPCR1_LPRXFT0_Pos (25U)
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+#define DSI_WPCR1_LPRXFT0_Msk (0x1UL << DSI_WPCR1_LPRXFT0_Pos) /*!< 0x02000000 */
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+#define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk
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+#define DSI_WPCR1_LPRXFT1_Pos (26U)
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+#define DSI_WPCR1_LPRXFT1_Msk (0x1UL << DSI_WPCR1_LPRXFT1_Pos) /*!< 0x04000000 */
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+#define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk
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+
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+/******************* Bit definition for DSI_WPCR2 register ***************/
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+#define DSI_WPCR2_TCLKPREP_Pos (0U)
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+#define DSI_WPCR2_TCLKPREP_Msk (0xFFUL << DSI_WPCR2_TCLKPREP_Pos) /*!< 0x000000FF */
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+#define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk /*!< t-CLKPREP */
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+#define DSI_WPCR2_TCLKPREP0_Pos (0U)
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+#define DSI_WPCR2_TCLKPREP0_Msk (0x1UL << DSI_WPCR2_TCLKPREP0_Pos) /*!< 0x00000001 */
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+#define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk
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+#define DSI_WPCR2_TCLKPREP1_Pos (1U)
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+#define DSI_WPCR2_TCLKPREP1_Msk (0x1UL << DSI_WPCR2_TCLKPREP1_Pos) /*!< 0x00000002 */
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+#define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk
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+#define DSI_WPCR2_TCLKPREP2_Pos (2U)
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+#define DSI_WPCR2_TCLKPREP2_Msk (0x1UL << DSI_WPCR2_TCLKPREP2_Pos) /*!< 0x00000004 */
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+#define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk
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+#define DSI_WPCR2_TCLKPREP3_Pos (3U)
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+#define DSI_WPCR2_TCLKPREP3_Msk (0x1UL << DSI_WPCR2_TCLKPREP3_Pos) /*!< 0x00000008 */
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+#define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk
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+#define DSI_WPCR2_TCLKPREP4_Pos (4U)
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+#define DSI_WPCR2_TCLKPREP4_Msk (0x1UL << DSI_WPCR2_TCLKPREP4_Pos) /*!< 0x00000010 */
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+#define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk
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+#define DSI_WPCR2_TCLKPREP5_Pos (5U)
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+#define DSI_WPCR2_TCLKPREP5_Msk (0x1UL << DSI_WPCR2_TCLKPREP5_Pos) /*!< 0x00000020 */
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+#define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk
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+#define DSI_WPCR2_TCLKPREP6_Pos (6U)
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+#define DSI_WPCR2_TCLKPREP6_Msk (0x1UL << DSI_WPCR2_TCLKPREP6_Pos) /*!< 0x00000040 */
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+#define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk
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+#define DSI_WPCR2_TCLKPREP7_Pos (7U)
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+#define DSI_WPCR2_TCLKPREP7_Msk (0x1UL << DSI_WPCR2_TCLKPREP7_Pos) /*!< 0x00000080 */
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+#define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk
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+
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+#define DSI_WPCR2_TCLKZERO_Pos (8U)
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+#define DSI_WPCR2_TCLKZERO_Msk (0xFFUL << DSI_WPCR2_TCLKZERO_Pos) /*!< 0x0000FF00 */
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+#define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk /*!< t-CLKZERO */
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+#define DSI_WPCR2_TCLKZERO0_Pos (8U)
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+#define DSI_WPCR2_TCLKZERO0_Msk (0x1UL << DSI_WPCR2_TCLKZERO0_Pos) /*!< 0x00000100 */
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+#define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk
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+#define DSI_WPCR2_TCLKZERO1_Pos (9U)
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+#define DSI_WPCR2_TCLKZERO1_Msk (0x1UL << DSI_WPCR2_TCLKZERO1_Pos) /*!< 0x00000200 */
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+#define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk
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+#define DSI_WPCR2_TCLKZERO2_Pos (10U)
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+#define DSI_WPCR2_TCLKZERO2_Msk (0x1UL << DSI_WPCR2_TCLKZERO2_Pos) /*!< 0x00000400 */
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+#define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk
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+#define DSI_WPCR2_TCLKZERO3_Pos (11U)
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+#define DSI_WPCR2_TCLKZERO3_Msk (0x1UL << DSI_WPCR2_TCLKZERO3_Pos) /*!< 0x00000800 */
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+#define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk
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+#define DSI_WPCR2_TCLKZERO4_Pos (12U)
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+#define DSI_WPCR2_TCLKZERO4_Msk (0x1UL << DSI_WPCR2_TCLKZERO4_Pos) /*!< 0x00001000 */
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+#define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk
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+#define DSI_WPCR2_TCLKZERO5_Pos (13U)
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+#define DSI_WPCR2_TCLKZERO5_Msk (0x1UL << DSI_WPCR2_TCLKZERO5_Pos) /*!< 0x00002000 */
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+#define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk
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+#define DSI_WPCR2_TCLKZERO6_Pos (14U)
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+#define DSI_WPCR2_TCLKZERO6_Msk (0x1UL << DSI_WPCR2_TCLKZERO6_Pos) /*!< 0x00004000 */
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+#define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk
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+#define DSI_WPCR2_TCLKZERO7_Pos (15U)
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+#define DSI_WPCR2_TCLKZERO7_Msk (0x1UL << DSI_WPCR2_TCLKZERO7_Pos) /*!< 0x00008000 */
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+#define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk
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+
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+#define DSI_WPCR2_THSPREP_Pos (16U)
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+#define DSI_WPCR2_THSPREP_Msk (0xFFUL << DSI_WPCR2_THSPREP_Pos) /*!< 0x00FF0000 */
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+#define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk /*!< t-HSPREP */
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+#define DSI_WPCR2_THSPREP0_Pos (16U)
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+#define DSI_WPCR2_THSPREP0_Msk (0x1UL << DSI_WPCR2_THSPREP0_Pos) /*!< 0x00010000 */
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+#define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk
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+#define DSI_WPCR2_THSPREP1_Pos (17U)
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+#define DSI_WPCR2_THSPREP1_Msk (0x1UL << DSI_WPCR2_THSPREP1_Pos) /*!< 0x00020000 */
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+#define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk
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+#define DSI_WPCR2_THSPREP2_Pos (18U)
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+#define DSI_WPCR2_THSPREP2_Msk (0x1UL << DSI_WPCR2_THSPREP2_Pos) /*!< 0x00040000 */
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+#define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk
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+#define DSI_WPCR2_THSPREP3_Pos (19U)
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+#define DSI_WPCR2_THSPREP3_Msk (0x1UL << DSI_WPCR2_THSPREP3_Pos) /*!< 0x00080000 */
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+#define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk
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+#define DSI_WPCR2_THSPREP4_Pos (20U)
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+#define DSI_WPCR2_THSPREP4_Msk (0x1UL << DSI_WPCR2_THSPREP4_Pos) /*!< 0x00100000 */
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+#define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk
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+#define DSI_WPCR2_THSPREP5_Pos (21U)
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+#define DSI_WPCR2_THSPREP5_Msk (0x1UL << DSI_WPCR2_THSPREP5_Pos) /*!< 0x00200000 */
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+#define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk
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+#define DSI_WPCR2_THSPREP6_Pos (22U)
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+#define DSI_WPCR2_THSPREP6_Msk (0x1UL << DSI_WPCR2_THSPREP6_Pos) /*!< 0x00400000 */
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+#define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk
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+#define DSI_WPCR2_THSPREP7_Pos (23U)
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+#define DSI_WPCR2_THSPREP7_Msk (0x1UL << DSI_WPCR2_THSPREP7_Pos) /*!< 0x00800000 */
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+#define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk
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+
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+#define DSI_WPCR2_THSTRAIL_Pos (24U)
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+#define DSI_WPCR2_THSTRAIL_Msk (0xFFUL << DSI_WPCR2_THSTRAIL_Pos) /*!< 0xFF000000 */
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+#define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk /*!< t-HSTRAIL */
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+#define DSI_WPCR2_THSTRAIL0_Pos (24U)
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+#define DSI_WPCR2_THSTRAIL0_Msk (0x1UL << DSI_WPCR2_THSTRAIL0_Pos) /*!< 0x01000000 */
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+#define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk
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+#define DSI_WPCR2_THSTRAIL1_Pos (25U)
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+#define DSI_WPCR2_THSTRAIL1_Msk (0x1UL << DSI_WPCR2_THSTRAIL1_Pos) /*!< 0x02000000 */
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+#define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk
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+#define DSI_WPCR2_THSTRAIL2_Pos (26U)
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+#define DSI_WPCR2_THSTRAIL2_Msk (0x1UL << DSI_WPCR2_THSTRAIL2_Pos) /*!< 0x04000000 */
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+#define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk
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+#define DSI_WPCR2_THSTRAIL3_Pos (27U)
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+#define DSI_WPCR2_THSTRAIL3_Msk (0x1UL << DSI_WPCR2_THSTRAIL3_Pos) /*!< 0x08000000 */
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+#define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk
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+#define DSI_WPCR2_THSTRAIL4_Pos (28U)
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+#define DSI_WPCR2_THSTRAIL4_Msk (0x1UL << DSI_WPCR2_THSTRAIL4_Pos) /*!< 0x10000000 */
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+#define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk
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+#define DSI_WPCR2_THSTRAIL5_Pos (29U)
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+#define DSI_WPCR2_THSTRAIL5_Msk (0x1UL << DSI_WPCR2_THSTRAIL5_Pos) /*!< 0x20000000 */
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+#define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk
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+#define DSI_WPCR2_THSTRAIL6_Pos (30U)
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+#define DSI_WPCR2_THSTRAIL6_Msk (0x1UL << DSI_WPCR2_THSTRAIL6_Pos) /*!< 0x40000000 */
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+#define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk
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+#define DSI_WPCR2_THSTRAIL7_Pos (31U)
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+#define DSI_WPCR2_THSTRAIL7_Msk (0x1UL << DSI_WPCR2_THSTRAIL7_Pos) /*!< 0x80000000 */
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+#define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk
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+
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+/******************* Bit definition for DSI_WPCR3 register ***************/
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+#define DSI_WPCR3_THSZERO_Pos (0U)
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+#define DSI_WPCR3_THSZERO_Msk (0xFFUL << DSI_WPCR3_THSZERO_Pos) /*!< 0x000000FF */
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+#define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk /*!< t-HSZERO */
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+#define DSI_WPCR3_THSZERO0_Pos (0U)
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+#define DSI_WPCR3_THSZERO0_Msk (0x1UL << DSI_WPCR3_THSZERO0_Pos) /*!< 0x00000001 */
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+#define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk
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+#define DSI_WPCR3_THSZERO1_Pos (1U)
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+#define DSI_WPCR3_THSZERO1_Msk (0x1UL << DSI_WPCR3_THSZERO1_Pos) /*!< 0x00000002 */
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+#define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk
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+#define DSI_WPCR3_THSZERO2_Pos (2U)
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+#define DSI_WPCR3_THSZERO2_Msk (0x1UL << DSI_WPCR3_THSZERO2_Pos) /*!< 0x00000004 */
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+#define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk
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+#define DSI_WPCR3_THSZERO3_Pos (3U)
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+#define DSI_WPCR3_THSZERO3_Msk (0x1UL << DSI_WPCR3_THSZERO3_Pos) /*!< 0x00000008 */
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+#define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk
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+#define DSI_WPCR3_THSZERO4_Pos (4U)
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+#define DSI_WPCR3_THSZERO4_Msk (0x1UL << DSI_WPCR3_THSZERO4_Pos) /*!< 0x00000010 */
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+#define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk
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+#define DSI_WPCR3_THSZERO5_Pos (5U)
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+#define DSI_WPCR3_THSZERO5_Msk (0x1UL << DSI_WPCR3_THSZERO5_Pos) /*!< 0x00000020 */
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+#define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk
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+#define DSI_WPCR3_THSZERO6_Pos (6U)
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+#define DSI_WPCR3_THSZERO6_Msk (0x1UL << DSI_WPCR3_THSZERO6_Pos) /*!< 0x00000040 */
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+#define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk
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+#define DSI_WPCR3_THSZERO7_Pos (7U)
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+#define DSI_WPCR3_THSZERO7_Msk (0x1UL << DSI_WPCR3_THSZERO7_Pos) /*!< 0x00000080 */
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+#define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk
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+
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+#define DSI_WPCR3_TLPXD_Pos (8U)
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+#define DSI_WPCR3_TLPXD_Msk (0xFFUL << DSI_WPCR3_TLPXD_Pos) /*!< 0x0000FF00 */
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+#define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk /*!< t-LPXD */
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+#define DSI_WPCR3_TLPXD0_Pos (8U)
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+#define DSI_WPCR3_TLPXD0_Msk (0x1UL << DSI_WPCR3_TLPXD0_Pos) /*!< 0x00000100 */
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+#define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk
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+#define DSI_WPCR3_TLPXD1_Pos (9U)
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+#define DSI_WPCR3_TLPXD1_Msk (0x1UL << DSI_WPCR3_TLPXD1_Pos) /*!< 0x00000200 */
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+#define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk
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+#define DSI_WPCR3_TLPXD2_Pos (10U)
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+#define DSI_WPCR3_TLPXD2_Msk (0x1UL << DSI_WPCR3_TLPXD2_Pos) /*!< 0x00000400 */
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+#define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk
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+#define DSI_WPCR3_TLPXD3_Pos (11U)
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+#define DSI_WPCR3_TLPXD3_Msk (0x1UL << DSI_WPCR3_TLPXD3_Pos) /*!< 0x00000800 */
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+#define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk
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+#define DSI_WPCR3_TLPXD4_Pos (12U)
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+#define DSI_WPCR3_TLPXD4_Msk (0x1UL << DSI_WPCR3_TLPXD4_Pos) /*!< 0x00001000 */
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+#define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk
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+#define DSI_WPCR3_TLPXD5_Pos (13U)
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+#define DSI_WPCR3_TLPXD5_Msk (0x1UL << DSI_WPCR3_TLPXD5_Pos) /*!< 0x00002000 */
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+#define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk
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+#define DSI_WPCR3_TLPXD6_Pos (14U)
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+#define DSI_WPCR3_TLPXD6_Msk (0x1UL << DSI_WPCR3_TLPXD6_Pos) /*!< 0x00004000 */
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+#define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk
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+#define DSI_WPCR3_TLPXD7_Pos (15U)
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+#define DSI_WPCR3_TLPXD7_Msk (0x1UL << DSI_WPCR3_TLPXD7_Pos) /*!< 0x00008000 */
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+#define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk
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+
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+#define DSI_WPCR3_THSEXIT_Pos (16U)
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+#define DSI_WPCR3_THSEXIT_Msk (0xFFUL << DSI_WPCR3_THSEXIT_Pos) /*!< 0x00FF0000 */
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+#define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk /*!< t-HSEXIT */
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+#define DSI_WPCR3_THSEXIT0_Pos (16U)
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+#define DSI_WPCR3_THSEXIT0_Msk (0x1UL << DSI_WPCR3_THSEXIT0_Pos) /*!< 0x00010000 */
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+#define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk
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+#define DSI_WPCR3_THSEXIT1_Pos (17U)
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+#define DSI_WPCR3_THSEXIT1_Msk (0x1UL << DSI_WPCR3_THSEXIT1_Pos) /*!< 0x00020000 */
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+#define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk
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+#define DSI_WPCR3_THSEXIT2_Pos (18U)
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+#define DSI_WPCR3_THSEXIT2_Msk (0x1UL << DSI_WPCR3_THSEXIT2_Pos) /*!< 0x00040000 */
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+#define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk
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+#define DSI_WPCR3_THSEXIT3_Pos (19U)
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+#define DSI_WPCR3_THSEXIT3_Msk (0x1UL << DSI_WPCR3_THSEXIT3_Pos) /*!< 0x00080000 */
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+#define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk
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+#define DSI_WPCR3_THSEXIT4_Pos (20U)
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+#define DSI_WPCR3_THSEXIT4_Msk (0x1UL << DSI_WPCR3_THSEXIT4_Pos) /*!< 0x00100000 */
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+#define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk
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+#define DSI_WPCR3_THSEXIT5_Pos (21U)
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+#define DSI_WPCR3_THSEXIT5_Msk (0x1UL << DSI_WPCR3_THSEXIT5_Pos) /*!< 0x00200000 */
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+#define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk
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+#define DSI_WPCR3_THSEXIT6_Pos (22U)
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+#define DSI_WPCR3_THSEXIT6_Msk (0x1UL << DSI_WPCR3_THSEXIT6_Pos) /*!< 0x00400000 */
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+#define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk
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+#define DSI_WPCR3_THSEXIT7_Pos (23U)
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+#define DSI_WPCR3_THSEXIT7_Msk (0x1UL << DSI_WPCR3_THSEXIT7_Pos) /*!< 0x00800000 */
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+#define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk
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+
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+#define DSI_WPCR3_TLPXC_Pos (24U)
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+#define DSI_WPCR3_TLPXC_Msk (0xFFUL << DSI_WPCR3_TLPXC_Pos) /*!< 0xFF000000 */
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+#define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk /*!< t-LPXC */
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+#define DSI_WPCR3_TLPXC0_Pos (24U)
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+#define DSI_WPCR3_TLPXC0_Msk (0x1UL << DSI_WPCR3_TLPXC0_Pos) /*!< 0x01000000 */
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+#define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk
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+#define DSI_WPCR3_TLPXC1_Pos (25U)
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+#define DSI_WPCR3_TLPXC1_Msk (0x1UL << DSI_WPCR3_TLPXC1_Pos) /*!< 0x02000000 */
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+#define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk
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+#define DSI_WPCR3_TLPXC2_Pos (26U)
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+#define DSI_WPCR3_TLPXC2_Msk (0x1UL << DSI_WPCR3_TLPXC2_Pos) /*!< 0x04000000 */
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+#define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk
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+#define DSI_WPCR3_TLPXC3_Pos (27U)
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+#define DSI_WPCR3_TLPXC3_Msk (0x1UL << DSI_WPCR3_TLPXC3_Pos) /*!< 0x08000000 */
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+#define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk
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+#define DSI_WPCR3_TLPXC4_Pos (28U)
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+#define DSI_WPCR3_TLPXC4_Msk (0x1UL << DSI_WPCR3_TLPXC4_Pos) /*!< 0x10000000 */
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+#define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk
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+#define DSI_WPCR3_TLPXC5_Pos (29U)
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+#define DSI_WPCR3_TLPXC5_Msk (0x1UL << DSI_WPCR3_TLPXC5_Pos) /*!< 0x20000000 */
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+#define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk
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+#define DSI_WPCR3_TLPXC6_Pos (30U)
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+#define DSI_WPCR3_TLPXC6_Msk (0x1UL << DSI_WPCR3_TLPXC6_Pos) /*!< 0x40000000 */
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+#define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk
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+#define DSI_WPCR3_TLPXC7_Pos (31U)
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+#define DSI_WPCR3_TLPXC7_Msk (0x1UL << DSI_WPCR3_TLPXC7_Pos) /*!< 0x80000000 */
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+#define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk
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+
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+/******************* Bit definition for DSI_WPCR4 register ***************/
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+#define DSI_WPCR4_TCLKPOST_Pos (0U)
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+#define DSI_WPCR4_TCLKPOST_Msk (0xFFUL << DSI_WPCR4_TCLKPOST_Pos) /*!< 0x000000FF */
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+#define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk /*!< t-CLKPOST */
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+#define DSI_WPCR4_TCLKPOST0_Pos (0U)
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+#define DSI_WPCR4_TCLKPOST0_Msk (0x1UL << DSI_WPCR4_TCLKPOST0_Pos) /*!< 0x00000001 */
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+#define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk
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+#define DSI_WPCR4_TCLKPOST1_Pos (1U)
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+#define DSI_WPCR4_TCLKPOST1_Msk (0x1UL << DSI_WPCR4_TCLKPOST1_Pos) /*!< 0x00000002 */
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+#define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk
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+#define DSI_WPCR4_TCLKPOST2_Pos (2U)
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+#define DSI_WPCR4_TCLKPOST2_Msk (0x1UL << DSI_WPCR4_TCLKPOST2_Pos) /*!< 0x00000004 */
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+#define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk
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+#define DSI_WPCR4_TCLKPOST3_Pos (3U)
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+#define DSI_WPCR4_TCLKPOST3_Msk (0x1UL << DSI_WPCR4_TCLKPOST3_Pos) /*!< 0x00000008 */
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+#define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk
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+#define DSI_WPCR4_TCLKPOST4_Pos (4U)
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+#define DSI_WPCR4_TCLKPOST4_Msk (0x1UL << DSI_WPCR4_TCLKPOST4_Pos) /*!< 0x00000010 */
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+#define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk
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+#define DSI_WPCR4_TCLKPOST5_Pos (5U)
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+#define DSI_WPCR4_TCLKPOST5_Msk (0x1UL << DSI_WPCR4_TCLKPOST5_Pos) /*!< 0x00000020 */
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+#define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk
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+#define DSI_WPCR4_TCLKPOST6_Pos (6U)
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|
|
+#define DSI_WPCR4_TCLKPOST6_Msk (0x1UL << DSI_WPCR4_TCLKPOST6_Pos) /*!< 0x00000040 */
|
|
|
+#define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk
|
|
|
+#define DSI_WPCR4_TCLKPOST7_Pos (7U)
|
|
|
+#define DSI_WPCR4_TCLKPOST7_Msk (0x1UL << DSI_WPCR4_TCLKPOST7_Pos) /*!< 0x00000080 */
|
|
|
+#define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk
|
|
|
+
|
|
|
+/******************* Bit definition for DSI_WRPCR register ***************/
|
|
|
+#define DSI_WRPCR_PLLEN_Pos (0U)
|
|
|
+#define DSI_WRPCR_PLLEN_Msk (0x1UL << DSI_WRPCR_PLLEN_Pos) /*!< 0x00000001 */
|
|
|
+#define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk /*!< PLL Enable */
|
|
|
+#define DSI_WRPCR_PLL_NDIV_Pos (2U)
|
|
|
+#define DSI_WRPCR_PLL_NDIV_Msk (0x7FUL << DSI_WRPCR_PLL_NDIV_Pos) /*!< 0x000001FC */
|
|
|
+#define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk /*!< PLL Loop Division Factor */
|
|
|
+#define DSI_WRPCR_PLL_NDIV0_Pos (2U)
|
|
|
+#define DSI_WRPCR_PLL_NDIV0_Msk (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos) /*!< 0x00000004 */
|
|
|
+#define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk
|
|
|
+#define DSI_WRPCR_PLL_NDIV1_Pos (3U)
|
|
|
+#define DSI_WRPCR_PLL_NDIV1_Msk (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos) /*!< 0x00000008 */
|
|
|
+#define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk
|
|
|
+#define DSI_WRPCR_PLL_NDIV2_Pos (4U)
|
|
|
+#define DSI_WRPCR_PLL_NDIV2_Msk (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos) /*!< 0x00000010 */
|
|
|
+#define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk
|
|
|
+#define DSI_WRPCR_PLL_NDIV3_Pos (5U)
|
|
|
+#define DSI_WRPCR_PLL_NDIV3_Msk (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos) /*!< 0x00000020 */
|
|
|
+#define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk
|
|
|
+#define DSI_WRPCR_PLL_NDIV4_Pos (6U)
|
|
|
+#define DSI_WRPCR_PLL_NDIV4_Msk (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos) /*!< 0x00000040 */
|
|
|
+#define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk
|
|
|
+#define DSI_WRPCR_PLL_NDIV5_Pos (7U)
|
|
|
+#define DSI_WRPCR_PLL_NDIV5_Msk (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos) /*!< 0x00000080 */
|
|
|
+#define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk
|
|
|
+#define DSI_WRPCR_PLL_NDIV6_Pos (8U)
|
|
|
+#define DSI_WRPCR_PLL_NDIV6_Msk (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos) /*!< 0x00000100 */
|
|
|
+#define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk
|
|
|
+
|
|
|
+#define DSI_WRPCR_PLL_IDF_Pos (11U)
|
|
|
+#define DSI_WRPCR_PLL_IDF_Msk (0xFUL << DSI_WRPCR_PLL_IDF_Pos) /*!< 0x00007800 */
|
|
|
+#define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk /*!< PLL Input Division Factor */
|
|
|
+#define DSI_WRPCR_PLL_IDF0_Pos (11U)
|
|
|
+#define DSI_WRPCR_PLL_IDF0_Msk (0x1UL << DSI_WRPCR_PLL_IDF0_Pos) /*!< 0x00000800 */
|
|
|
+#define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk
|
|
|
+#define DSI_WRPCR_PLL_IDF1_Pos (12U)
|
|
|
+#define DSI_WRPCR_PLL_IDF1_Msk (0x1UL << DSI_WRPCR_PLL_IDF1_Pos) /*!< 0x00001000 */
|
|
|
+#define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk
|
|
|
+#define DSI_WRPCR_PLL_IDF2_Pos (13U)
|
|
|
+#define DSI_WRPCR_PLL_IDF2_Msk (0x1UL << DSI_WRPCR_PLL_IDF2_Pos) /*!< 0x00002000 */
|
|
|
+#define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk
|
|
|
+#define DSI_WRPCR_PLL_IDF3_Pos (14U)
|
|
|
+#define DSI_WRPCR_PLL_IDF3_Msk (0x1UL << DSI_WRPCR_PLL_IDF3_Pos) /*!< 0x00004000 */
|
|
|
+#define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk
|
|
|
+
|
|
|
+#define DSI_WRPCR_PLL_ODF_Pos (16U)
|
|
|
+#define DSI_WRPCR_PLL_ODF_Msk (0x3UL << DSI_WRPCR_PLL_ODF_Pos) /*!< 0x00030000 */
|
|
|
+#define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk /*!< PLL Output Division Factor */
|
|
|
+#define DSI_WRPCR_PLL_ODF0_Pos (16U)
|
|
|
+#define DSI_WRPCR_PLL_ODF0_Msk (0x1UL << DSI_WRPCR_PLL_ODF0_Pos) /*!< 0x00010000 */
|
|
|
+#define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk
|
|
|
+#define DSI_WRPCR_PLL_ODF1_Pos (17U)
|
|
|
+#define DSI_WRPCR_PLL_ODF1_Msk (0x1UL << DSI_WRPCR_PLL_ODF1_Pos) /*!< 0x00020000 */
|
|
|
+#define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk
|
|
|
+
|
|
|
+#define DSI_WRPCR_REGEN_Pos (24U)
|
|
|
+#define DSI_WRPCR_REGEN_Msk (0x1UL << DSI_WRPCR_REGEN_Pos) /*!< 0x01000000 */
|
|
|
+#define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk /*!< Regulator Enable */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/** @addtogroup Exported_macros
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+/******************************* ADC Instances ********************************/
|
|
|
+#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
|
|
|
+ ((__INSTANCE__) == ADC2) || \
|
|
|
+ ((__INSTANCE__) == ADC3))
|
|
|
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
|
|
|
+
|
|
|
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
|
|
|
+
|
|
|
+/******************************* CAN Instances ********************************/
|
|
|
+#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
|
|
|
+ ((__INSTANCE__) == CAN2) || \
|
|
|
+ ((__INSTANCE__) == CAN3))
|
|
|
+/******************************* CRC Instances ********************************/
|
|
|
+#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
|
|
|
+
|
|
|
+/******************************* DAC Instances ********************************/
|
|
|
+#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1)
|
|
|
+
|
|
|
+/******************************* DCMI Instances *******************************/
|
|
|
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
|
|
|
+
|
|
|
+/****************************** DFSDM Instances *******************************/
|
|
|
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
|
|
|
+ ((INSTANCE) == DFSDM1_Filter1) || \
|
|
|
+ ((INSTANCE) == DFSDM1_Filter2) || \
|
|
|
+ ((INSTANCE) == DFSDM1_Filter3))
|
|
|
+
|
|
|
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
|
|
|
+ ((INSTANCE) == DFSDM1_Channel1) || \
|
|
|
+ ((INSTANCE) == DFSDM1_Channel2) || \
|
|
|
+ ((INSTANCE) == DFSDM1_Channel3) || \
|
|
|
+ ((INSTANCE) == DFSDM1_Channel4) || \
|
|
|
+ ((INSTANCE) == DFSDM1_Channel5) || \
|
|
|
+ ((INSTANCE) == DFSDM1_Channel6) || \
|
|
|
+ ((INSTANCE) == DFSDM1_Channel7))
|
|
|
+
|
|
|
+/******************************* DMA2D Instances *******************************/
|
|
|
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
|
|
|
+
|
|
|
+/******************************** DMA Instances *******************************/
|
|
|
+#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
|
|
|
+ ((__INSTANCE__) == DMA1_Stream1) || \
|
|
|
+ ((__INSTANCE__) == DMA1_Stream2) || \
|
|
|
+ ((__INSTANCE__) == DMA1_Stream3) || \
|
|
|
+ ((__INSTANCE__) == DMA1_Stream4) || \
|
|
|
+ ((__INSTANCE__) == DMA1_Stream5) || \
|
|
|
+ ((__INSTANCE__) == DMA1_Stream6) || \
|
|
|
+ ((__INSTANCE__) == DMA1_Stream7) || \
|
|
|
+ ((__INSTANCE__) == DMA2_Stream0) || \
|
|
|
+ ((__INSTANCE__) == DMA2_Stream1) || \
|
|
|
+ ((__INSTANCE__) == DMA2_Stream2) || \
|
|
|
+ ((__INSTANCE__) == DMA2_Stream3) || \
|
|
|
+ ((__INSTANCE__) == DMA2_Stream4) || \
|
|
|
+ ((__INSTANCE__) == DMA2_Stream5) || \
|
|
|
+ ((__INSTANCE__) == DMA2_Stream6) || \
|
|
|
+ ((__INSTANCE__) == DMA2_Stream7))
|
|
|
+
|
|
|
+/******************************* GPIO Instances *******************************/
|
|
|
+#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
|
|
|
+ ((__INSTANCE__) == GPIOB) || \
|
|
|
+ ((__INSTANCE__) == GPIOC) || \
|
|
|
+ ((__INSTANCE__) == GPIOD) || \
|
|
|
+ ((__INSTANCE__) == GPIOE) || \
|
|
|
+ ((__INSTANCE__) == GPIOF) || \
|
|
|
+ ((__INSTANCE__) == GPIOG) || \
|
|
|
+ ((__INSTANCE__) == GPIOH) || \
|
|
|
+ ((__INSTANCE__) == GPIOI) || \
|
|
|
+ ((__INSTANCE__) == GPIOJ) || \
|
|
|
+ ((__INSTANCE__) == GPIOK))
|
|
|
+
|
|
|
+#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
|
|
|
+ ((__INSTANCE__) == GPIOB) || \
|
|
|
+ ((__INSTANCE__) == GPIOC) || \
|
|
|
+ ((__INSTANCE__) == GPIOD) || \
|
|
|
+ ((__INSTANCE__) == GPIOE) || \
|
|
|
+ ((__INSTANCE__) == GPIOF) || \
|
|
|
+ ((__INSTANCE__) == GPIOG) || \
|
|
|
+ ((__INSTANCE__) == GPIOH) || \
|
|
|
+ ((__INSTANCE__) == GPIOI) || \
|
|
|
+ ((__INSTANCE__) == GPIOJ) || \
|
|
|
+ ((__INSTANCE__) == GPIOK))
|
|
|
+
|
|
|
+/****************************** CEC Instances *********************************/
|
|
|
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
|
|
|
+
|
|
|
+/****************************** QSPI Instances *********************************/
|
|
|
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
|
|
|
+
|
|
|
+
|
|
|
+/******************************** I2C Instances *******************************/
|
|
|
+#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
|
|
|
+ ((__INSTANCE__) == I2C2) || \
|
|
|
+ ((__INSTANCE__) == I2C3) || \
|
|
|
+ ((__INSTANCE__) == I2C4))
|
|
|
+
|
|
|
+/****************************** SMBUS Instances *******************************/
|
|
|
+#define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
|
|
|
+ ((__INSTANCE__) == I2C2) || \
|
|
|
+ ((__INSTANCE__) == I2C3) || \
|
|
|
+ ((__INSTANCE__) == I2C4))
|
|
|
+
|
|
|
+
|
|
|
+/******************************** I2S Instances *******************************/
|
|
|
+#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
|
|
|
+ ((__INSTANCE__) == SPI2) || \
|
|
|
+ ((__INSTANCE__) == SPI3))
|
|
|
+
|
|
|
+/******************************* LPTIM Instances ********************************/
|
|
|
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
|
|
|
+
|
|
|
+/****************************** LTDC Instances ********************************/
|
|
|
+#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
|
|
|
+
|
|
|
+/****************************** MDIOS Instances ********************************/
|
|
|
+#define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS)
|
|
|
+
|
|
|
+/****************************** MDIOS Instances ********************************/
|
|
|
+#define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)
|
|
|
+
|
|
|
+
|
|
|
+/******************************* RNG Instances ********************************/
|
|
|
+#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
|
|
|
+
|
|
|
+/****************************** RTC Instances *********************************/
|
|
|
+#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
|
|
|
+
|
|
|
+/******************************* SAI Instances ********************************/
|
|
|
+#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
|
|
|
+ ((__PERIPH__) == SAI1_Block_B) || \
|
|
|
+ ((__PERIPH__) == SAI2_Block_A) || \
|
|
|
+ ((__PERIPH__) == SAI2_Block_B))
|
|
|
+/* Legacy define */
|
|
|
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
|
|
|
+
|
|
|
+/******************************** SDMMC Instances *******************************/
|
|
|
+#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
|
|
|
+ ((__INSTANCE__) == SDMMC2))
|
|
|
+
|
|
|
+/****************************** SPDIFRX Instances *********************************/
|
|
|
+#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
|
|
|
+
|
|
|
+/******************************** SPI Instances *******************************/
|
|
|
+#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
|
|
|
+ ((__INSTANCE__) == SPI2) || \
|
|
|
+ ((__INSTANCE__) == SPI3) || \
|
|
|
+ ((__INSTANCE__) == SPI4) || \
|
|
|
+ ((__INSTANCE__) == SPI5) || \
|
|
|
+ ((__INSTANCE__) == SPI6))
|
|
|
+
|
|
|
+/****************** TIM Instances : All supported instances *******************/
|
|
|
+#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM6) || \
|
|
|
+ ((__INSTANCE__) == TIM7) || \
|
|
|
+ ((__INSTANCE__) == TIM8) || \
|
|
|
+ ((__INSTANCE__) == TIM9) || \
|
|
|
+ ((__INSTANCE__) == TIM10) || \
|
|
|
+ ((__INSTANCE__) == TIM11) || \
|
|
|
+ ((__INSTANCE__) == TIM12) || \
|
|
|
+ ((__INSTANCE__) == TIM13) || \
|
|
|
+ ((__INSTANCE__) == TIM14))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting 32 bits counter ****************/
|
|
|
+#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM5))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting the break function *************/
|
|
|
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM8))
|
|
|
+
|
|
|
+/************** TIM Instances : supporting Break source selection *************/
|
|
|
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM8))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting 2 break inputs *****************/
|
|
|
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM8))
|
|
|
+
|
|
|
+/************* TIM Instances : at least 1 capture/compare channel *************/
|
|
|
+#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8) || \
|
|
|
+ ((__INSTANCE__) == TIM9) || \
|
|
|
+ ((__INSTANCE__) == TIM10) || \
|
|
|
+ ((__INSTANCE__) == TIM11) || \
|
|
|
+ ((__INSTANCE__) == TIM12) || \
|
|
|
+ ((__INSTANCE__) == TIM13) || \
|
|
|
+ ((__INSTANCE__) == TIM14))
|
|
|
+
|
|
|
+/************ TIM Instances : at least 2 capture/compare channels *************/
|
|
|
+#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8) || \
|
|
|
+ ((__INSTANCE__) == TIM9) || \
|
|
|
+ ((__INSTANCE__) == TIM12))
|
|
|
+
|
|
|
+/************ TIM Instances : at least 3 capture/compare channels *************/
|
|
|
+#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/************ TIM Instances : at least 4 capture/compare channels *************/
|
|
|
+#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/****************** TIM Instances : at least 5 capture/compare channels *******/
|
|
|
+#define IS_TIM_CC5_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/****************** TIM Instances : at least 6 capture/compare channels *******/
|
|
|
+#define IS_TIM_CC6_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
|
|
|
+#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
|
|
|
+#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM8) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM6) || \
|
|
|
+ ((__INSTANCE__) == TIM7))
|
|
|
+
|
|
|
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
|
|
|
+#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/******************** TIM Instances : DMA burst feature ***********************/
|
|
|
+#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
|
|
|
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
|
|
|
+ (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting counting mode selection ********/
|
|
|
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting encoder interface **************/
|
|
|
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting OCxREF clear *******************/
|
|
|
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
|
|
|
+ (((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
|
|
|
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
|
|
|
+ (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
|
|
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
|
|
|
+ (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/******************** TIM Instances : Advanced-control timers *****************/
|
|
|
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/******************* TIM Instances : Timer input XOR function *****************/
|
|
|
+#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
|
|
|
+#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM6) || \
|
|
|
+ ((__INSTANCE__) == TIM7) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
|
|
|
+#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8) || \
|
|
|
+ ((__INSTANCE__) == TIM9) || \
|
|
|
+ ((__INSTANCE__) == TIM12))
|
|
|
+
|
|
|
+/***************** TIM Instances : external trigger input available ************/
|
|
|
+#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/****************** TIM Instances : remapping capability **********************/
|
|
|
+#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM11))
|
|
|
+
|
|
|
+/******************* TIM Instances : output(s) available **********************/
|
|
|
+#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
|
|
|
+ ((((__INSTANCE__) == TIM1) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_5) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_6))) \
|
|
|
+ || \
|
|
|
+ (((__INSTANCE__) == TIM2) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \
|
|
|
+ || \
|
|
|
+ (((__INSTANCE__) == TIM3) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \
|
|
|
+ || \
|
|
|
+ (((__INSTANCE__) == TIM4) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \
|
|
|
+ || \
|
|
|
+ (((__INSTANCE__) == TIM5) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \
|
|
|
+ || \
|
|
|
+ (((__INSTANCE__) == TIM8) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_5) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_6))) \
|
|
|
+ || \
|
|
|
+ (((__INSTANCE__) == TIM9) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_2))) \
|
|
|
+ || \
|
|
|
+ (((__INSTANCE__) == TIM10) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \
|
|
|
+ || \
|
|
|
+ (((__INSTANCE__) == TIM11) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \
|
|
|
+ || \
|
|
|
+ (((__INSTANCE__) == TIM12) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_2))) \
|
|
|
+ || \
|
|
|
+ (((__INSTANCE__) == TIM13) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \
|
|
|
+ || \
|
|
|
+ (((__INSTANCE__) == TIM14) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1))))
|
|
|
+
|
|
|
+/************ TIM Instances : complementary output(s) available ***************/
|
|
|
+#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
|
|
|
+ ((((__INSTANCE__) == TIM1) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_3))) \
|
|
|
+ || \
|
|
|
+ (((__INSTANCE__) == TIM8) && \
|
|
|
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
|
|
|
+ ((__CHANNEL__) == TIM_CHANNEL_3))))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
|
|
+#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
|
|
|
+ (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM8) )
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting clock division *****************/
|
|
|
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8) || \
|
|
|
+ ((__INSTANCE__) == TIM9) || \
|
|
|
+ ((__INSTANCE__) == TIM10) || \
|
|
|
+ ((__INSTANCE__) == TIM11) || \
|
|
|
+ ((__INSTANCE__) == TIM12) || \
|
|
|
+ ((__INSTANCE__) == TIM13) || \
|
|
|
+ ((__INSTANCE__) == TIM14))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting repetition counter *************/
|
|
|
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
|
|
|
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8) || \
|
|
|
+ ((__INSTANCE__) == TIM9) || \
|
|
|
+ ((__INSTANCE__) == TIM12))
|
|
|
+
|
|
|
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
|
|
|
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting Hall sensor interface **********/
|
|
|
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM2) || \
|
|
|
+ ((__INSTANCE__) == TIM3) || \
|
|
|
+ ((__INSTANCE__) == TIM4) || \
|
|
|
+ ((__INSTANCE__) == TIM5) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting commutation event generation ***/
|
|
|
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
|
|
|
+ ((__INSTANCE__) == TIM8))
|
|
|
+
|
|
|
+/******************** USART Instances : Synchronous mode **********************/
|
|
|
+#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
|
|
|
+ ((__INSTANCE__) == USART2) || \
|
|
|
+ ((__INSTANCE__) == USART3) || \
|
|
|
+ ((__INSTANCE__) == USART6))
|
|
|
+
|
|
|
+/******************** UART Instances : Asynchronous mode **********************/
|
|
|
+#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
|
|
|
+ ((__INSTANCE__) == USART2) || \
|
|
|
+ ((__INSTANCE__) == USART3) || \
|
|
|
+ ((__INSTANCE__) == UART4) || \
|
|
|
+ ((__INSTANCE__) == UART5) || \
|
|
|
+ ((__INSTANCE__) == USART6) || \
|
|
|
+ ((__INSTANCE__) == UART7) || \
|
|
|
+ ((__INSTANCE__) == UART8))
|
|
|
+
|
|
|
+/****************** UART Instances : Auto Baud Rate detection ****************/
|
|
|
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
|
|
|
+ ((__INSTANCE__) == USART2) || \
|
|
|
+ ((__INSTANCE__) == USART3) || \
|
|
|
+ ((__INSTANCE__) == USART6))
|
|
|
+
|
|
|
+/****************** UART Instances : Driver Enable *****************/
|
|
|
+#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
|
|
|
+ ((__INSTANCE__) == USART2) || \
|
|
|
+ ((__INSTANCE__) == USART3) || \
|
|
|
+ ((__INSTANCE__) == UART4) || \
|
|
|
+ ((__INSTANCE__) == UART5) || \
|
|
|
+ ((__INSTANCE__) == USART6) || \
|
|
|
+ ((__INSTANCE__) == UART7) || \
|
|
|
+ ((__INSTANCE__) == UART8))
|
|
|
+
|
|
|
+/******************** UART Instances : Half-Duplex mode **********************/
|
|
|
+#define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
|
|
|
+ ((__INSTANCE__) == USART2) || \
|
|
|
+ ((__INSTANCE__) == USART3) || \
|
|
|
+ ((__INSTANCE__) == UART4) || \
|
|
|
+ ((__INSTANCE__) == UART5) || \
|
|
|
+ ((__INSTANCE__) == USART6) || \
|
|
|
+ ((__INSTANCE__) == UART7) || \
|
|
|
+ ((__INSTANCE__) == UART8))
|
|
|
+
|
|
|
+/****************** UART Instances : Hardware Flow control ********************/
|
|
|
+#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
|
|
|
+ ((__INSTANCE__) == USART2) || \
|
|
|
+ ((__INSTANCE__) == USART3) || \
|
|
|
+ ((__INSTANCE__) == UART4) || \
|
|
|
+ ((__INSTANCE__) == UART5) || \
|
|
|
+ ((__INSTANCE__) == USART6) || \
|
|
|
+ ((__INSTANCE__) == UART7) || \
|
|
|
+ ((__INSTANCE__) == UART8))
|
|
|
+
|
|
|
+/******************** UART Instances : LIN mode **********************/
|
|
|
+#define IS_UART_LIN_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
|
|
|
+ ((__INSTANCE__) == USART2) || \
|
|
|
+ ((__INSTANCE__) == USART3) || \
|
|
|
+ ((__INSTANCE__) == UART4) || \
|
|
|
+ ((__INSTANCE__) == UART5) || \
|
|
|
+ ((__INSTANCE__) == USART6) || \
|
|
|
+ ((__INSTANCE__) == UART7) || \
|
|
|
+ ((__INSTANCE__) == UART8))
|
|
|
+
|
|
|
+/*********************** UART Instances : Wake-up from Stop mode ***************************/
|
|
|
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
|
|
|
+ ((__INSTANCE__) == USART2) || \
|
|
|
+ ((__INSTANCE__) == USART3) || \
|
|
|
+ ((__INSTANCE__) == UART4) || \
|
|
|
+ ((__INSTANCE__) == UART5) || \
|
|
|
+ ((__INSTANCE__) == USART6) || \
|
|
|
+ ((__INSTANCE__) == UART7) || \
|
|
|
+ ((__INSTANCE__) == UART8))
|
|
|
+
|
|
|
+/********************* UART Instances : Smart card mode ***********************/
|
|
|
+#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
|
|
|
+ ((__INSTANCE__) == USART2) || \
|
|
|
+ ((__INSTANCE__) == USART3) || \
|
|
|
+ ((__INSTANCE__) == USART6))
|
|
|
+
|
|
|
+/*********************** UART Instances : IRDA mode ***************************/
|
|
|
+#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
|
|
|
+ ((__INSTANCE__) == USART2) || \
|
|
|
+ ((__INSTANCE__) == USART3) || \
|
|
|
+ ((__INSTANCE__) == UART4) || \
|
|
|
+ ((__INSTANCE__) == UART5) || \
|
|
|
+ ((__INSTANCE__) == USART6) || \
|
|
|
+ ((__INSTANCE__) == UART7) || \
|
|
|
+ ((__INSTANCE__) == UART8))
|
|
|
+
|
|
|
+/****************************** IWDG Instances ********************************/
|
|
|
+#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
|
|
|
+
|
|
|
+/****************************** WWDG Instances ********************************/
|
|
|
+#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
|
|
|
+
|
|
|
+/*********************** PCD Instances ****************************************/
|
|
|
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
|
|
|
+ ((INSTANCE) == USB_OTG_HS))
|
|
|
+
|
|
|
+/*********************** HCD Instances ****************************************/
|
|
|
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
|
|
|
+ ((INSTANCE) == USB_OTG_HS))
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* For a painless codes migration between the STM32F7xx device product */
|
|
|
+/* lines, the aliases defined below are put in place to overcome the */
|
|
|
+/* differences in the interrupt handlers and IRQn definitions. */
|
|
|
+/* No need to update developed interrupt code when moving across */
|
|
|
+/* product lines within the same STM32F7 Family */
|
|
|
+/******************************************************************************/
|
|
|
+
|
|
|
+/* Aliases for __IRQn */
|
|
|
+#define HASH_RNG_IRQn RNG_IRQn
|
|
|
+
|
|
|
+/* Aliases for __IRQHandler */
|
|
|
+#define HASH_RNG_IRQHandler RNG_IRQHandler
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+#ifdef __cplusplus
|
|
|
+}
|
|
|
+#endif /* __cplusplus */
|
|
|
+
|
|
|
+#endif /* __STM32F769xx_H */
|
|
|
+
|
|
|
+
|
