#if 0
/*
 * max14830.h
 *
 *  Created on: Oct 25, 2024
 *      Author: Invcuser_102
 */

#ifndef SPI_UART_MAX14830_H_
#define SPI_UART_MAX14830_H_

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>

/*
#define CSN_Pin GPIO_PIN_11
#define CSN_GPIO_Port GPIOA
#define IRQ_Pin GPIO_PIN_4
#define IRQ_GPIO_Port GPIOJ
#define IRQ_EXTI_IRQn EXTI4_IRQn
#define RST_Pin GPIO_PIN_3
#define RST_GPIO_Port GPIOJ
 */
#define MAX14830_REF_FREQ  44236800    //3686400  //Mhz  44236800

#define MAX14830_NAME           "MAX14830"
#define MAX14830_MAJOR          204
#define MAX14830_MINOR          209
#define MAX14830_UART_NRMAX     16
#define MAX14830_RETRY_COUNT    20
#define MAX_TX_LEN 32  //bytes

/* MAX14830 register definitions */
#define MAX14830_RHR_REG            (0x00) /* RX FIFO */
#define MAX14830_THR_REG            (0x00) /* TX FIFO */
#define MAX14830_IRQEN_REG      (0x01) /* IRQ enable */
#define MAX14830_IRQSTS_REG     (0x02) /* IRQ status */
#define MAX14830_LSR_IRQEN_REG      (0x03) /* LSR IRQ enable */
#define MAX14830_LSR_IRQSTS_REG     (0x04) /* LSR IRQ status */
#define MAX14830_REG_05         (0x05)
#define MAX14830_SPCHR_IRQEN_REG        MAX14830_REG_05 /* Special char IRQ en */
#define MAX14830_SPCHR_IRQSTS_REG   (0x06) /* Special char IRQ status */
#define MAX14830_STS_IRQEN_REG      (0x07) /* Status IRQ enable */
#define MAX14830_STS_IRQSTS_REG     (0x08) /* Status IRQ status */
#define MAX14830_MODE1_REG      (0x09) /* MODE1 */
#define MAX14830_MODE2_REG      (0x0a) /* MODE2 */
#define MAX14830_LCR_REG            (0x0B) /* LCR */
#define MAX14830_RXTO_REG       (0x0c) /* RX timeout */
#define MAX14830_HDPIXDELAY_REG     (0x0d) /* Auto transceiver delays */
#define MAX14830_IRDA_REG       (0x0e) /* IRDA settings */
#define MAX14830_FLOWLVL_REG        (0x0f) /* Flow control levels */
#define MAX14830_FIFOTRIGLVL_REG        (0x10) /* FIFO IRQ trigger levels */
#define MAX14830_TXFIFOLVL_REG      (0x11) /* TX FIFO level */
#define MAX14830_RXFIFOLVL_REG      (0x12) /* RX FIFO level */
#define MAX14830_FLOWCTRL_REG       (0x13) /* Flow control */
#define MAX14830_XON1_REG       (0x14) /* XON1 character */
#define MAX14830_XON2_REG       (0x15) /* XON2 character */
#define MAX14830_XOFF1_REG      (0x16) /* XOFF1 character */
#define MAX14830_XOFF2_REG      (0x17) /* XOFF2 character */
#define MAX14830_GPIOCFG_REG        (0x18) /* GPIO config */
#define MAX14830_GPIODATA_REG       (0x19) /* GPIO data */
#define MAX14830_PLLCFG_REG     (0x1a) /* PLL config */
#define MAX14830_BRGCFG_REG     (0x1b) /* Baud rate generator conf */
#define MAX14830_BRGDIVLSB_REG      (0x1c) /* Baud rate divisor LSB */
#define MAX14830_BRGDIVMSB_REG      (0x1d) /* Baud rate divisor MSB */
#define MAX14830_CLKSRC_REG     (0x1e) /* Clock source */
#define MAX14830_REG_1F         (0x1f)

#define MAX14830_REVID_REG      MAX14830_REG_1F /* Revision ID */

#define MAX14830_GLOBALIRQ_REG      MAX14830_REG_1F /* Global IRQ (RO) */
#define MAX14830_GLOBALCMD_REG      MAX14830_REG_1F /* Global Command (WO) */

/* Extended registers */
#define MAX14830_SPI_REVID_EXTREG   MAX14830_REG_05 /* Revision ID */
#define MAX14830_I2C_REVID_EXTREG   (0x25) /* Revision ID */

/* IRQ register bits */
#define MAX14830_IRQ_LSR_BIT        (1 << 0) /* LSR interrupt */
#define MAX14830_IRQ_SPCHR_BIT      (1 << 1) /* Special char interrupt */
#define MAX14830_IRQ_STS_BIT        (1 << 2) /* Status interrupt */
#define MAX14830_IRQ_RXFIFO_BIT     (1 << 3) /* RX FIFO interrupt */
#define MAX14830_IRQ_TXFIFO_BIT     (1 << 4) /* TX FIFO interrupt */
#define MAX14830_IRQ_TXEMPTY_BIT        (1 << 5) /* TX FIFO empty interrupt */
#define MAX14830_IRQ_RXEMPTY_BIT        (1 << 6) /* RX FIFO empty interrupt */
#define MAX14830_IRQ_CTS_BIT        (1 << 7) /* CTS interrupt */

/* LSR register bits */
#define MAX14830_LSR_RXTO_BIT       (1 << 0) /* RX timeout */
#define MAX14830_LSR_RXOVR_BIT      (1 << 1) /* RX overrun */
#define MAX14830_LSR_RXPAR_BIT      (1 << 2) /* RX parity error */
#define MAX14830_LSR_FRERR_BIT      (1 << 3) /* Frame error */
#define MAX14830_LSR_RXBRK_BIT      (1 << 4) /* RX break */
#define MAX14830_LSR_RXNOISE_BIT        (1 << 5) /* RX noise */
#define MAX14830_LSR_CTS_BIT        (1 << 7) /* CTS pin state */

/* Special character register bits */
#define MAX14830_SPCHR_XON1_BIT     (1 << 0) /* XON1 character */
#define MAX14830_SPCHR_XON2_BIT     (1 << 1) /* XON2 character */
#define MAX14830_SPCHR_XOFF1_BIT        (1 << 2) /* XOFF1 character */
#define MAX14830_SPCHR_XOFF2_BIT        (1 << 3) /* XOFF2 character */
#define MAX14830_SPCHR_BREAK_BIT        (1 << 4) /* RX break */
#define MAX14830_SPCHR_MULTIDROP_BIT    (1 << 5) /* 9-bit multidrop addr char */

/* Status register bits */
#define MAX14830_STS_GPIO0_BIT      (1 << 0) /* GPIO 0 interrupt */
#define MAX14830_STS_GPIO1_BIT      (1 << 1) /* GPIO 1 interrupt */
#define MAX14830_STS_GPIO2_BIT      (1 << 2) /* GPIO 2 interrupt */
#define MAX14830_STS_GPIO3_BIT      (1 << 3) /* GPIO 3 interrupt */
#define MAX14830_STS_CLKREADY_BIT   (1 << 5) /* Clock ready */
#define MAX14830_STS_SLEEP_BIT      (1 << 6) /* Sleep interrupt */

/* MODE1 register bits */
#define MAX14830_MODE1_RXDIS_BIT        (1 << 0) /* RX disable */
#define MAX14830_MODE1_TXDIS_BIT        (1 << 1) /* TX disable */
#define MAX14830_MODE1_TXHIZ_BIT        (1 << 2) /* TX pin three-state */
#define MAX14830_MODE1_RTSHIZ_BIT   (1 << 3) /* RTS pin three-state */
#define MAX14830_MODE1_TRNSCVCTRL_BIT   (1 << 4) /* Transceiver ctrl enable */
#define MAX14830_MODE1_FORCESLEEP_BIT   (1 << 5) /* Force sleep mode */
#define MAX14830_MODE1_AUTOSLEEP_BIT    (1 << 6) /* Auto sleep enable */
#define MAX14830_MODE1_IRQSEL_BIT   (1 << 7) /* IRQ pin enable */

/* MODE2 register bits */
#define MAX14830_MODE2_RST_BIT      (1 << 0) /* Chip reset */
#define MAX14830_MODE2_FIFORST_BIT  (1 << 1) /* FIFO reset */
#define MAX14830_MODE2_RXTRIGINV_BIT    (1 << 2) /* RX FIFO INT invert */
#define MAX14830_MODE2_RXEMPTINV_BIT    (1 << 3) /* RX FIFO empty INT invert */
#define MAX14830_MODE2_SPCHR_BIT        (1 << 4) /* Special chr detect enable */
#define MAX14830_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
#define MAX14830_MODE2_MULTIDROP_BIT    (1 << 6) /* 9-bit multidrop enable */
#define MAX14830_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */

/* LCR register bits */
#define MAX14830_LCR_LENGTH0_BIT        (1 << 0) /* Word length bit 0 */
#define MAX14830_LCR_LENGTH1_BIT        (1 << 1) /* Word length bit 1
 *
 * Word length bits table:
 * 00 -> 5 bit words
 * 01 -> 6 bit words
 * 10 -> 7 bit words
 * 11 -> 8 bit words
 */
#define MAX14830_LCR_STOPLEN_BIT        (1 << 2) /* STOP length bit
 *
 * STOP length bit table:
 * 0 -> 1 stop bit
 * 1 -> 1-1.5 stop bits if
 *      word length is 5,
 *      2 stop bits otherwise
 */
#define MAX14830_LCR_PARITY_BIT     (1 << 3) /* Parity bit enable */
#define MAX14830_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
#define MAX14830_LCR_FORCEPARITY_BIT    (1 << 5) /* 9-bit multidrop parity */
#define MAX14830_LCR_TXBREAK_BIT        (1 << 6) /* TX break enable */
#define MAX14830_LCR_RTS_BIT        (1 << 7) /* RTS pin control */

/* IRDA register bits */
#define MAX14830_IRDA_IRDAEN_BIT        (1 << 0) /* IRDA mode enable */
#define MAX14830_IRDA_SIR_BIT       (1 << 1) /* SIR mode enable */

/* Flow control trigger level register masks */
#define MAX14830_FLOWLVL_HALT_MASK  (0x000f) /* Flow control halt level */
#define MAX14830_FLOWLVL_RES_MASK   (0x00f0) /* Flow control resume level */
#define MAX14830_FLOWLVL_HALT(words)    ((words / 8) & 0x0f)
#define MAX14830_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)

/* FIFO interrupt trigger level register masks */
#define MAX14830_FIFOTRIGLVL_TX_MASK    (0x0f) /* TX FIFO trigger level */
#define MAX14830_FIFOTRIGLVL_RX_MASK    (0xf0) /* RX FIFO trigger level */
#define MAX14830_FIFOTRIGLVL_TX(words)  ((words / 8) & 0x0f)
#define MAX14830_FIFOTRIGLVL_RX(words)  (((words / 8) & 0x0f) << 4)

/* Flow control register bits */
#define MAX14830_FLOWCTRL_AUTORTS_BIT   (1 << 0) /* Auto RTS flow ctrl enable */
#define MAX14830_FLOWCTRL_AUTOCTS_BIT   (1 << 1) /* Auto CTS flow ctrl enable */
#define MAX14830_FLOWCTRL_GPIADDR_BIT   (1 << 2) /* Enables that GPIO inputs
 * are used in conjunction with
 * XOFF2 for definition of
 * special character */
#define MAX14830_FLOWCTRL_SWFLOWEN_BIT  (1 << 3) /* Auto SW flow ctrl enable */
#define MAX14830_FLOWCTRL_SWFLOW0_BIT   (1 << 4) /* SWFLOW bit 0 */
#define MAX14830_FLOWCTRL_SWFLOW1_BIT   (1 << 5) /* SWFLOW bit 1
 *
 * SWFLOW bits 1 & 0 table:
 * 00 -> no transmitter flow
 *       control
 * 01 -> receiver compares
 *       XON2 and XOFF2
 *       and controls
 *       transmitter
 * 10 -> receiver compares
 *       XON1 and XOFF1
 *       and controls
 *       transmitter
 * 11 -> receiver compares
 *       XON1, XON2, XOFF1 and
 *       XOFF2 and controls
 *       transmitter
 */
#define MAX14830_FLOWCTRL_SWFLOW2_BIT   (1 << 6) /* SWFLOW bit 2 */
#define MAX14830_FLOWCTRL_SWFLOW3_BIT   (1 << 7) /* SWFLOW bit 3
 *
 * SWFLOW bits 3 & 2 table:
 * 00 -> no received flow
 *       control
 * 01 -> transmitter generates
 *       XON2 and XOFF2
 * 10 -> transmitter generates
 *       XON1 and XOFF1
 * 11 -> transmitter generates
 *       XON1, XON2, XOFF1 and
 *       XOFF2
 */

/* PLL configuration register masks */
#define MAX14830_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
#define MAX14830_PLLCFG_PLLFACTOR_MASK  (0xc0) /* PLL multiplication factor */

/* Baud rate generator configuration register bits */
#define MAX14830_BRGCFG_2XMODE_BIT  (1 << 4) /* Double baud rate */
#define MAX14830_BRGCFG_4XMODE_BIT  (1 << 5) /* Quadruple baud rate */

/* Clock source register bits */
#define MAX14830_CLKSRC_CRYST_BIT   (1 << 1) /* Crystal osc enable */
#define MAX14830_CLKSRC_PLL_BIT     (1 << 2) /* PLL enable */
#define MAX14830_CLKSRC_PLLBYP_BIT  (1 << 3) /* PLL bypass */
#define MAX14830_CLKSRC_EXTCLK_BIT  (1 << 4) /* External clock enable */
#define MAX14830_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */

/* Global commands */
#define MAX14830_EXTREG_ENBL        (0xce)
#define MAX14830_EXTREG_DSBL        (0xcd)

/* Misc definitions */
#define MAX14830_FIFO_SIZE      (128)
#define MAX14830_REV_MASK       (0xf8)
#define MAX14830_WRITE_BIT      0x80


/* MAX14830 specific */
#define MAX14830_BRGCFG_CLKDIS_BIT  (1 << 6) /* Clock Disable */
#define MAX14830_REV_ID         (0xb0)


#define MAX14830_CLK_CFG            0x06    //0x04
#define MAX14830_PLL_CFG            0x44
#define MAX14830_TIMEOUT_CFG        200
#define MAX14830_FIFO_TRIG_LVL_CFG  0x44
#define MAX14830_LSR_IRQ_EN_CFG     0x01
#define MAX14830_MODE1_REG_CFG      0x81
#define MAX14830_TIMEOUT_OFFSET     10000

#define MAX14830_CH0 0x00 //Channel 0
#define MAX14830_CH1 0x20 //Channel 1
#define MAX14830_CH2 0x40 //Channel 2
#define MAX14830_CH3 0x60 //Channel 3

#define MAX14830_UART0  0x0E    //Channel 0
#define MAX14830_UART1  0x0D    //Channel 1
#define MAX14830_UART2  0x0B    //Channel 2
#define MAX14830_UART3  0x07   //Channel 3

#define MAX1680_SW_TMOUT 5000
#define MAX1680_FIFO_LEN 128

#define MAX14830_GPIO_PIN_0                 ((uint16_t)0x0001U)  /* Pin 0 selected    */
#define MAX14830_GPIO_PIN_1                 ((uint16_t)0x0002U)  /* Pin 1 selected    */
#define MAX14830_GPIO_PIN_2                 ((uint16_t)0x0004U)  /* Pin 2 selected    */
#define MAX14830_GPIO_PIN_3                 ((uint16_t)0x0008U)  /* Pin 3 selected    */
#define MAX14830_GPIO_PIN_4                 ((uint16_t)0x0010U)  /* Pin 4 selected    */
#define MAX14830_GPIO_PIN_5                 ((uint16_t)0x0020U)  /* Pin 5 selected    */
#define MAX14830_GPIO_PIN_6                 ((uint16_t)0x0040U)  /* Pin 6 selected    */
#define MAX14830_GPIO_PIN_7                 ((uint16_t)0x0080U)  /* Pin 7 selected    */
#define MAX14830_GPIO_PIN_8                 ((uint16_t)0x0100U)  /* Pin 8 selected    */
#define MAX14830_GPIO_PIN_9                 ((uint16_t)0x0200U)  /* Pin 9 selected    */
#define MAX14830_GPIO_PIN_10                ((uint16_t)0x0400U)  /* Pin 10 selected   */
#define MAX14830_GPIO_PIN_11                ((uint16_t)0x0800U)  /* Pin 11 selected   */
#define MAX14830_GPIO_PIN_12                ((uint16_t)0x1000U)  /* Pin 12 selected   */
#define MAX14830_GPIO_PIN_13                ((uint16_t)0x2000U)  /* Pin 13 selected   */
#define MAX14830_GPIO_PIN_14                ((uint16_t)0x4000U)  /* Pin 14 selected   */
#define MAX14830_GPIO_PIN_15                ((uint16_t)0x8000U)  /* Pin 15 selected   */
#define MAX14830_GPIO_PIN_All               ((uint16_t)0xFFFFU)  /* All pins selected */

#define IRQ_Pin MAX14830_GPIO_PIN_5
#define RST_PIN MAX14830_GPIO_PIN_4
#define CSN_Pin MAX14830_GPIO_PIN_11

#define MAX14830_WAIT_FOREVER 0xFFFFFFFFU  ///< Indefinite waiting time

/*
 * @brief GPIO pin state enumeration
 */
typedef enum
{
    MAX14830_GPIO_RESET = 0,            ///< GPIO reset
    MAX14830_GPIO_SET ,                 ///< GPIO set
    MAX14830_MAX_GPIO_STATE
}e_max14830_gpio_pin_state;

typedef struct
{
    uint8_t channel_id;
    uint8_t test_mode;
    uint8_t status;
    char data[15];
}s_test_spi_uart_conv;


/**
 * @brief spi read function pointer
 */
typedef uint8_t (*max14830_read_spi_fptr_t)(void* intf_hdl,uint8_t *buffer,uint16_t len,uint32_t timeout);

/**
 * @brief spi write function pointer
 */
typedef uint8_t (*max14830_write_spi_fptr_t)(void* intf_hdl,uint8_t *buffer,uint16_t len,uint32_t timeout);

/**
 * @brief spi read write function pointer
 */
typedef uint8_t (*max14830_read_write_spi_fptr_t)(void* intf_hdl,uint8_t *tx_buffer,uint8_t *rx_buffer,uint16_t len,uint32_t timeout);

/**
 * @brief i2c read function pointer
 */
typedef uint8_t (*max14830_read_i2c_fptr_t)(void* intf_hdl,uint16_t slave_address, uint8_t reg_addr, uint8_t *data, uint16_t len);

/**
 * @brief i2c write function pointer
 */
typedef uint8_t (*max14830_write_i2c_fptr_t)(void* intf_hdl,uint16_t slave_address, uint8_t reg_addr, uint8_t *read_data, uint16_t len);

/**
 * @brief gpio read function pointer
 */
typedef uint8_t (*max14830_read_gpio_fptr_t)(uint32_t gpio_Pin);

/**
 * @brief gpio write function pointer
 */
typedef void (*max14830_write_gpio_fptr_t)(uint32_t gpio_Pin, e_max14830_gpio_pin_state pin_state);

/**
 * @brief callback function pointer of port0
 */
typedef void (*max14830_callback_port0_fptr_t)(void);

/**
 * @brief callback function pointer of port1
 */
typedef void (*max14830_callback_port1_fptr_t)(void);

/**
 * @brief callback function pointer of port2
 */
typedef void (*max14830_callback_port2_fptr_t)(void);

/**
 * @brief callback function pointer of port3
 */
typedef void (*max14830_callback_port3_fptr_t)(void);

/**
 * @brief timer function pointer
 */
typedef uint32_t (*max14830_timer_fptr_t)(void);

/**
 * @brief semaphore take function pointer
 */
typedef int8_t (*max14830_sem_take_fptr_t)(void* sem_id,uint32_t tick_time);

/**
 * @brief semaphore give function pointer
 */
typedef int8_t (*max14830_sem_give_fptr_t)(void* sem_id);

/**
 * @brief os delay function pointer
 */
typedef int8_t (*max14830_os_delay_fptr_t)(uint32_t delay_time);

/**
 * @brief timer start function pointer
 */
typedef int8_t (*max14830_timer_start_fptr_t)(void* timer_hdle,uint32_t time);

/**
 * @brief timer stop function pointer
 */
typedef int8_t (*max14830_timer_stop_fptr_t)(void* timer_hdle);

/**
 * @brief malloc function pointer
 */
typedef void* (*max14830_malloc_fptr_t)(uint32_t size);

/**
 * @brief queue send function pointer
 */
typedef uint8_t (*max14830_queue_send_fptr_t)(void* queue_hdl,void* msg_ptr,uint32_t time);

/**
 * @brief callback function pointer
 */
typedef void (*max14830_callback_fptr_t)(void);

/**
 * @brief write function pointer
 */
typedef struct
{
    uint8_t clk;                    /*!< clock configuration                   */
    uint8_t pll;                    /*!< pll configuration                     */
    uint8_t rxto_reg;               /*!< receive timeout configuration         */
    uint8_t lsr_irq_en_reg;         /*!< lsr irq enable configuration          */
    uint8_t mode_reg;               /*!< mode1 configuration                   */
    uint8_t irq_en_reg;             /*!< irq enable configuration              */
    uint8_t fifo_trglvl_reg;        /*!< FIFO trigger level configuration      */
    uint8_t lcr_reg;                /*!< lcr configuration                     */

}s_port_reg_cfg_value;


extern max14830_sem_take_fptr_t sem_take;
extern max14830_timer_fptr_t timer;
extern max14830_os_delay_fptr_t delay_ms;
extern max14830_sem_give_fptr_t sem_give;
//extern max14830_delay_fptr_t delay_func;
extern max14830_timer_start_fptr_t timer_start;
extern max14830_timer_stop_fptr_t timer_stop;
extern max14830_malloc_fptr_t malloc_func;
extern max14830_queue_send_fptr_t queue_send;


/*
 * @brief GPIO port enumeration
 */
typedef enum
{
    MAX14830_GPIO_A,                    ///< GPIO port A
    MAX14830_GPIO_B,                    ///< GPIO port B
    MAX14830_GPIO_C,                    ///< GPIO port C
    MAX14830_GPIO_D,                    ///< GPIO port D
    MAX14830_GPIO_E,                    ///< GPIO port E
    MAX14830_GPIO_F,                    ///< GPIO port F
    MAX14830_GPIO_G,                    ///< GPIO port G
    MAX14830_GPIO_H,                    ///< GPIO port H
    MAX14830_GPIO_I,                    ///< GPIO port I
    MAX14830_GPIO_J                     ///< GPIO port J
}e_gpio_port;

/*
 * @brief MAX14830 initialization configuration structure
 */
typedef struct
{
    uint32_t  baudrate;         /*!< Baudrate       */
    uint8_t  stop_bit;          /*!< stop bit       */
    uint8_t  wrd_len;           /*!< word length    */
    uint8_t parity_bit;         /*!< parity bit     */
    uint8_t chnl_id;            /*!< channel id     */
}s_max14830_uart_init_cfg;

/*
 * @brief Interface id enumeration
 */
typedef enum
{
    MAX14830_SPI_INTF = 0,              ///< SPI interface
    MAX14830_I2C_INTF,                  ///< I2C interface
    MAX14830_MAX_INTF
}e_max14830_intf_id;

/*
 * @brief MAX14830 control block structure definition
 */
typedef struct
{
    uint16_t slave_address;                             /*!< slave address                              */
    void *io_intf_hdle;                                 /*!< interface handle                           */
    uint8_t intf_id;                                    /*!< interface id                               */
    max14830_read_spi_fptr_t spi_read;                  /*!< spi read function pointer                  */
    max14830_write_spi_fptr_t spi_write;                /*!< spi write function pointer                 */
    max14830_read_write_spi_fptr_t spi_read_write;      /*!< spi read write function pointer            */
    max14830_read_i2c_fptr_t i2c_read;                  /*!< i2c read function pointer                  */
    max14830_write_i2c_fptr_t i2c_write;                /*!< i2c write function pointer                 */
    max14830_read_gpio_fptr_t gpio_read;                /*!< gpio read function pointer                 */
    max14830_write_gpio_fptr_t gpio_write;              /*!< gpio write function pointer                */
    uint8_t *rcv0_ptr;                                  /*!< receive buffer for port0                   */
    uint8_t *rcv1_ptr;                                  /*!< receive buffer for port1                   */
    uint8_t *rcv2_ptr;                                  /*!< receive buffer for port2                   */
    uint8_t *rcv3_ptr;                                  /*!< receive buffer for port3                   */
    max14830_callback_port0_fptr_t callback0_func;      /*!< callback function pointer for port0        */
    max14830_callback_port1_fptr_t callback1_func;      /*!< callback function pointer for port1        */
    max14830_callback_port2_fptr_t callback2_func;      /*!< callback function pointer for port2        */
    max14830_callback_port3_fptr_t callback3_func;      /*!< callback function pointer for port3        */
    uint32_t irq_pin = MAX14830_GPIO_PIN_5;
    uint32_t rst_pin = MAX14830_GPIO_PIN_4;
    uint32_t cs_pin = MAX14830_GPIO_PIN_11;
    uint32_t cs_port = MAX14830_GPIO_A;

}s_max14830_hdle;

/*
 * @brief MAX14830 return status enumeration
 */
typedef enum
{
    MAX14830_SCS = -0,                  ///< MAX14830 success
    MAX14830_ERR = -1,                  ///< MAX14830 error
    MAX14830_INVLD_ARG = -2,            ///< MAX14830 invalid argument
    MAX14830_ALRDY_USD =-3,             ///< MAX14830 already used
    MAX14830_COM_ERR = -4,              ///< MAX14830 communication error
    MAX14830_NULL_PTR = -5,             ///< MAX14830 NULL pointer error
    MAX14830_ERR_MAX = -6
}e_max14830_ret_sts;

//void max14830_intr_hdlr();

/**
 * @brief Initialize the MAX14830 and configure the required parameter
 * @param[in] max14830_hdl : structure handle of MAX14830
 * @retval e_max14830_ret_sts - returns the success or error code
 */
uint8_t max14830_init(s_max14830_hdle *max14830_hdl);

/**
 * @brief This function set the baudrate
 * @param[in] max14830_hdl : structure handle of MAX14830
 * @param[in] port : Indicated the UART port
 * @param[in] baud_rate : Baudrate to be set
 * @retval e_max14830_ret_sts - returns the success or error code
 */
uint16_t max14830_set_baudrate(s_max14830_hdle *max14830_hdl,uint8_t port, uint32_t baud_rate);

//void max14830_uart_puts(uint8_t port,char *ptr, uint16_t len);
void MAX14830_port_irq();

/**
 * @brief This function receive the data from the channel 0 with interrupt mode
 * @param[in] max14830_hdl : structure handle of MAX14830
 * @retval e_max14830_ret_sts - returns the success or error code
 */
void max14830_rx_ch0_it();

/**
 * @brief This function receive the data from the channel 1 with interrupt mode
 * @param[in] max14830_hdl : structure handle of MAX14830
 * @retval e_max14830_ret_sts - returns the success or error code
 */
void max14830_rx_ch1_it();

/**
 * @brief This function receive the data from the channel 2 with interrupt mode
 * @param[in] max14830_hdl : structure handle of MAX14830
 * @retval e_max14830_ret_sts - returns the success or error code
 */
void max14830_rx_ch2_it();

/**
 * @brief This function receive the data from the channel 3 with interrupt mode
 * @param[in] max14830_hdl : structure handle of MAX14830
 * @retval e_max14830_ret_sts - returns the success or error code
 */
void max14830_rx_ch3_it();

/**
 * @brief This function initialize the UART configurations
 * @param[in] max14830_hdl : structure handle of MAX14830
 * @param[in] init_data : structure handle for init configuration
 * @retval e_max14830_ret_sts - returns the success or error code
 */
e_max14830_ret_sts max14830_uart_init(s_max14830_hdle *max14830_hdl,s_max14830_uart_init_cfg *init_data);

/**
 * @brief This function transmit the data
 * @param[in] hdle : structure handle of MAX14830
 * @param[in] port - channel id
 * @param[in] tx_buff - pointer to a buffer
 * @param[in] tx_len : length of the data
 * @retval e_max14830_ret_sts - returns the success or error code
 */
void max14830_uart_tx(s_max14830_hdle *hdle,uint8_t port, uint8_t *tx_buff, uint16_t tx_len);

/**
 * @brief This function recieve the data in interrupt mode
 * @param[in] hdle : structure handle of MAX14830
 * @param[in] port - channel id
 * @param[in] len : length of the data
 * @param[in] callback_func - callback function
 * @retval e_max14830_ret_sts - returns the success or error code
 */
e_max14830_ret_sts max14830_uart_rx_intr(s_max14830_hdle *hdle,uint8_t port,uint16_t len,max14830_callback_fptr_t callback_func);

/**
 * @brief This function set the required number of stop bit
 * @param[in] max14830_hdl : structure handle of MAX14830
 * @param[in] port - channel id
 * @param[in] reg_id : register address
 * @param[in] val - value to be set
 * @retval e_max14830_ret_sts - returns the success or error code
 */
e_max14830_ret_sts max14830_set_stopbit(s_max14830_hdle *max14830_hdl,uint8_t port,uint8_t reg_id,uint8_t val);

/**
 * @brief This function set the word length
 * @param[in] max14830_hdl : structure handle of MAX14830
 * @param[in] port - channel id
 * @param[in] reg_id : register address
 * @param[in] val - value to be set
 * @retval e_max14830_ret_sts - returns the success or error code
 */
e_max14830_ret_sts max14830_set_wrdlen(s_max14830_hdle *max14830_hdl,uint8_t port,uint8_t reg_id,uint8_t val);

/**
 * @brief This function set the required number of stop bit
 * @param[in] max14830_hdl : structure handle of MAX14830
 * @param[in] port - channel id
 * @param[in] reg_id : register address
 * @param[in] len : length of the data
 * @param[out] buff - pointer to a buffer
 * @retval e_max14830_ret_sts - returns the success or error code
 */
e_max14830_ret_sts max14830_read(s_max14830_hdle *max14830_hdl,uint8_t port, uint8_t reg_addr,uint16_t len,uint8_t *buff);

/*
 * @brief This function use to self test the SPI to UART convertor
 * @param[in] max14830_hdl : Instance handle
 */
e_max14830_ret_sts max14830_self_test(s_max14830_hdle *inst_hdl);

void spi_uart_init_func(uint8_t ahw_id);

#endif /* SPI_UART_MAX14830_H_ */
#endif
