#ifndef EPS_INC_EPS_CNTRL_INIT_H_
#define EPS_INC_EPS_CNTRL_INIT_H_

#include "stdio.h"
#include <string.h>
#include "stdint.h"
#include "stdlib.h"
#include "exo_osal.h"
#include "exo_common.h"
#include "eps.h"
#include "eps_ctrlr.h"
#include "exo_io_al_sos_timer.h"


#include "nvm.h"


#define EPS_NVM_GET_ALERT_CNT

#define EPS_PWR_TMR        	  10      //msec

#define EPS_BTRY_OFF_VAL  	 9.0      //volt
#define EPS_BTRY_CRTCAL_VAL  10.5
#define EPS_BTRY_SAFE_VAL    10.8
#define EPS_BTRY_NORMAL_VAL  11.5
#define EPS_BTRY_FULL_VAL    12.6
#define EPS_CHNL_OFF(x,y)  (x = x&~(1<<y))
#define EPS_SET_ON(x,y)  (x = x|(1<<y))
#define EPS_GET_CHNL(x,y) (x&1<<y)>0?1:0

extern os_itc_msg_handle_t 		eps_itc_msg;

/**
 * @brief EPS device current timer structure
 */
typedef struct eps_dev_crnt_tmr_t
{
	uint8_t 	state;					/*!< state			*/
	uint8_t 	enable;					/*!< enable			*/
	uint32_t 	cntr;					/*!< counter		*/
}eps_dev_crnt_tmr_s;

/**
 * @brief EPS health information structure
 */
typedef struct eps_hlth_infor_t
{
	uint16_t  		dev_hw_sts;				/*!< device hw status				*/
	uint32_t 		alrt_value;				/*!< alert value					*/
	uint32_t 	 	com_fail_cnt;			/*!< communication fail count		*/
	uint32_t 	 	crc_fail_cnt;			/*!< communication fail count		*/
	eps_get_btry_brd_tmr_s btry_params;		/*!< battery parameter				*/
	eps_get_conv_brd_tmr_s conv_params;		/*!< convertor parameter			*/
}eps_hlth_info_s;
/*
typedef struct _eps_beakcon_info_s
{
	uint8_t totl_btry_volt;
	uint8_t totl_panel_pwr;
	uint16_t chnl_sts;
	uint8_t overcrnt_err_flg_byte1;
	uint16_t overcrnt_err_flg_byte2;

}eps_beakcon_info_s;
*/
/**
 * @brief EPS power timer convertor inline function
 *
 * @param _tmr - eps timer variable
 *
 * @return time
 */
static inline uint32_t eps_pwr_tmr_conv(eps_time_s _tmr)
{
	return((((_tmr.min*60)+_tmr.sec)*100) + _tmr.msec/10);
}


#ifndef EPS_NVM_EN
#if 1
/**
 * @brief Inline function for battery mode default values
 *
 * @param _eps_btry_thrshld - structure that holds the eps battery threashold parameter
 *
 * No return
 */

static inline void btry_mode_defaults(eps_btry_thrshld_s *_eps_btry_thrshld)
{
 	_eps_btry_thrshld->volt[HW_BTRY_CRTCAL]	= (float)EPS_BTRY_CRTCAL_VAL;
	_eps_btry_thrshld->volt[HW_BTRY_SAFE]  = (float)EPS_BTRY_SAFE_VAL;
	_eps_btry_thrshld->volt[HW_BTRY_NORMAL]  = (float)EPS_BTRY_NORMAL_VAL;
	//_eps_btry_thrshld->volt[EPS_MODE_FULL]  = (float)EPS_BTRY_FULL_VAL;
}
#endif

static inline void eps_chnl_eligible_to_restart(uint16_t *eps_chnl_num)
{
	*eps_chnl_num=									\
			(  0  <<  HW_PL_TRANSCELESTIAL)|		\
			(  1  <<  HW_S_BAND)|					\
			(  0  <<  HW_X_BAND)|					\
			(  0  <<  HW_PL_STS300)|				\
			(  1  <<  HW_ADCS)|						\
			(  0  <<  HW_PROP_UNIT_THRUSTER)|		\
			(  1  <<  HW_UHF)|						\
			(  0  <<  HW_PL_SCANWAY)|				\
			(  0  <<  HW_PL_NETRA)|					\
			(  0  <<  HW_EDGE_BRD)|					\
			(  0  <<  HW_OBC_PS_GPS_STD_PL_BRD)|	\
			(  0  <<  HW_HRM);
}

/**
 * @brief Inline function for default values of individual channel state with respective mode
 *
 * @param _eps_btry_ch_map - structure holds the _eps_btry_ch_map
 */
static inline void eps_ctrlr_set_ch_valid_defaults(eps_btry_ch_map_s *_eps_btry_ch_map)
{
#ifdef JANUS1
	//1 - channel enable   , 0 - channel disable
	_eps_btry_ch_map->valid_on[HW_BTRY_CRTCAL]=		\
			(  0  <<  HW_PL_TRANSCELESTIAL)|		\
			(  0  <<  HW_X_BAND)|					\
			(  0  <<  HW_S_BAND)|					\
			(  0  <<  HW_ADCS0)|					\
			(  0  <<  HW_ADCS)|						\
			(  0  <<  HW_PROP_UNIT_THRUSTER)|		\
			(  0  <<  HW_PL_ZES)|					\
			(  0  <<  HW_PL_SAYARLABS)|				\
			(  0  <<  HW_PL_NETRA)|					\
			(  0  <<  HW_EDGE_BRD)|					\
			(  1  <<  HW_OBC_PS_GPS_STD_PL_BRD)|	\
			(  0  <<  HW_PL_SERVER)|				\
			(  0  <<  HW_GPS)|						\
			(  1  <<  HW_HRM);

	_eps_btry_ch_map->valid_on[HW_BTRY_SAFE] =		\
			(  0  <<  HW_PL_TRANSCELESTIAL)|		\
			(  0  <<  HW_X_BAND)|					\
			(  1  <<  HW_S_BAND)|					\
			(  1  <<  HW_ADCS0)|					\
			(  1  <<  HW_ADCS)|						\
			(  0  <<  HW_PROP_UNIT_THRUSTER)|		\
			(  0  <<  HW_PL_ZES)|					\
			(  0  <<  HW_PL_SAYARLABS)|				\
			(  0  <<  HW_PL_NETRA)|					\
			(  0  <<  HW_EDGE_BRD)|					\
			(  1  <<  HW_OBC_PS_GPS_STD_PL_BRD)|	\
			(  0  <<  HW_PL_SERVER)|				\
			(  0  <<  HW_GPS)|						\
			(  1  <<  HW_HRM);

	_eps_btry_ch_map->valid_on[HW_BTRY_NORMAL]=		\
			(  1  <<  HW_PL_TRANSCELESTIAL)|		\
			(  1  <<  HW_X_BAND)|					\
			(  1  <<  HW_S_BAND)|					\
			(  1  <<  HW_ADCS0)|					\
			(  1  <<  HW_ADCS)|						\
			(  1  <<  HW_PROP_UNIT_THRUSTER)|		\
			(  1  <<  HW_PL_ZES)|					\
			(  1  <<  HW_PL_SAYARLABS)|				\
			(  1  <<  HW_PL_NETRA)|					\
			(  1  <<  HW_EDGE_BRD)|					\
			(  1  <<  HW_OBC_PS_GPS_STD_PL_BRD)|	\
			(  1  <<  HW_PL_SERVER)|				\
			(  1  <<  HW_GPS)|						\
			(  1  <<  HW_HRM);

	_eps_btry_ch_map->auto_on[HW_BTRY_CRTCAL] =		\
			(  0  <<  HW_PL_TRANSCELESTIAL)|		\
			(  0  <<  HW_X_BAND)|					\
			(  0  <<  HW_S_BAND)|					\
			(  0  <<  HW_ADCS0)|					\
			(  0  <<  HW_ADCS)|						\
			(  0  <<  HW_PROP_UNIT_THRUSTER)|		\
			(  0  <<  HW_PL_ZES)|					\
			(  0  <<  HW_PL_SAYARLABS)|				\
			(  0  <<  HW_PL_NETRA)|					\
			(  0  <<  HW_EDGE_BRD)|					\
			(  1  <<  HW_OBC_PS_GPS_STD_PL_BRD)|	\
			(  0  <<  HW_PL_SERVER)|				\
			(  0  <<  HW_GPS)|						\
			(  0  <<  HW_HRM);

	_eps_btry_ch_map->auto_on[HW_BTRY_SAFE] =		\
			(  0  <<  HW_PL_TRANSCELESTIAL)|		\
			(  0  <<  HW_X_BAND)|					\
			(  1  <<  HW_S_BAND)|					\
			(  0  <<  HW_ADCS0)|					\
			(  1  <<  HW_ADCS)|						\
			(  0  <<  HW_PROP_UNIT_THRUSTER)|		\
			(  0  <<  HW_PL_ZES)|					\
			(  0  <<  HW_PL_SAYARLABS)|				\
			(  0  <<  HW_PL_NETRA)|					\
			(  0  <<  HW_EDGE_BRD)|					\
			(  1  <<  HW_OBC_PS_GPS_STD_PL_BRD)|	\
			(  0  <<  HW_PL_SERVER)|				\
			(  0  <<  HW_GPS)|						\
			(  0  <<  HW_HRM);

	_eps_btry_ch_map->auto_on[HW_BTRY_NORMAL] =
			(  0  <<  HW_PL_TRANSCELESTIAL)|		\
			(  0  <<  HW_X_BAND)|					\
			(  1  <<  HW_S_BAND)|					\
			(  0  <<  HW_ADCS0)|					\
			(  1  <<  HW_ADCS)|						\
			(  0  <<  HW_PROP_UNIT_THRUSTER)|		\
			(  0  <<  HW_PL_ZES)|					\
			(  0  <<  HW_PL_SAYARLABS)|				\
			(  0  <<  HW_PL_NETRA)|					\
			(  0  <<  HW_EDGE_BRD)|					\
			(  1  <<  HW_OBC_PS_GPS_STD_PL_BRD)|	\
			(  0  <<  HW_PL_SERVER)|				\
			(  0  <<  HW_GPS)|						\
			(  0  <<  HW_HRM);

#else
	//1 - channel enable   , 0 - channel disable
#ifndef DRISHTI_EN
	_eps_btry_ch_map->valid_on[HW_BTRY_CRTCAL]=		\
			(  0  <<  HW_PL_TRANSCELESTIAL)|		\
			(  0  <<  HW_S_BAND)|					\
			(  0  <<  HW_X_BAND)|					\
			(  0  <<  HW_PL_STS300)|				\
			(  0  <<  HW_ADCS)|						\
			(  0  <<  HW_PROP_UNIT_THRUSTER)|		\
			(  0  <<  HW_UHF)|						\
			(  0  <<  HW_PL_SCANWAY)|				\
			(  0  <<  HW_PL_NETRA)|					\
			(  0  <<  HW_EDGE_BRD)|					\
			(  1  <<  HW_OBC_PS_GPS_STD_PL_BRD)|	\
			(  0  <<  HW_PL_SERVER)|				\
			(  0  <<  HW_GPS)|						\
			(  1  <<  HW_HRM);

	_eps_btry_ch_map->valid_on[HW_BTRY_SAFE] =		\
			(  0  <<  HW_PL_TRANSCELESTIAL)|		\
			(  1  <<  HW_S_BAND)|					\
			(  0  <<  HW_X_BAND)|					\
			(  0  <<  HW_PL_STS300)|				\
			(  1  <<  HW_ADCS)|						\
			(  0  <<  HW_PROP_UNIT_THRUSTER)|		\
			(  1  <<  HW_UHF)|						\
			(  0  <<  HW_PL_SCANWAY)|				\
			(  0  <<  HW_PL_NETRA)|					\
			(  0  <<  HW_EDGE_BRD)|					\
			(  1  <<  HW_OBC_PS_GPS_STD_PL_BRD)|	\
			(  0  <<  HW_PL_SERVER)|				\
			(  0  <<  HW_GPS)|						\
			(  1  <<  HW_HRM);

	_eps_btry_ch_map->valid_on[HW_BTRY_NORMAL]=		\
			(  1  <<  HW_PL_TRANSCELESTIAL)|		\
			(  1  <<  HW_S_BAND)|					\
			(  1  <<  HW_X_BAND)|					\
			(  1  <<  HW_PL_STS300)|				\
			(  1  <<  HW_ADCS)|						\
			(  1  <<  HW_PROP_UNIT_THRUSTER)|		\
			(  1  <<  HW_UHF)|						\
			(  1  <<  HW_PL_SCANWAY)|				\
			(  1  <<  HW_PL_NETRA)|					\
			(  1  <<  HW_EDGE_BRD)|					\
			(  1  <<  HW_OBC_PS_GPS_STD_PL_BRD)|	\
			(  1  <<  HW_PL_SERVER)|				\
			(  1  <<  HW_GPS)|						\
			(  1  <<  HW_HRM);


	_eps_btry_ch_map->auto_on[HW_BTRY_CRTCAL] =		\
			(  0  <<  HW_PL_TRANSCELESTIAL)|		\
			(  0  <<  HW_S_BAND)|					\
			(  0  <<  HW_X_BAND)|					\
			(  0  <<  HW_PL_STS300)|				\
			(  0  <<  HW_ADCS)|						\
			(  0  <<  HW_PROP_UNIT_THRUSTER)|		\
			(  0  <<  HW_UHF)|						\
			(  0  <<  HW_PL_SCANWAY)|				\
			(  0  <<  HW_PL_NETRA)|					\
			(  0  <<  HW_EDGE_BRD)|					\
			(  0  <<  HW_OBC_PS_GPS_STD_PL_BRD)|	\
			(  0  <<  HW_PL_SERVER)|				\
			(  0  <<  HW_GPS)|						\
			(  0  <<  HW_HRM);

	_eps_btry_ch_map->auto_on[HW_BTRY_SAFE] =		\
			(  0  <<  HW_PL_TRANSCELESTIAL)|		\
			(  1  <<  HW_S_BAND)|					\
			(  0  <<  HW_X_BAND)|					\
			(  0  <<  HW_PL_STS300)|				\
			(  1  <<  HW_ADCS)|						\
			(  0  <<  HW_PROP_UNIT_THRUSTER)|		\
			(  1  <<  HW_UHF)|						\
			(  0  <<  HW_PL_SCANWAY)|				\
			(  0  <<  HW_PL_NETRA)|					\
			(  0  <<  HW_EDGE_BRD)|					\
			(  0  <<  HW_OBC_PS_GPS_STD_PL_BRD)|	\
			(  0  <<  HW_PL_SERVER)|				\
			(  0  <<  HW_GPS)|						\
			(  0  <<  HW_HRM);

	_eps_btry_ch_map->auto_on[HW_BTRY_NORMAL] =		\
			(  0  <<  HW_PL_TRANSCELESTIAL)|		\
			(  1  <<  HW_S_BAND)|					\
			(  0  <<  HW_X_BAND)|					\
			(  0  <<  HW_PL_STS300)|				\
			(  1  <<  HW_ADCS)|						\
			(  0  <<  HW_PROP_UNIT_THRUSTER)|		\
			(  1  <<  HW_UHF)|						\
			(  0  <<  HW_PL_SCANWAY)|				\
			(  0  <<  HW_PL_NETRA)|					\
			(  0  <<  HW_EDGE_BRD)|					\
			(  0  <<  HW_OBC_PS_GPS_STD_PL_BRD)|	\
			(  0  <<  HW_PL_SERVER)|				\
			(  0  <<  HW_GPS)|						\
			(  0  <<  HW_HRM);
#else

#define COREBOARD_A        HW_PL_TRANSCELESTIAL
#define COREBOARD_B         HW_S_BAND
#define AVIONICS            HW_X_BAND
#define GEN2_ADCS                HW_PL_STS300
#define GEN2_THRUSTER           HW_ADCS
#define GEN2_UHF                 HW_PROP_UNIT_THRUSTER
#define GEN2_S_BAND              HW_UHF
#define GEN2_X_BAND_2            HW_PL_SCANWAY
#define GEN2_X_BAND_1            HW_PL_NETRA
#define MSI_PAYLOAD         HW_EDGE_BRD
#define SAR_PAYLOAD         HW_OBC_PS_GPS_STD_PL_BRD

 _eps_btry_ch_map->valid_on[HW_BTRY_CRTCAL]=             \
                        (  1  <<  COREBOARD_A)|                \
                        (  0  <<    COREBOARD_B)|                                   \
                        (  0  <<  AVIONICS)|                                \
                        (  0  <<  GEN2_ADCS)|                                 \
                        (  0  <<  GEN2_THRUSTER)|                                             \
                        (  0  <<  GEN2_UHF)|               \
                        (  0  <<  GEN2_S_BAND)|                                              \
                        (  0  <<  GEN2_X_BAND_2)|                               \
                        (  0  <<  GEN2_X_BAND_1)|                                 \
                        (  0  <<  MSI_PAYLOAD)|                             \
                        (  0  <<  SAR_PAYLOAD);                                   


        _eps_btry_ch_map->valid_on[HW_BTRY_SAFE] =              \
                        (  1  <<  COREBOARD_A)|                \
                        (  0  <<  COREBOARD_B)|                                   \
                        (  1  <<  AVIONICS)|                                \
                        (  1  <<  GEN2_ADCS)|                                 \
                        (  0  <<  GEN2_THRUSTER)|                                             \
                        (  1  <<  GEN2_UHF)|               \
                        (  1  <<  GEN2_S_BAND)|                                              \
                        (  0  <<  GEN2_X_BAND_2)|                               \
                        (  0  <<  GEN2_X_BAND_1)|                                 \
                        (  0  <<  MSI_PAYLOAD)|         \
                        (  0  <<  SAR_PAYLOAD);                                   

_eps_btry_ch_map->valid_on[HW_BTRY_NORMAL]=             \
                                                (  1  <<  COREBOARD_A)|                \
                        (  1  <<  COREBOARD_B)|                                   \
                        (  1  <<  AVIONICS)|                                \
                        (  1  <<  GEN2_ADCS)|                                 \
                        (  1  <<  GEN2_THRUSTER)|                                             \
                        (  1  <<  GEN2_UHF)|               \
                        (  1  <<  GEN2_S_BAND)|                                              \
                        (  1  <<  GEN2_X_BAND_2)|                               \
                        (  1  <<  GEN2_X_BAND_1)|                                 \
                        (  1  <<  MSI_PAYLOAD)|             \
                        (  1  <<  SAR_PAYLOAD);                                   

                _eps_btry_ch_map->auto_on[HW_BTRY_CRTCAL] =             \
                                                (  0  <<  COREBOARD_A)|                \
                        (  0  <<  COREBOARD_B)|                                   \
                        (  0  <<  AVIONICS)|                                \
                        (  0  <<  GEN2_ADCS)|                                 \
                        (  0  <<  GEN2_THRUSTER)|                                             \
                        (  0  <<  GEN2_UHF)|               \
                        (  0  <<  GEN2_S_BAND)|                                              \
                        (  0  <<  GEN2_X_BAND_2)|                               \
                        (  0  <<  GEN2_X_BAND_1)|                                 \
                        (  0  <<  MSI_PAYLOAD)|                     \
                        (  0  <<  SAR_PAYLOAD);                                   

                _eps_btry_ch_map->auto_on[HW_BTRY_SAFE] =               \
                                                (  0  <<  COREBOARD_A)|                \
                        (  0  <<  COREBOARD_B)|                                   \
                        (  1  <<  AVIONICS)|                                \
                        (  1  <<  GEN2_ADCS)|                                 \
                        (  0  <<  GEN2_THRUSTER)|                                             \
                        (  1  <<  GEN2_UHF)|               \
                        (  1  <<  GEN2_S_BAND)|                                              \
                        (  0  <<  GEN2_X_BAND_2)|                               \
                        (  0  <<  GEN2_X_BAND_1)|                                 \
                        (  0  <<  MSI_PAYLOAD)|                 \
                        (  0  <<  SAR_PAYLOAD);                                   

                 _eps_btry_ch_map->auto_on[HW_BTRY_NORMAL] =             \
                                                (  0  <<  COREBOARD_A)|                \
                        (  0  <<  COREBOARD_B)|                                   \
                        (  1  <<  AVIONICS)|                                \
                        (  1  <<  GEN2_ADCS)|                                 \
                        (  0  <<  GEN2_THRUSTER)|                                             \
                        (  1  <<  GEN2_UHF)|               \
                        (  1  <<  GEN2_S_BAND)|                                              \
                        (  0  <<  GEN2_X_BAND_2)|                               \
                        (  0  <<  GEN2_X_BAND_1)|                                 \
                        (  0  <<  MSI_PAYLOAD)|     \
                        (  0  <<  SAR_PAYLOAD);                                   

#endif
#endif
}


#if 0
/**
 * @brief 
 *
 * @param _btry_tmr
 */
static inline void eps_btry_tmr_defaults(eps_dev_tmr_t *_btry_tmr)
{
	_btry_tmr->on_tmr.max_st_cnt= 1;

	_btry_tmr->on_tmr.st_val[0].min  = 5;
	_btry_tmr->on_tmr.st_val[0].sec  = 0;
	_btry_tmr->on_tmr.st_val[0].msec = 0;

	_btry_tmr->off_tmr.max_st_cnt= 1;

	_btry_tmr->off_tmr.st_val[0].min  = 1;
	_btry_tmr->off_tmr.st_val[0].sec  = 0;
	_btry_tmr->off_tmr.st_val[0].msec = 0;
}


/**
 * @brief 
 *
 * @param _btry_tmr
 */
static inline void eps_btry_mode_ch_valid(eps_dev_tmr_t *_btry_tmr)
{
	_btry_tmr->on_tmr.max_st_cnt= 1;

	_btry_tmr->on_tmr.st_val[0].min  = 5;
	_btry_tmr->on_tmr.st_val[0].sec  = 0;
	_btry_tmr->on_tmr.st_val[0].msec = 0;

	_btry_tmr->off_tmr.max_st_cnt= 1;

	_btry_tmr->off_tmr.st_val[0].min  = 5;
	_btry_tmr->off_tmr.st_val[0].sec  = 0;
	_btry_tmr->off_tmr.st_val[0].msec = 0;
}
#endif
/**
 * @brief Inline function for ON and OFF timer of transclestial payload
 *
 * @param _pl_trans_tmr - structure holds on and off timer parameter
 */
static inline void eps_pl_trans_tmr_defaults(eps_dev_tmr_t *_pl_trans_tmr)
{
	_pl_trans_tmr->on_tmr.max_st_cnt= 2;

	_pl_trans_tmr->on_tmr.st_val[0].min  = 0;
	_pl_trans_tmr->on_tmr.st_val[0].sec  = 33;
	_pl_trans_tmr->on_tmr.st_val[0].msec = 0;
	_pl_trans_tmr->on_tmr.st_val[1].min  = 0;
	_pl_trans_tmr->on_tmr.st_val[1].sec  = 2;
	_pl_trans_tmr->on_tmr.st_val[1].msec = 10;

	_pl_trans_tmr->off_tmr.max_st_cnt= 2;

	_pl_trans_tmr->off_tmr.st_val[0].min  = 0;
	_pl_trans_tmr->off_tmr.st_val[0].sec  = 3;
	_pl_trans_tmr->off_tmr.st_val[0].msec = 0;
}


/**
 * @brief Inline function for ON and OFF timer of netra payload
 *
 * @param _pl_netra_tmr - structure holds on and off timer parameter
 */
static inline void eps_pl_netra_tmr_defaults(eps_dev_tmr_t *_pl_netra_tmr)
{
	_pl_netra_tmr->on_tmr.max_st_cnt= 2;

	_pl_netra_tmr->on_tmr.st_val[0].min  = 0;
	_pl_netra_tmr->on_tmr.st_val[0].sec  = 13;
	_pl_netra_tmr->on_tmr.st_val[0].msec = 0;
	_pl_netra_tmr->on_tmr.st_val[1].min  = 0;
	_pl_netra_tmr->on_tmr.st_val[1].sec  = 0;
	_pl_netra_tmr->on_tmr.st_val[1].msec = 10;

	_pl_netra_tmr->off_tmr.max_st_cnt= 2;

	_pl_netra_tmr->off_tmr.st_val[0].min  = 0;
	_pl_netra_tmr->off_tmr.st_val[0].sec  = 3;
	_pl_netra_tmr->off_tmr.st_val[0].msec = 0;
}

#ifdef JANUS1
/**
 * @brief Inline function for ON and OFF timer of sayarlabs payload
 *
 * @param _pl_syrlbs_tmr - structure holds on and off timer parameter
 */
static inline void eps_pl_syrlbs_tmr_defaults(eps_dev_tmr_t *_pl_syrlbs_tmr)
{
	_pl_syrlbs_tmr->on_tmr.max_st_cnt= 2;

	_pl_syrlbs_tmr->on_tmr.st_val[0].min  = 0;
	_pl_syrlbs_tmr->on_tmr.st_val[0].sec  = 0;
	_pl_syrlbs_tmr->on_tmr.st_val[0].msec = 50;
	_pl_syrlbs_tmr->on_tmr.st_val[1].min  = 0;
	_pl_syrlbs_tmr->on_tmr.st_val[1].sec  = 0;
	_pl_syrlbs_tmr->on_tmr.st_val[1].msec = 10;

	_pl_syrlbs_tmr->off_tmr.max_st_cnt= 2;

	_pl_syrlbs_tmr->off_tmr.st_val[0].min  = 0;
	_pl_syrlbs_tmr->off_tmr.st_val[0].sec  = 1;
	_pl_syrlbs_tmr->off_tmr.st_val[0].msec = 0;

}



/**
 * @brief Inline function for ON and OFF timer of zes payload
 *
 * @param _pl_zes_tmr - structure holds on and off timer parameter
 */
static inline void eps_pl_zes_tmr_defaults(eps_dev_tmr_t *_pl_zes_tmr)
{
	_pl_zes_tmr->on_tmr.max_st_cnt= 2;

	_pl_zes_tmr->on_tmr.st_val[0].min  = 0;
	_pl_zes_tmr->on_tmr.st_val[0].sec  = 0;
	_pl_zes_tmr->on_tmr.st_val[0].msec = 50;
	_pl_zes_tmr->on_tmr.st_val[1].min  = 0;
	_pl_zes_tmr->on_tmr.st_val[1].sec  = 0;
	_pl_zes_tmr->on_tmr.st_val[1].msec = 10;

	_pl_zes_tmr->off_tmr.max_st_cnt= 2;

	_pl_zes_tmr->off_tmr.st_val[0].min  = 0;
	_pl_zes_tmr->off_tmr.st_val[0].sec  = 1;
	_pl_zes_tmr->off_tmr.st_val[0].msec = 0;
}
#else
/**
 * @brief Inline function for ON and OFF timer of sts300 payload
 *
 * @param _pl_sts300_tmr - structure holds on and off timer parameter
 */
static inline void eps_pl_sts300_tmr_defaults(eps_dev_tmr_t *_pl_sts300_tmr)
{
	_pl_sts300_tmr->on_tmr.max_st_cnt= 2;

	_pl_sts300_tmr->on_tmr.st_val[0].min  = 0;
	_pl_sts300_tmr->on_tmr.st_val[0].sec  = 0;
	_pl_sts300_tmr->on_tmr.st_val[0].msec = 50;
	_pl_sts300_tmr->on_tmr.st_val[1].min  = 0;
	_pl_sts300_tmr->on_tmr.st_val[1].sec  = 0;
	_pl_sts300_tmr->on_tmr.st_val[1].msec = 10;

	_pl_sts300_tmr->off_tmr.max_st_cnt= 2;

	_pl_sts300_tmr->off_tmr.st_val[0].min  = 0;
	_pl_sts300_tmr->off_tmr.st_val[0].sec  = 1;
	_pl_sts300_tmr->off_tmr.st_val[0].msec = 0;
}

/**
 * @brief Inline function for ON and OFF timer of uhf payload
 *
 * @param _pl_syrlbs_tmr - structure holds on and off timer parameter
 */
static inline void eps_pl_uhf_tmr_defaults(eps_dev_tmr_t *_pl_uhf_tmr)
{
	_pl_uhf_tmr->on_tmr.max_st_cnt= 2;

	_pl_uhf_tmr->on_tmr.st_val[0].min  = 0;
	_pl_uhf_tmr->on_tmr.st_val[0].sec  = 3;
	_pl_uhf_tmr->on_tmr.st_val[0].msec = 0;
	_pl_uhf_tmr->on_tmr.st_val[1].min  = 0;
	_pl_uhf_tmr->on_tmr.st_val[1].sec  = 0;
	_pl_uhf_tmr->on_tmr.st_val[1].msec = 10;

	_pl_uhf_tmr->off_tmr.max_st_cnt= 2;

	_pl_uhf_tmr->off_tmr.st_val[0].min  = 0;
	_pl_uhf_tmr->off_tmr.st_val[0].sec  = 3;
	_pl_uhf_tmr->off_tmr.st_val[0].msec = 0;
}

/**
 * @brief Inline function for ON and OFF timer of scanway payload
 *
 * @param _pl_scanway_tmr - structure holds on and off timer parameter
 */
static inline void eps_pl_scanway_tmr_defaults(eps_dev_tmr_t *_pl_scanway_tmr)
{
	_pl_scanway_tmr->on_tmr.max_st_cnt= 2;

	_pl_scanway_tmr->on_tmr.st_val[0].min  = 0;
	_pl_scanway_tmr->on_tmr.st_val[0].sec  = 0;
	_pl_scanway_tmr->on_tmr.st_val[0].msec = 50;
	_pl_scanway_tmr->on_tmr.st_val[1].min  = 0;
	_pl_scanway_tmr->on_tmr.st_val[1].sec  = 0;
	_pl_scanway_tmr->on_tmr.st_val[1].msec = 10;

	_pl_scanway_tmr->off_tmr.max_st_cnt= 2;

	_pl_scanway_tmr->off_tmr.st_val[0].min  = 0;
	_pl_scanway_tmr->off_tmr.st_val[0].sec  = 1;
	_pl_scanway_tmr->off_tmr.st_val[0].msec = 0;
}

#endif


/**
 * @brief Inline function for ON and OFF timer of thruster payload
 *
 * @param _thrstr_tmr - structure holds on and off timer parameter
 */
static inline void eps_thrstr_tmr_defaults(eps_dev_tmr_t *_thrstr_tmr)
{
	_thrstr_tmr->on_tmr.max_st_cnt= 2;

	_thrstr_tmr->on_tmr.st_val[0].min  = 0;
	_thrstr_tmr->on_tmr.st_val[0].sec  = 0;
	_thrstr_tmr->on_tmr.st_val[0].msec = 50;
	_thrstr_tmr->on_tmr.st_val[1].min  = 0;
	_thrstr_tmr->on_tmr.st_val[1].sec  = 0;
	_thrstr_tmr->on_tmr.st_val[1].msec = 10;

	_thrstr_tmr->off_tmr.max_st_cnt= 2;

	_thrstr_tmr->off_tmr.st_val[0].min  = 0;
	_thrstr_tmr->off_tmr.st_val[0].sec  = 1;
	_thrstr_tmr->off_tmr.st_val[0].msec = 0;

}


/**
 * @brief Inline function for ON and OFF timer of OBC payload
 *
 * @param _obc_tmr - structure holds on and off timer parameter
 */
static inline void eps_obc_tmr_defaults(eps_dev_tmr_t *_obc_tmr)
{
	_obc_tmr->on_tmr.max_st_cnt= 2;

	_obc_tmr->on_tmr.st_val[0].min  = 0;
	_obc_tmr->on_tmr.st_val[0].sec  = 0;
	_obc_tmr->on_tmr.st_val[0].msec = 50;
	_obc_tmr->on_tmr.st_val[1].min  = 0;
	_obc_tmr->on_tmr.st_val[1].sec  = 0;
	_obc_tmr->on_tmr.st_val[1].msec = 10;

	_obc_tmr->off_tmr.max_st_cnt= 2;

	_obc_tmr->off_tmr.st_val[0].min  = 5;
	_obc_tmr->off_tmr.st_val[0].sec  = 0;
	_obc_tmr->off_tmr.st_val[0].msec = 0;
	_obc_tmr->off_tmr.st_val[1].min  = 0;
	_obc_tmr->off_tmr.st_val[1].sec  = 0;
	_obc_tmr->off_tmr.st_val[1].msec = 10;

}

/**
 * @brief Inline function for ON and OFF timer of xband
 *
 * @param _xband_tmr - structure holds on and off timer parameter
 */
static inline void eps_xband_tmr_defaults(eps_dev_tmr_t *_xband_tmr)
{
	_xband_tmr->on_tmr.max_st_cnt= 2;

	_xband_tmr->on_tmr.st_val[0].min  = 0;
	_xband_tmr->on_tmr.st_val[0].sec  = 0;
	_xband_tmr->on_tmr.st_val[0].msec = 50;
	_xband_tmr->on_tmr.st_val[1].min  = 0;
	_xband_tmr->on_tmr.st_val[1].sec  = 0;
	_xband_tmr->on_tmr.st_val[1].msec = 10;

	_xband_tmr->off_tmr.max_st_cnt= 2;

	_xband_tmr->off_tmr.st_val[0].min  = 0;
	_xband_tmr->off_tmr.st_val[0].sec  = 1;
	_xband_tmr->off_tmr.st_val[0].msec = 0;

}


/**
 * @brief Inline function for ON and OFF timer of edge payload
 *
 * @param _edge_brd_tmr - structure holds on and off timer parameter
 */
static inline void eps_edge_tmr_defaults(eps_dev_tmr_t *_edge_brd_tmr)
{
	_edge_brd_tmr->on_tmr.max_st_cnt= 5;

	_edge_brd_tmr->on_tmr.st_val[0].min  = 0;
	_edge_brd_tmr->on_tmr.st_val[0].sec  = 2;
	_edge_brd_tmr->on_tmr.st_val[0].msec = 0;
	_edge_brd_tmr->on_tmr.st_val[1].min  = 0;
	_edge_brd_tmr->on_tmr.st_val[1].sec  = 0;
	_edge_brd_tmr->on_tmr.st_val[1].msec = 100;
	_edge_brd_tmr->on_tmr.st_val[2].min  = 0;
	_edge_brd_tmr->on_tmr.st_val[2].sec  = 2;
	_edge_brd_tmr->on_tmr.st_val[2].msec = 0;
	_edge_brd_tmr->on_tmr.st_val[3].min  = 1;
	_edge_brd_tmr->on_tmr.st_val[3].sec  = 35;
	_edge_brd_tmr->on_tmr.st_val[3].msec = 0;
	_edge_brd_tmr->on_tmr.st_val[4].min  = 5;
	_edge_brd_tmr->on_tmr.st_val[4].sec  = 0;
	_edge_brd_tmr->on_tmr.st_val[4].msec = 0;

	_edge_brd_tmr->off_tmr.max_st_cnt= 5;

	_edge_brd_tmr->off_tmr.st_val[0].min  = 1;
	_edge_brd_tmr->off_tmr.st_val[0].sec  = 0;
	_edge_brd_tmr->off_tmr.st_val[0].msec = 0;
	_edge_brd_tmr->off_tmr.st_val[1].min  = 0;
	_edge_brd_tmr->off_tmr.st_val[1].sec  = 0;
	_edge_brd_tmr->off_tmr.st_val[1].msec = 10;
	_edge_brd_tmr->off_tmr.st_val[2].min  = 0;
	_edge_brd_tmr->off_tmr.st_val[2].sec  = 0;
	_edge_brd_tmr->off_tmr.st_val[2].msec = 10;
	_edge_brd_tmr->off_tmr.st_val[3].min  = 2;
	_edge_brd_tmr->off_tmr.st_val[3].sec  = 3;
	_edge_brd_tmr->off_tmr.st_val[3].msec = 10;
	_edge_brd_tmr->off_tmr.st_val[4].min  = 0;
	_edge_brd_tmr->off_tmr.st_val[4].sec  = 0;
	_edge_brd_tmr->off_tmr.st_val[4].msec = 10;
}



/**
 * @brief Inline function for ON and OFF timer of adcs payload
 *
 * @param _adcs_brd_tmr - structure holds on and off timer parameter
 */
static inline void eps_adcs_tmr_defaults(eps_dev_tmr_t *_adcs_brd_tmr)
{
	_adcs_brd_tmr->on_tmr.max_st_cnt= 3;

	_adcs_brd_tmr->on_tmr.st_val[0].min  = 0;
	_adcs_brd_tmr->on_tmr.st_val[0].sec  = 1;
	_adcs_brd_tmr->on_tmr.st_val[0].msec = 0;
	_adcs_brd_tmr->on_tmr.st_val[1].min  = 0;
	_adcs_brd_tmr->on_tmr.st_val[1].sec  = 5;
	_adcs_brd_tmr->on_tmr.st_val[1].msec = 0;
	_adcs_brd_tmr->on_tmr.st_val[2].min  = 0;
	_adcs_brd_tmr->on_tmr.st_val[2].sec  = 5;
	_adcs_brd_tmr->on_tmr.st_val[2].msec = 0;

	_adcs_brd_tmr->off_tmr.max_st_cnt= 3;

	_adcs_brd_tmr->off_tmr.st_val[0].min  = 0;
	_adcs_brd_tmr->off_tmr.st_val[0].sec  = 5;
	_adcs_brd_tmr->off_tmr.st_val[0].msec = 0;
	_adcs_brd_tmr->off_tmr.st_val[1].min  = 0;
	_adcs_brd_tmr->off_tmr.st_val[1].sec  = 1;
	_adcs_brd_tmr->off_tmr.st_val[1].msec = 0;
	_adcs_brd_tmr->off_tmr.st_val[2].min   = 0;
	_adcs_brd_tmr->off_tmr.st_val[2].sec   = 1;
	_adcs_brd_tmr->off_tmr.st_val[2].msec  = 0;
}


/**
 * @brief Inline function for ON and OFF timer of hrm
 *
 * @param _hrm_tmr- structure holds on and off timer parameter
 */
static inline void eps_hrm_tmr_defaults(eps_dev_tmr_t *_hrm_tmr)
{
	_hrm_tmr->on_tmr.max_st_cnt= 3;

	_hrm_tmr->on_tmr.st_val[0].min  = 20;
	_hrm_tmr->on_tmr.st_val[0].sec  = 0;
	_hrm_tmr->on_tmr.st_val[0].msec = 0;
	_hrm_tmr->on_tmr.st_val[1].min  = 0;
	_hrm_tmr->on_tmr.st_val[1].sec  = 30;
	_hrm_tmr->on_tmr.st_val[1].msec = 0;
	_hrm_tmr->on_tmr.st_val[2].min  = 2;
	_hrm_tmr->on_tmr.st_val[2].sec  = 0;
	_hrm_tmr->on_tmr.st_val[2].msec = 0;

	_hrm_tmr->off_tmr.max_st_cnt= 4;
}


/**
 * @brief Inline function for ON and OFF timer of GPS payload
 *
 * @param _gps_dc_brd_tmr- structure holds on and off timer parameter
 */
static inline void eps_gps_dc_tmr_defaults(eps_dev_tmr_t *_gps_dc_brd_tmr)
{
	_gps_dc_brd_tmr->on_tmr.max_st_cnt= 3;

	_gps_dc_brd_tmr->on_tmr.st_val[0].min  = 0;
	_gps_dc_brd_tmr->on_tmr.st_val[0].sec  = 1;
	_gps_dc_brd_tmr->on_tmr.st_val[0].msec = 0;
	_gps_dc_brd_tmr->on_tmr.st_val[1].min  = 1;
	_gps_dc_brd_tmr->on_tmr.st_val[1].sec  = 3;
	_gps_dc_brd_tmr->on_tmr.st_val[1].msec = 0;
	_gps_dc_brd_tmr->on_tmr.st_val[2].min  = 0;
	_gps_dc_brd_tmr->on_tmr.st_val[2].sec  = 3;
	_gps_dc_brd_tmr->on_tmr.st_val[2].msec = 0;

	_gps_dc_brd_tmr->off_tmr.max_st_cnt= 3;

	_gps_dc_brd_tmr->off_tmr.st_val[0].min  = 0;
	_gps_dc_brd_tmr->off_tmr.st_val[0].sec  = 1;
	_gps_dc_brd_tmr->off_tmr.st_val[0].msec = 0;
	_gps_dc_brd_tmr->off_tmr.st_val[1].min  = 0;
	_gps_dc_brd_tmr->off_tmr.st_val[1].sec  = 1;
	_gps_dc_brd_tmr->off_tmr.st_val[1].msec = 0;
	_gps_dc_brd_tmr->off_tmr.st_val[2].min  = 0;
	_gps_dc_brd_tmr->off_tmr.st_val[2].sec  = 1;
	_gps_dc_brd_tmr->off_tmr.st_val[2].msec = 0;
}




/**
 * @brief Inline function for ON and OFF timer of sband payload
 *
 * @param _sband_tmr - structure holds on and off timer parameter
 */
static inline void eps_sband_tmr_defaults(eps_dev_tmr_t *_sband_tmr)
{
	_sband_tmr->on_tmr.max_st_cnt= 2;

	_sband_tmr->on_tmr.st_val[0].min  = 0;
	_sband_tmr->on_tmr.st_val[0].sec  = 13;
	_sband_tmr->on_tmr.st_val[0].msec = 0;
	_sband_tmr->on_tmr.st_val[1].min  = 0;
	_sband_tmr->on_tmr.st_val[1].sec  = 0;
	_sband_tmr->on_tmr.st_val[1].msec = 10;

	_sband_tmr->off_tmr.max_st_cnt= 2;

	_sband_tmr->off_tmr.st_val[0].min  = 0;
	_sband_tmr->off_tmr.st_val[0].sec  = 3;
	_sband_tmr->off_tmr.st_val[0].msec = 0;
	_sband_tmr->off_tmr.st_val[1].min  = 0;
	_sband_tmr->off_tmr.st_val[1].sec  = 0;
	_sband_tmr->off_tmr.st_val[1].msec = 10;
}




/**
 * @brief Inline function for ON and OFF timer of payload server
 *
 * @param _ps_brd_tmr - structure holds on and off timer parameter
 */
static inline void eps_ps_brd_tmr_defaults(eps_dev_tmr_t *_ps_brd_tmr)
{
	_ps_brd_tmr->on_tmr.max_st_cnt= 5;

	_ps_brd_tmr->on_tmr.st_val[0].min  = 0;
	_ps_brd_tmr->on_tmr.st_val[0].sec  = 0;
	_ps_brd_tmr->on_tmr.st_val[0].msec = 50;
	_ps_brd_tmr->on_tmr.st_val[1].min  = 0;
	_ps_brd_tmr->on_tmr.st_val[1].sec  = 0;
	_ps_brd_tmr->on_tmr.st_val[1].msec = 10;
	_ps_brd_tmr->on_tmr.st_val[2].min  = 1;
	_ps_brd_tmr->on_tmr.st_val[2].sec  = 35;
	_ps_brd_tmr->on_tmr.st_val[2].msec = 0;

	_ps_brd_tmr->off_tmr.max_st_cnt= 5;

	_ps_brd_tmr->off_tmr.st_val[0].min  = 1;
	_ps_brd_tmr->off_tmr.st_val[0].sec  = 0;
	_ps_brd_tmr->off_tmr.st_val[0].msec = 0;
	_ps_brd_tmr->off_tmr.st_val[1].min  = 0;
	_ps_brd_tmr->off_tmr.st_val[1].sec  = 0;
	_ps_brd_tmr->off_tmr.st_val[1].msec = 10;
	_ps_brd_tmr->off_tmr.st_val[2].min  = 2;
	_ps_brd_tmr->off_tmr.st_val[2].sec  = 3;
	_ps_brd_tmr->off_tmr.st_val[2].msec = 0;
}


/**
 * @brief Inline function for default values of convertor board
 *
 * @param _set_conv_brd - structure holds eps convertor board parameter
 */
static inline void eps_set_conv_defaults(eps_set_conv_brd_s *_set_conv_brd)
{
	_set_conv_brd->mppt_enb_cnt 			=MAX_MPPT_CONV_CNT 	;
	_set_conv_brd->conv_op_enb_cnt 			=MAX_MPPT_CONV_CNT 	;
	_set_conv_brd->conv_op_volt_cnt 			=MAX_MPPT_CONV_CNT 	;
	_set_conv_brd->mem_set 			= 	TEMP_MEM;
	_set_conv_brd->mppt_enb[0]		=	1;
	_set_conv_brd->mppt_enb[1]		=	1;
	_set_conv_brd->mppt_enb[2]		=	1;
	_set_conv_brd->mppt_enb[3]		=	1;
	_set_conv_brd->op_conv_enb[0]	=	1;
	_set_conv_brd->op_conv_enb[1]	=	1;
	_set_conv_brd->op_conv_enb[2]	=	1;
	_set_conv_brd->op_conv_enb[3]	=	1;
	_set_conv_brd->op_conv_volt[0]	=	12;
	_set_conv_brd->op_conv_volt[1]	=	3.3;
	_set_conv_brd->op_conv_volt[2]	=	5;
	_set_conv_brd->op_conv_volt[3]	=	5;

	
}

/**
 * @brief Inline function for default values of battery board
 *
 * @param _set_bat_brd - structure holds eps mode parameter
 */
static inline void eps_set_batt_defaults(eps_set_btry_brd_s *_set_bat_brd)
{
	_set_bat_brd->temp_lmt_sns_cnt 			=MAX_BTRY_TMP_SNSR_CNT 	;
	_set_bat_brd->mem_set 			= 	TEMP_MEM;
	_set_bat_brd->cur_lmt_chrg		=	10;
	_set_bat_brd->cur_lmt_dischrg	=  -20;
        _set_bat_brd->temp_lmt[0][0]   =       5;  //low tmperature
        _set_bat_brd->temp_lmt[0][1]   =       7;
	_set_bat_brd->temp_lmt[1][0]	=	5;  //low tmperature
	_set_bat_brd->temp_lmt[1][1]	=	7;  //high temperature
	_set_bat_brd->temp_lmt[2][0]	=	5;
	_set_bat_brd->temp_lmt[2][1]	=   7;
	_set_bat_brd->temp_lmt[3][0]	=	5;
	_set_bat_brd->temp_lmt[3][1]	=	7;
	_set_bat_brd->temp_lmt[4][0]	=	5;
	_set_bat_brd->temp_lmt[4][1]	=	7;
	_set_bat_brd->temp_lmt[5][0]	=	5;
	_set_bat_brd->temp_lmt[5][1]	=	7;
	_set_bat_brd->temp_lmt[6][0]	=	5;
	_set_bat_brd->temp_lmt[6][1]	=	7;
	_set_bat_brd->temp_lmt[7][0]	=	5;
	_set_bat_brd->temp_lmt[7][1]	=	7;
	_set_bat_brd->heat_mode	        =	0;
	_set_bat_brd->heat_mode_flgs	=	0;

}

/**
 * @brief Inline function for default values of channel state
 *
 * @param _out_en - structure holds eps mode parameter
 */
static inline void eps_set_out_ch_defaults(eps_set_out_chnl_enb_s *_out_en)
{
	_out_en->mem_set 	= TEMP_MEM;
	EPS_SET_ON(_out_en->chnl1_8,0);
	EPS_SET_ON(_out_en->chnl1_8,1);
	EPS_SET_ON(_out_en->chnl1_8,2);
	EPS_SET_ON(_out_en->chnl1_8,3);
	EPS_SET_ON(_out_en->chnl1_8,4);
	EPS_SET_ON(_out_en->chnl1_8,5);
	EPS_SET_ON(_out_en->chnl1_8,6);
	EPS_SET_ON(_out_en->chnl1_8,7);
	EPS_SET_ON(_out_en->chnl9_12,8);
	EPS_SET_ON(_out_en->chnl9_12,9);
	EPS_SET_ON(_out_en->chnl9_12,10);
	EPS_SET_ON(_out_en->chnl9_12,11);
#if 0
        _out_en->state[EPS_PL_TRANSCELESTIAL]	=1;
	_out_en->state[EPS_X_BAND]				=1;
	_out_en->state[EPS_S_BAND]				=1;
        _out_en->state[EPS_ADCS0]				=1;
	_out_en->state[EPS_ADCS]				=1;
	_out_en->state[EPS_PROP_UNIT_THRUSTER]	=1;
	_out_en->state[EPS_PL_ZES]				=1;
	_out_en->state[EPS_PL_SAYARLABS]		=1;
	_out_en->state[EPS_PL_NETRA]			=1;
	_out_en->state[EPS_EDGE_BRD]			=1;
	_out_en->state[EPS_OBC_PS_GPS_STD_PL_BRD]=1;
	_out_en->state[EPS_HRM]					=1;
#endif
}

/**
 * @brief Inline function for default values of eps mode
 *
 * @param _set_mode_params - structure holds eps mode parameter
 */
static inline void eps_set_mode_params_defaults(eps_set_mode_s *_set_mode_params)
{
	_set_mode_params->mem_set 					= TEMP_MEM;
	_set_mode_params->nrml_mode_thrld_volt		=(float)EPS_BTRY_NORMAL_VAL;
	_set_mode_params->safe_mode_thrld_volt		=(float)EPS_BTRY_SAFE_VAL;
	_set_mode_params->crtl_mode_thrld_volt		=(float)EPS_BTRY_CRTCAL_VAL;
}

/**
 * @brief Inline function for default values of output channel current limit
 *
 * @param _out_ch_cur_lmt - structure holds output channel current limit parameter
 */
static inline void eps_set_out_chnl_cur_lmt_defaults(eps_set_out_chnl_crnt_lmt_s *_out_ch_cur_lmt)
{
	_out_ch_cur_lmt->chnl_cnt 			=MAX_VOLT_RAIL_CNT	;
	_out_ch_cur_lmt->mem_set 			=	TEMP_MEM;
#ifndef DRISHTI_EN 
	_out_ch_cur_lmt->chnl[ch1_12v]		=	2.5;
	_out_ch_cur_lmt->chnl[ch2_12v]		=	2.5;
	_out_ch_cur_lmt->chnl[ch3_5v]		=	2;
	_out_ch_cur_lmt->chnl[ch4_5v]		=	1;
	_out_ch_cur_lmt->chnl[ch5_5v]		=	1;
	_out_ch_cur_lmt->chnl[ch5_3v]		=	1;
	_out_ch_cur_lmt->chnl[ch5_btry]		=	2;
	_out_ch_cur_lmt->chnl[ch6_12v]		=	4;
	_out_ch_cur_lmt->chnl[ch6_3v]		=	4;
	_out_ch_cur_lmt->chnl[ch7_5v]		=	3;
	_out_ch_cur_lmt->chnl[ch7_btry]		=	3;
	_out_ch_cur_lmt->chnl[ch8_12v]		=	3;
	_out_ch_cur_lmt->chnl[ch9_5v]		=	8;
	_out_ch_cur_lmt->chnl[ch10_btry]	=	4;
	_out_ch_cur_lmt->chnl[ch11_btry]	=	4;
	_out_ch_cur_lmt->chnl[ch12_btry]	=	2;
#else
	_out_ch_cur_lmt->chnl[ch1_12v]		=	0.5;
	_out_ch_cur_lmt->chnl[ch2_12v]		=	0.5;
	_out_ch_cur_lmt->chnl[ch3_5v]		=	10;
	_out_ch_cur_lmt->chnl[ch4_5v]		=	1;
	_out_ch_cur_lmt->chnl[ch5_5v]		=	5.7;
	_out_ch_cur_lmt->chnl[ch5_3v]		=	1.4;
	_out_ch_cur_lmt->chnl[ch5_btry]		=	1.25;
	_out_ch_cur_lmt->chnl[ch6_12v]		=	1.33;
	_out_ch_cur_lmt->chnl[ch6_3v]		=	1.33;
	_out_ch_cur_lmt->chnl[ch7_5v]		=	1;
	_out_ch_cur_lmt->chnl[ch7_btry]		=	37.5;
#endif
}
#if 0
conv.addr[0] =  0x98;
conv.addr[1] =  0x01;
conv.addr[2] =  0x00;
conv.addr[3] =  0x20;

op_ch.addr[0] =  0x84;
op_ch.addr[1] =  0x01;
op_ch.addr[2] =  0x00;
op_ch.addr[3] =  0x20;
sts =  eps_get_variable_data(conv_brd,&conv,&var);
sts =  eps_get_variable_data(op_ch_brd,&op_ch,&var);

#endif

#endif

#ifdef EPS_DBG_EN
/**
 * @brief EPS status error print inline function
 *
 * @param sts - error status
 */
static inline void eps_sts_err_print(eps_err_sts_e sts)
{
	DEBUG_CPRINT(("EPS ERR - "));
	switch(sts)
	{
	case EPS_COM_FAIL:		DEBUG_CPRINT(("I2C\n"));		break;
	case EPS_INVLD_ARG:		DEBUG_CPRINT(("INP_ARG\n"));	break;
	case EPS_CRC_FAIL:		DEBUG_CPRINT(("CRC\n"));		break;
	case EPS_SET_PARAM_ERR:	DEBUG_CPRINT(("SET_PARAM\n"));break;
	case EPS_ERR:			DEBUG_CPRINT(("ERR\n"));		break;
	case EPS_NULL_PTR_ERR:	DEBUG_CPRINT(("NULL PTR\n"));	break;
	case EPS_SUCCESS:		DEBUG_CPRINT(("NONE\n"));		break;
	case EPS_RESP_ERR:			DEBUG_CPRINT(("EPS_RESP_ERR\n"));		break;
	}
}

/**
 * @brief EPS channel print inline function
 *
 * @param rd_ch - command ID
 */
static inline void eps_chnl_print(eps_cmd rd_ch)
{
	switch(rd_ch)
	{
	case EPS_SET_CONV_BRD          : DEBUG_CPRINT(("EPS_SET_CONV_BRD\t")); 	      break;
	case EPS_RD_BUF                : DEBUG_CPRINT(("EPS_RD_BUF\t")); 			      break;
	case EPS_GET_CONV_BRD_ST          : DEBUG_CPRINT(("EPS_GET_CONV_BRD_ST\t")); 	      break;
	case EPS_GET_CONV_BRD_RD          : DEBUG_CPRINT(("EPS_GET_CONV_BRD_RD\t")); 	      break;
	case EPS_SET_BTRY_BRD          : DEBUG_CPRINT(("EPS_SET_BTRY_BRD\t")); 	      break;
	case EPS_GET_BTRY_BRD_ST          : DEBUG_CPRINT(("EPS_GET_BTRY_BRD_ST\t")); 	      break;
	case EPS_GET_BTRY_BRD_RD          : DEBUG_CPRINT(("EPS_GET_BTRY_BRD_RD\t")); 	      break;
	case EPS_SET_OP_CHNL_PARM      : DEBUG_CPRINT(("EPS_SET_OP_CHNL_PARM\t"));      break;
	case EPS_SET_OP_CHNL_CUR       : DEBUG_CPRINT(("EPS_SET_OP_CHNL_CUR\t"));       break;
	case EPS_GET_OP_CHNL_PARM      : DEBUG_CPRINT(("EPS_GET_OP_CHNL_PARM\t"));      break;
    case EPS_GET_OP_CHNL_CUR_RD    : DEBUG_CPRINT(("EPS_GET_OP_CHNL_CUR_RD\t")); break;
    case EPS_GET_OP_CHNL_CUR_LMT_SET: DEBUG_CPRINT(("EPS_GET_OP_CHNL_CUR_LMT_SET\t")); break;
	case EPS_SET_MODE_PARM         : DEBUG_CPRINT(("EPS_SET_MODE_PARM\t"));	      break;
	case EPS_GET_MODE_PARM         : DEBUG_CPRINT(("EPS_GET_MODE_PARM\t"));         break;
	case EPS_GET_ALRT_FLAG         : DEBUG_CPRINT(("EPS_GET_ALRT_FLAG\t"));         break;
	case EPS_GET_ADDR_VAR_OP_BRD   : DEBUG_CPRINT(("EPS_GET_ADDR_VAR_OP_BRD\t"));   break;
	case EPS_GET_ADDR_VAR_CONV_BRD : DEBUG_CPRINT(("EPS_GET_ADDR_VAR_CONV_BRD\t")); break;
	case EPS_SET_RTC_DATA          : DEBUG_CPRINT(("EPS_SET_RTC_DATA\t"));			break;
	case EPS_GET_RTC_DATA		   : DEBUG_CPRINT(("EPS_GET_RTC_DATA\t"));          break;
	case EPS_GET_OP_CHNL_FW_VERS		   : DEBUG_CPRINT(("EPS_GET_FIRMWARE\t"));          break;
	case EPS_GET_CONV_BRD_FW_VERS		   : DEBUG_CPRINT(("EPS_GET_FIRMWARE\t"));          break;
        case EPS_SET_COM_TIMEOUT                   :DEBUG_CPRINT(("EPS_SET_OBC_COM_TIMEOUT\t"));          break;
        case EPS_GET_COM_TIMEOUT:    DEBUG_CPRINT(("EPS_GET_OBC_COM_TIMEOUT\t"));          break;

	}
}

/**
 * @brief EPS mode print inline function
 *
 * @param mode - eps mode
 */
static inline void eps_mode_print(uint8_t mode)
{
	DEBUG_CPRINT(("EPS_BTRY_MODE-"));
	switch(mode)
	{
	//case EPS_MODE_OFF  : DEBUG_CPRINT(("OFF\n"));
	case HW_BTRY_CRTCAL : DEBUG_CPRINT(("CRITICAL\n"));
	case HW_BTRY_SAFE : DEBUG_CPRINT(("SAFE\n"));
	case HW_BTRY_NORMAL : DEBUG_CPRINT(("NRML\n"));
	//case EPS_MODE_FULL : DEBUG_CPRINT(("FULL\n"));
	}
}
#endif

/**
* @brief EPS thread manages eps paarameter read from driver and control output channel
*
* @param[out]  args - unused
*
*/
void *eps_proc(void* args);

/**
 * @brief Battery timer callback
 */
void eps_batt_tmr_cb();

/**
* @brief API for eps alert interrupt callback
*
*/
//void eps_alert_cb();

/**
 * @brief EPS Battery check function
 */
void eps_battery_check();

/**
 * @brief EPS alert flag check function
 */
void eps_alert_check();

/**
 * @brief EPS OBC send battery status function
 *
 * @param eps_btry_sts - battery status
 *
 * @return - eps error status
 */
eps_ctrlr_err_sts_s eps_obc_send_bat_sts(sat_btry_sts_s eps_btry_sts);

/**
 * @brief EPS message send function
 *
 * @param ch_no - Channel number
 * @param state - state of channel
 *
 * @return - eps error status
 */
eps_ctrlr_err_sts_s eps_msg_send(uint8_t ch_no, uint8_t state);

/**
 * @brief This API packs ipc data and trigger itc send to destination thread
 *
 * @param[in]  dst_id  	: destination id of thread
 * @param[in]  pld_info : information on payload
 * @param[in]  msg_id  	: Pointer to data packed with tc tm headers
 * @param[in]  pld 		: Pointer to received data
 * @param[in]  pld_size	: size of payload message which is accessed from pld pointer
 *
 * @return status of eps_ctrlr_err_sts_s
 * @retval equal to zero -> Success / greater than zero -> failure.
 */
eps_ctrlr_err_sts_s eps_ctrl_send_ipc_msg_pld(uint8_t dst_id, uint8_t pld_info, uint16_t msg_id, uint8_t *pld, uint8_t pld_size);

/**
* @brief  This API initialize the output channel default parameters and power timer required.
* 		  This is executed once during start of the program.
*
*/
void eps_ctrl_dev_init();

/**
* @brief  This API stops the power timer.
*
*/
void eps_ctrl_dev_deinit();

/**
* @brief This API loads pre-stored timer counter value for power state change of individual channel
*   	 Value loaded from nvm memory if it is valid or it uses data from inline function
* 		 This API runs only once during start of program.
*
*/
void eps_ctrl_dev_defaults();

/**
* @brief This API controls entire module power on/off sequence
*
*/
void eps_pwr_seq_st(eps_ch_s ch_no);

/**
* @brief This API is timer callback. API hits every 10 msec provided any one channel on/off sequence
*
*/
void eps_pwr_tmr_cb();
#if 0
/**
* @brief This API controls hrm power on/off sequence
*
*/
void eps_hrm_pwr_seq();
#endif
/**
* @brief This API updates timer current counter values of individual channel power on/off sequence
*
* @param[in] ch_no : channel number of the timer update
*
*/
void eps_pwr_tmr_cntr_updt(eps_ch_s ch_no);

/**
* @brief This API updates the battery timer
*
* @param[in] ch_no : channel number of the timer update
*
*/
void eps_btry_tmr_updt(eps_dev_tmr_t *_btry_tmr);

/**
 * @brief EPS control battery mode map function
 */
void eps_ctrl_btry_mode_map();

/**
* @brief This API gets data from eps driver and extract re-pack the information
*
* @param[in]  _chnl : input channel gives which board parameter to be read from esp drivers
*
* @return status of eps_ctrlr_err_sts_s
* @retval equal to zero -> Success / greater than zero -> failure.
*/
eps_ctrlr_err_sts_s eps_hw_values_read(uint8_t _chnl);

/**
* @brief This API controls on/off state of output for channel based on current battery mode.
*		 Whenever battery mode changes this API is called.
*/
void eps_ctrl_btry_mode_map();

/**
* @brief This API packs ipc data and trigger itc send to destination thread
*
* @param[in] _btry_volt : destination id of thread
*
*/
void eps_ctrlr_btry_vs_mode(float _btry_volt);

/**
* @brief This API sets battery threshold limit for all 4 modes that can be changed dynamically from GS
*
* @param[in] _eps_btry_thrshld - structure holds the battery voltage
*
*/
void eps_set_btry_thrshld(eps_btry_thrshld_s *_eps_btry_thrshld);
void eps_btry_tmr_deinit();
/**
* @brief  This API verify the channel state and store the channel status to NVM memory
*
* @param[in] chnl_state - eps channel state from eps module
* @param[in]  nvm_chnl_state - channel state from NVM memory
*/
void eps_ctrl_verify_chnl_state_nvm(eps_get_out_chnl_sts_s *chnl_state,uint8_t *nvm_chnl_state);
void eps_chnl_on_off_trig_after_com_scs();
void eps_com_fail_cb();
void eps_init_com_time_out();
#endif /* DRIVERS_AHW_DRIVERS_EPS_INC_EPS_H_ */
