#include "eps_ctrlr_init.h"
#include "nvm.h"
#include "logger.h"
#include "exo_gpio.h"
#include "exo_tctm_ipc.h"
#include "eps_btlr_driver.h"

sat_dev_sts_s sat_dev_sts[MAX_SAT_DEV_CNT];

static os_timer_handle_ptr 	eps_pwr_tmr;

static eps_dev_tmr_t 		pwr_tmr[MAX_SAT_DEV_CNT];
static eps_dev_crnt_tmr_s 	eps_dev_crnt_tmr[MAX_SAT_DEV_CNT];
static eps_btry_ch_map_s 	eps_btry_ch_map;
static uint8_t 				eps_tmr_cb_en_cntr=0;
extern eps_hlth_info_s 		eps_hlth_info;
static uint8_t hrm_err_cntr=0;
static uint8_t eps_nvm_chnl_st_err_flg=0;
static uint8_t channel_status[MAX_SAT_DEV_CNT] = {0};
extern eps_beakcon_info_s  eps_get_info;
extern uint16_t nvm_eps_chnl_ovr_cur_err;
extern uint16_t eps_chnl_num ;
uint8_t eps_com_fail_cnt=EPS_MAX_TM_MIN	;
uint8_t eps_com_fail_flg=0;

eps_ctrlr_err_sts_s eps_obc_ch_state_ind(uint8_t ch_no, uint8_t state);

/**
 * @brief  This API verify the channel state and store the channel status to NVM memory
 *
 */
void eps_ctrl_verify_chnl_state_nvm(eps_get_out_chnl_sts_s *chnl_state,uint8_t *nvm_chnl_state)
{
	uint8_t eps_sts;
	uint8_t data[2];
	uint8_t chnl_no ;
	for(chnl_no = 0; chnl_no < MAX_SAT_DEV_CNT ; chnl_no++)
	{
		if(chnl_no < 8)
		{
			if(((chnl_state->chnl1_8 >> chnl_no)& 1) != nvm_chnl_state[chnl_no])
			{
				eps_nvm_chnl_st_err_flg = 1;
				nvm_chnl_state[chnl_no] = (chnl_state->chnl1_8 >> chnl_no)& 1;
				nvm_parameter_write(NVM_DATA,(NVM_HW_PL_TRANSCELESTIAL+chnl_no),(uint8_t*)&nvm_chnl_state[chnl_no]);
			}
		}
		else if(chnl_no < 12)
		{
			if(((chnl_state->chnl9_12 >> (chnl_no%8))& 1) != nvm_chnl_state[chnl_no])
			{
				eps_nvm_chnl_st_err_flg = 1;
				nvm_chnl_state[chnl_no] = (chnl_state->chnl9_12 >> (chnl_no%8))& 1;
				nvm_parameter_write(NVM_DATA,(NVM_HW_PL_TRANSCELESTIAL+chnl_no),(uint8_t*)&nvm_chnl_state[chnl_no]);
			}
		}
		else if(chnl_no == HW_PL_SERVER)
		{
			if(eps_get_chnl_state_pl_srvr() == EPS_SUCCESS)
			{
				eps_sts = 1;
			}
			else
			{
				eps_sts = 0;
			}
			if(nvm_chnl_state[HW_PL_SERVER] != eps_sts)
			{
				nvm_chnl_state[HW_PL_SERVER] = eps_sts;
				nvm_parameter_write(NVM_DATA,(NVM_HW_PL_TRANSCELESTIAL+chnl_no),(uint8_t*)&nvm_chnl_state[chnl_no]);
			}
		}
		else if(chnl_no == HW_GPS)
		{
			if(eps_get_chnl_state_gps() == EPS_SUCCESS)
			{
				nvm_chnl_state[HW_GPS] = 1;
			}
			else
			{
				nvm_chnl_state[HW_GPS] = 0;
			}
			nvm_parameter_write(NVM_DATA,(NVM_HW_PL_TRANSCELESTIAL+chnl_no),(uint8_t*)&nvm_chnl_state[chnl_no]);
		}
		else
		{
			//invald channel number
		}
		sat_dev_sts[chnl_no].hw_sts=nvm_chnl_state[chnl_no];
		if(sat_dev_sts[chnl_no].hw_sts)
		{
			data[0] = chnl_no;
			data[1] = sat_dev_sts[chnl_no].hw_sts;
			eps_ctrl_send_ipc_msg_pld(OBC_MAIN,0,EPS_OBC_DEV_STS_IND,(uint8_t *)data,2);
		}
	}
}

/**
 * @brief This API loads pre-stored timer counter value for power state change of individual channel
 *   	 Value loaded from nvm memory if it is valid or it uses data from inline function
 * 		 This API runs only once during start of program.
 *
 */
void eps_ctrl_dev_defaults()
{
#ifdef EPS_SIMU_ENABLE
	uint8_t eps_ch_cnt=0;
#else
	uint8_t eps_ch_cnt=0;
	nvm_parameter_read(NVM_DATA,RSVD_BIT_1,(uint8_t*)&eps_ch_cnt);
#endif

	if(eps_ch_cnt != 0xA5)
	{
		eps_edge_tmr_defaults(&pwr_tmr[HW_EDGE_BRD]);
		eps_adcs_tmr_defaults(&pwr_tmr[HW_ADCS]);
		eps_gps_dc_tmr_defaults(&pwr_tmr[HW_GPS]);
		eps_ps_brd_tmr_defaults(&pwr_tmr[HW_PL_SERVER]);
		eps_sband_tmr_defaults(&pwr_tmr[HW_S_BAND]);
		eps_xband_tmr_defaults(&pwr_tmr[HW_X_BAND]);
		eps_pl_trans_tmr_defaults(&pwr_tmr[HW_PL_TRANSCELESTIAL]);
		eps_pl_netra_tmr_defaults(&pwr_tmr[HW_PL_NETRA]);
		eps_obc_tmr_defaults(&pwr_tmr[HW_OBC_PS_GPS_STD_PL_BRD]);
		eps_thrstr_tmr_defaults(&pwr_tmr[HW_PROP_UNIT_THRUSTER]);
		eps_hrm_tmr_defaults(&pwr_tmr[HW_HRM]);

#ifdef JANUS1
		eps_pl_syrlbs_tmr_defaults(&pwr_tmr[HW_PL_SAYARLABS]);
		eps_pl_zes_tmr_defaults(&pwr_tmr[HW_PL_ZES]);
#else
		eps_pl_sts300_tmr_defaults(&pwr_tmr[HW_PL_STS300]);
		eps_pl_uhf_tmr_defaults(&pwr_tmr[HW_UHF]);
		eps_pl_scanway_tmr_defaults(&pwr_tmr[HW_PL_SCANWAY]);
#endif
		eps_ctrlr_set_ch_valid_defaults(&eps_btry_ch_map);

		nvm_parameter_write(NVM_DATA,EPS_BTRY_CH_MAP,(uint8_t*)&eps_btry_ch_map);

		for(eps_ch_cnt=0;eps_ch_cnt<MAX_SAT_DEV_CNT;eps_ch_cnt++)
		{
			nvm_parameter_write(NVM_DATA,(EPS_PWR_TMR1+eps_ch_cnt),(uint8_t*)&pwr_tmr[eps_ch_cnt]);
		}
		eps_ch_cnt=0xA5;
		nvm_parameter_write(NVM_DATA,RSVD_BIT_1,(uint8_t*)&eps_ch_cnt);
		eps_chnl_eligible_to_restart(&eps_chnl_num);
		nvm_parameter_write(NVM_DATA,EPS_ELIGIBLE_CHNL,(uint8_t*)&eps_chnl_num);
	}
	else  // read from NVM memory database
	{
		for(eps_ch_cnt=0;eps_ch_cnt<MAX_SAT_DEV_CNT;eps_ch_cnt++)
		{
			nvm_parameter_read(NVM_DATA,(EPS_PWR_TMR1+eps_ch_cnt),(uint8_t*)&pwr_tmr[eps_ch_cnt]);
		}
		nvm_parameter_read(NVM_DATA,EPS_BTRY_CH_MAP,(uint8_t*)&eps_btry_ch_map);

		for(eps_ch_cnt=0;eps_ch_cnt<MAX_SAT_DEV_CNT;eps_ch_cnt++)
		{
			nvm_parameter_read(NVM_DATA,(NVM_HW_PL_TRANSCELESTIAL+eps_ch_cnt),(uint8_t*)&channel_status[eps_ch_cnt]);
		}
		nvm_parameter_read(NVM_DATA,EPS_ELIGIBLE_CHNL,(uint8_t*)&eps_chnl_num);
		nvm_parameter_read(NVM_DATA,EPS_CHNL_OVR_CUR_ERR,(uint8_t*)&nvm_eps_chnl_ovr_cur_err);
	}
}

/**
 * @brief  This API stops the power timer.
 *
 */
void eps_ctrl_dev_deinit()
{
	os_timer_stop(eps_pwr_tmr);
}

/**
 * @brief This API controls on/off state of output for channel based on current battery mode.
 *		 Whenever battery mode changes this API is called.
 */
void eps_ctrl_btry_mode_map()
{
	uint8_t ch_no=0;
	static uint8_t eps_mode_old=0;
	if(eps_mode_old != sat_btry_info.status)
	{
#ifdef EPS_DBG_EN
		log_id_with_one_arg(LOG_INFO_L1,LOG_EPS,EPS_MODE__u8_,sat_btry_info.status);
#endif
		DEBUG_CPRINT(("Battery mode :%d\n",sat_btry_info.status));

		eps_ctrl_send_ipc_msg_pld(OBC_MAIN,0,EPS_OBC_BAT_STS_IND,(uint8_t *)&sat_btry_info.status,1);

		for(ch_no=0;ch_no<MAX_SAT_DEV_CNT;ch_no++)
		{
			if(eps_btry_ch_map.valid_on[sat_btry_info.status] & ((uint16_t)1<<ch_no))
			{
				// turning device automatically on based on channel map
				if(eps_btry_ch_map.auto_on[sat_btry_info.status] & ((uint16_t)1<<ch_no))
				{
					if(sat_dev_sts[ch_no].hw_sts == PWR_ERR || (sat_dev_sts[ch_no].hw_sts == PWR_SD))
					{
						eps_dev_crnt_tmr[ch_no].enable 	= 0;
						eps_dev_crnt_tmr[ch_no].cntr 	= 0;
						eps_dev_crnt_tmr[ch_no].state 	= 1;
						sat_dev_sts[ch_no].hw_sts 		= PWR_OFF;
					}
					if(sat_dev_sts[ch_no].hw_sts == PWR_OFF)
						eps_ctrl_en_chnl(ch_no,EPS_PWR_ON);
				}
			}
			else
			{
				if (sat_dev_sts[ch_no].hw_sts == PWR_ERR)
				{
					eps_dev_crnt_tmr[ch_no].enable 	= 0;
					eps_dev_crnt_tmr[ch_no].cntr 	= 0;
					eps_dev_crnt_tmr[ch_no].state 	= 1;
					sat_dev_sts[ch_no].hw_sts 		= PWR_ON;
				}
				if(sat_dev_sts[ch_no].hw_sts == PWR_ON)
					eps_ctrl_en_chnl(ch_no,PWR_OFF);
			}
		}
		eps_mode_old = sat_btry_info.status;
	}
}

/**
 * @brief This API is for copying incoming data to structure eps_btry_ch_map
 *
 */
eps_ctrlr_err_sts_s eps_ctrl_set_btry_ch_map(eps_btry_ch_map_s *_eps_btry_ch_map)
{
	if(_eps_btry_ch_map->mode_cnt == EPS_MODE_CNT)
	{
#ifdef LINUX_TEMP_PORT
		DEBUG_CPRINT(("btry chnl map valid : %x \n",_eps_btry_ch_map->valid_on[0]));
		DEBUG_CPRINT(("btry chnl map valid: %x \n",_eps_btry_ch_map->valid_on[1]));
		DEBUG_CPRINT(("btry chnl map valid: %x \n",_eps_btry_ch_map->valid_on[2]));
		DEBUG_CPRINT(("btry chnl map auto on: %x \n",_eps_btry_ch_map->auto_on[0]));
		DEBUG_CPRINT(("btry chnl map auto on : %x \n",_eps_btry_ch_map->auto_on[1]));
		DEBUG_CPRINT(("btry chnl map auto on : %x \n",_eps_btry_ch_map->auto_on[2]));
#endif
		os_memcpy(&eps_btry_ch_map,_eps_btry_ch_map,sizeof(eps_btry_ch_map_s));
		return EPS_CTRL_SUCCESS;
	}
	return EPS_CTRL_PARAM_ERR;
}

/**
 * @brief This API is for copying existing data to structure eps_btry_ch_map
 *
 */
eps_ctrlr_err_sts_s eps_ctrl_get_btry_ch_map(eps_btry_ch_map_s *_eps_btry_ch_map)
{

#if LINUX_TEMP_PORT
	DEBUG_CPRINT(("btry chnl : %x \n",_eps_btry_ch_map->valid_on[0]));
	DEBUG_CPRINT(("btry chnl : %x \n",_eps_btry_ch_map->valid_on[1]));
	DEBUG_CPRINT(("btry chnl : %x \n",_eps_btry_ch_map->valid_on[2]));

	DEBUG_CPRINT(("btry chnl : %x \n",_eps_btry_ch_map->auto_on[0]));
	DEBUG_CPRINT(("btry chnl : %x \n",_eps_btry_ch_map->auto_on[1]));
	DEBUG_CPRINT(("btry chnl : %x \n",_eps_btry_ch_map->auto_on[2]));
#endif
	os_memcpy(_eps_btry_ch_map,&eps_btry_ch_map,sizeof(eps_btry_ch_map_s));
	return EPS_CTRL_SUCCESS;
}

/**
 * @brief This API sets power timer for individual channel which triggered from TC TM
 *
 */
eps_ctrlr_err_sts_s eps_ctrl_set_pwr_tmr(eps_dev_tmr_c *eps_dev_tmr)
{
	if(eps_dev_tmr->ch_no < MAX_SAT_DEV_CNT)
	{

#ifdef LINUX_TEMP_PORT
		DEBUG_CPRINT(("Decode DATA cnt:%d\n",eps_dev_tmr->ch_tmr_val.on_tmr.max_st_cnt));

		for(uint8_t cnt = 0 ; cnt < eps_dev_tmr->ch_tmr_val.on_tmr.max_st_cnt; cnt++)
		{
			DEBUG_CPRINT(("on_tmr[%d] \n",eps_dev_tmr->ch_tmr_val.on_tmr.st_val[cnt].min));
			DEBUG_CPRINT(("on_tmr[%d] \n",eps_dev_tmr->ch_tmr_val.on_tmr.st_val[cnt].sec));
			DEBUG_CPRINT(("on_tmr[%d] \n",eps_dev_tmr->ch_tmr_val.on_tmr.st_val[cnt].msec));
		}

		DEBUG_CPRINT(("Decode DATA cnt:%d\n",eps_dev_tmr->ch_tmr_val.off_tmr.max_st_cnt));

		for(uint8_t cnt = 0 ; cnt < eps_dev_tmr->ch_tmr_val.on_tmr.max_st_cnt; cnt++)
		{
			DEBUG_CPRINT(("off_tmr[%d] \n",eps_dev_tmr->ch_tmr_val.off_tmr.st_val[cnt].min));
			DEBUG_CPRINT(("off_tmr[%d] \n",eps_dev_tmr->ch_tmr_val.off_tmr.st_val[cnt].sec));
			DEBUG_CPRINT(("off_tmr[%d] \n",eps_dev_tmr->ch_tmr_val.off_tmr.st_val[cnt].msec));
		}
#endif
		nvm_parameter_write(NVM_DATA,(EPS_PWR_TMR1+eps_dev_tmr->ch_no),(uint8_t*)&pwr_tmr[eps_dev_tmr->ch_no]);
	}
	return EPS_CTRL_SUCCESS;
}

/**
 * @brief This API triggers on off sequence of output channel provided current battery voltage
 *
 * @param[in]  ch_no  : output channel selection
 * @param[in]  state  : on off request for channel number
 *
 * @return status of eps_ctrlr_err_sts_s
 * @retval equal to zero -> Success / greater than zero -> failure.
 *
 */
eps_ctrlr_err_sts_s eps_ctrl_en_chnl(eps_ch_s ch_no,eps_ch_state state)
{
	eps_ctrlr_err_sts_s eps_sts = EPS_CTRL_SUCCESS;

	log_id_with_two_arg(LOG_INFO_L1, LOG_EPS, BTRY_REQ_OP_CH__u8__STATE__u8_,ch_no,state);
	DEBUG_CPRINT(("Channel number : %d Power state : %d\n",ch_no,state));
#if 0
//#ifdef DRISHTI_EN

	if((state == EPS_PWR_RSTRT)  || (state == EPS_PWR_OFF))
	{
		eps_sts= eps_en_chnl(ch_no,PWR_OFF);

		if(eps_sts == EPS_CTRL_SUCCESS)
			sat_dev_sts[ch_no].hw_sts = PWR_OFF;
	}

	if((state == EPS_PWR_RSTRT)  || (state == EPS_PWR_ON))
	{
		eps_sts= eps_en_chnl(ch_no,PWR_ON);
		if(eps_sts == EPS_CTRL_SUCCESS)
			sat_dev_sts[ch_no].hw_sts = PWR_ON;
	}

	if(eps_sts == EPS_CTRL_SUCCESS)
	{
		if(ch_no < MAX_EPS_DEV_CNT)
			eps_obc_ch_state_ind(ch_no ,state);
	}

//#else
#endif
	switch(state)
	{
	case EPS_PWR_RSTRT:
	{
#ifndef DRISHTI_EN
		if((ch_no == HW_OBC_PS_GPS_STD_PL_BRD) || (ch_no == HW_HRM) || (ch_no == HW_X_BAND))
#else
                if(0)
#endif
			eps_sts = EPS_CTRL_PARAM_ERR;
		else
		{
			switch(sat_dev_sts[ch_no].hw_sts)
			{
			case PWR_BOOT:
			case PWR_SD:	eps_sts = EPS_CTRL_ERR;							break;
			case PWR_RSTRT:	eps_sts = EPS_CTRL_IN_PROG;						break;
			case PWR_ON:
			case PWR_ERR:	sat_dev_sts[ch_no].hw_sts = PWR_RSTRT;			break;
			case PWR_OFF:
				if(eps_btry_ch_map.valid_on[sat_btry_info.status] & ((uint8_t)1 << ch_no))
					sat_dev_sts[ch_no].hw_sts = PWR_BOOT;  //Check power on elegiblity status
				else
				{
					eps_sts = EPS_CTRL_BTRY_ERR;
#ifdef EPS_DBG_EN
					DEBUG_CPRINT(("\nBTRY_CH_MAP_ERR - ch[%d]-btry[%d]",ch_no,sat_btry_info.status));
					log_id_with_two_arg(LOG_ERROR, LOG_EPS, BTRY_CH_MAP_ERR_CH_u8_BTRY_u8_,ch_no,sat_btry_info.status);
#endif
				}
				break;
			}
		}
	}
	break;

	case EPS_PWR_ON:
	{
		if(((nvm_eps_chnl_ovr_cur_err >> ch_no) & 0x01) == 0)
		{
			switch(sat_dev_sts[ch_no].hw_sts)
			{
			case PWR_OFF:
#ifndef DRISHTI_EN
				if(!(ch_no == HW_X_BAND))
				{
#endif
					if(eps_btry_ch_map.valid_on[sat_btry_info.status] & ((uint8_t)1 << ch_no))
						sat_dev_sts[ch_no].hw_sts = PWR_BOOT;  //Check power on elegiblity status
					else
					{
						eps_sts = EPS_CTRL_BTRY_ERR;
#ifdef EPS_DBG_EN
						DEBUG_CPRINT(("\nBTRY_CH_MAP_ERR - ch[%d]-btry[%d]",ch_no,sat_btry_info.status));
						log_id_with_two_arg(LOG_ERROR, LOG_EPS, BTRY_CH_MAP_ERR_CH_u8_BTRY_u8_,ch_no,sat_btry_info.status);
#endif
					}
#ifndef DRISHTI_EN
				}
				else
				{
					eps_sts= EPS_CTRL_PARAM_ERR;
				}
#endif
				break;

			case PWR_BOOT:	eps_sts = EPS_CTRL_IN_PROG;		break;
			case PWR_ON:	eps_sts = EPS_CTRL_PARAM_ERR;	break;
			case PWR_SD:
			case PWR_RSTRT:	eps_sts = EPS_CTRL_ERR;			break;
			default: break;
			}
		}
		else
		{
			eps_sts = EPS_CTRL_CHNL_OVR_CUR_ERR;
		}
	}
	break;

	case  EPS_PWR_OFF:
	{
		switch(sat_dev_sts[ch_no].hw_sts)
		{
		case PWR_ON:	sat_dev_sts[ch_no].hw_sts = PWR_SD;	break;
		case PWR_RSTRT:	eps_sts	= EPS_CTRL_ERR;				break;
		case PWR_BOOT:	eps_sts = EPS_CTRL_ERR;				break;
		case PWR_OFF:	eps_sts = EPS_CTRL_PARAM_ERR;		break;
		case PWR_SD:	eps_sts = EPS_CTRL_IN_PROG;			break;

		default:			break;
		}
	}
	}

	if(eps_sts==EPS_CTRL_SUCCESS)
	{
		eps_dev_crnt_tmr[ch_no].state = 0;
		eps_ctrl_send_ipc_msg_pld(EPS_TASK, EPS_HW_PWR_SEQ, ch_no,NULL,0);
	}
//#endif

	return(eps_sts);
}

/**
 * @brief This API triggers status indication for OBC FSM
 *
 * @param[in]  ch_no  : output channel number
 * @param[in]  state  : output channel number
 *
 * @return status of eps_ctrlr_err_sts_s
 * @retval equal to zero -> Success / greater than zero -> failure.
 *
 */
eps_ctrlr_err_sts_s eps_obc_ch_state_ind(uint8_t ch_no, uint8_t state)
{
	uint8_t data[2];
	data[0] = ch_no;
	data[1] = state;
	eps_ctrl_send_ipc_msg_pld(OBC_MAIN,0,EPS_OBC_DEV_STS_IND,(uint8_t *)data,2);
	DEBUG_CPRINT(("Channel number :%d Channel power status : %d\n",data[0],data[1]));
	if(ch_no < MAX_SAT_DEV_CNT)
	{
		if(state)
			eps_hlth_info.dev_hw_sts |= ((uint16_t)1<<ch_no);
		else
			eps_hlth_info.dev_hw_sts &= ~((uint16_t)1<<ch_no);
		nvm_parameter_write(NVM_DATA,(NVM_HW_PL_TRANSCELESTIAL+ch_no),(uint8_t*)&state);
	}
	return EPS_SUCCESS;
}

/**
 * @brief This API is timer callback. API hits every 10 msec provided any one channel on/off sequence
 *
 */
void eps_pwr_tmr_cb()
{
	uint8_t eps_dev_cnt=0;
	uint8_t eps_tmr_cb_en_cntr_tmp = 0;

	while(eps_dev_cnt < MAX_SAT_DEV_CNT)
	{
		if(eps_dev_crnt_tmr[eps_dev_cnt].enable)
		{
			eps_tmr_cb_en_cntr_tmp = 1;
			if(eps_dev_crnt_tmr[eps_dev_cnt].cntr)
				eps_dev_crnt_tmr[eps_dev_cnt].cntr--;
			else
			{
				eps_dev_crnt_tmr[eps_dev_cnt].enable=0;
				eps_ctrl_send_ipc_msg_pld(EPS_TASK, EPS_HW_PWR_SEQ, eps_dev_cnt,NULL,0);
			}
		}
		eps_dev_cnt++;
	}

	if(eps_tmr_cb_en_cntr_tmp==0)
	{
		if(eps_tmr_cb_en_cntr)
			eps_tmr_cb_en_cntr--;
		else
			os_timer_stop(eps_pwr_tmr);
	}
}

/**
 * @brief This API updates timer current counter values of individual channel power on/off sequence
 *
 */
void eps_pwr_tmr_cntr_updt(eps_ch_s ch_no)
{
	if(sat_dev_sts[ch_no].hw_sts==PWR_BOOT)
		eps_dev_crnt_tmr[ch_no].cntr = eps_pwr_tmr_conv(pwr_tmr[ch_no].on_tmr.st_val[eps_dev_crnt_tmr[ch_no].state]);
	else
		eps_dev_crnt_tmr[ch_no].cntr = eps_pwr_tmr_conv(pwr_tmr[ch_no].off_tmr.st_val[eps_dev_crnt_tmr[ch_no].state]);

	eps_dev_crnt_tmr[ch_no].state += 1;

	if(eps_dev_crnt_tmr[ch_no].cntr==0) // enable next state immediately if zero  timer value
		eps_ctrl_send_ipc_msg_pld(EPS_TASK, EPS_HW_PWR_SEQ, ch_no,NULL,0);
	else
	{
		eps_dev_crnt_tmr[ch_no].enable=1;
		if(eps_tmr_cb_en_cntr == 0)
			os_timer_start(eps_pwr_tmr,(os_tick_time_t)EPS_PWR_TMR);
		eps_tmr_cb_en_cntr = 250;  //2.5 seconds to disable timer callback if no new power on / off request
	}
}

#ifdef JANUS1

/**
 * @brief This API controls sayarlabs payload power on/off sequence
 *
 */

void eps_pl_syrlbs_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_PL_SAYARLABS].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_PL_SAYARLABS].state)
		{
		case 0:
			eps_sts= eps_en_chnl(HW_PL_SAYARLABS,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_PL_SAYARLABS);
			break;

		case 1:
			sat_dev_sts[HW_PL_SAYARLABS].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_PL_SAYARLABS ,EPS_PWR_ON);
			break;
		}
	}
	else if((sat_dev_sts[HW_PL_SAYARLABS].hw_sts == PWR_SD) || (sat_dev_sts[HW_PL_SAYARLABS].hw_sts == PWR_RSTRT))
	{
		switch(eps_dev_crnt_tmr[HW_PL_SAYARLABS].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_PL_SAYARLABS,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_PL_SAYARLABS);
			break;

		case 1:
			eps_sts= eps_en_chnl(HW_PL_SAYARLABS,OFF);
			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_PL_SAYARLABS].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_PL_SAYARLABS].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_PL_SAYARLABS,PWR_ON);
				}
				else
					sat_dev_sts[HW_PL_SAYARLABS].hw_sts = PWR_OFF;
			}

			break;
		}
	}

	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN
		DEBUG_CPRINT(("PL_SYRLBS_PWR ERR=%d\n",eps_dev_crnt_tmr[HW_PL_SAYARLABS].state));
		log_id_with_one_arg(LOG_ERROR,LOG_EPS,PL_SYRLBS_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_PL_SAYARLABS].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_PL_SAYARLABS].hw_sts = PWR_ERR;
	}
}
#else

#endif

/**
 * @brief This API controls netra payload power on/off sequence
 *
 */
void eps_pl_netra_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_PL_NETRA].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_PL_NETRA].state)
		{
		case 0:
			eps_sts= eps_en_chnl(HW_PL_NETRA,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_PL_NETRA);

			break;

		case 1:
			sat_dev_sts[HW_PL_NETRA].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_PL_NETRA ,EPS_PWR_ON);
			log_id(LOG_INFO_L2,LOG_EPS,NETRA_HW_STS_PWR_ON);
			break;
		}
	}
	else if((sat_dev_sts[HW_PL_NETRA].hw_sts == PWR_SD) || (sat_dev_sts[HW_PL_NETRA].hw_sts == PWR_RSTRT))
	{
		switch(eps_dev_crnt_tmr[HW_PL_NETRA].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_PL_NETRA,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_PL_NETRA);
			break;

		case 1:
			eps_sts= eps_en_chnl(HW_PL_NETRA,OFF);
			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_PL_NETRA].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_PL_NETRA].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_PL_NETRA,PWR_ON);
				}
				else
					sat_dev_sts[HW_PL_NETRA].hw_sts = PWR_OFF;
				log_id(LOG_INFO_L2,LOG_EPS,NETRA_HW_STS_PWR_OFF);
			}
			break;
		}
	}
	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN
		DEBUG_CPRINT(("PL_NETRA_PWR ERR=%d\n",eps_dev_crnt_tmr[HW_PL_NETRA].state));
		log_id_with_one_arg(LOG_ERROR,LOG_EPS,PL_NETRA_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_PL_NETRA].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_PL_NETRA].hw_sts = PWR_ERR;
	}
}

/**
 * @brief This API controls transcelestial payload power on/off sequence
 *
 */
void eps_pl_trans_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_PL_TRANSCELESTIAL].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_PL_TRANSCELESTIAL].state)
		{
		case 0:
			eps_sts= eps_en_chnl(HW_PL_TRANSCELESTIAL,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_PL_TRANSCELESTIAL);
			break;

		case 1:
			sat_dev_sts[HW_PL_TRANSCELESTIAL].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_PL_TRANSCELESTIAL ,EPS_PWR_ON);
			log_id(LOG_INFO_L2,LOG_EPS,TRANSCELESTIAL_HW_STS_PWR_ON);
			break;
		}
	}
	else if((sat_dev_sts[HW_PL_TRANSCELESTIAL].hw_sts == PWR_SD) || (sat_dev_sts[HW_PL_TRANSCELESTIAL].hw_sts == PWR_RSTRT))
	{
		switch(eps_dev_crnt_tmr[HW_PL_TRANSCELESTIAL].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_PL_TRANSCELESTIAL,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_PL_TRANSCELESTIAL);
			break;

		case 1:
			eps_sts= eps_en_chnl(HW_PL_TRANSCELESTIAL,OFF);
			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_PL_TRANSCELESTIAL].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_PL_TRANSCELESTIAL].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_PL_TRANSCELESTIAL,PWR_ON);
				}
				else
					sat_dev_sts[HW_PL_TRANSCELESTIAL].hw_sts = PWR_OFF;
				log_id(LOG_INFO_L2,LOG_EPS,TRANSCELESTIAL_HW_STS_PWR_OFF);
			}
			break;
		}
	}

	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN
#ifdef JANUS1
		log_id_with_one_arg(LOG_ERROR,LOG_EPS,PL_ZE5_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_PL_ZES].state);
#endif

		log_id_with_one_arg(LOG_ERROR,LOG_EPS,PL_TRANS_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_PL_TRANSCELESTIAL].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_PL_TRANSCELESTIAL].hw_sts = PWR_ERR;
	}
}

#ifdef JANUS1
/**
 * @brief This API controls ZES power on/off sequence
 *
 */

void eps_pl_ze5_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_PL_ZES].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_PL_ZES].state)
		{
		case 0:
			eps_sts= eps_en_chnl(HW_PL_ZES,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_PL_ZES);

			break;

		case 1:
			sat_dev_sts[HW_PL_ZES].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_PL_ZES ,EPS_PWR_ON);
			break;
		}
	}
	else if((sat_dev_sts[HW_PL_ZES].hw_sts == PWR_SD) || (sat_dev_sts[HW_PL_ZES].hw_sts == PWR_RSTRT))
	{
		switch(eps_dev_crnt_tmr[HW_PL_ZES].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_PL_ZES,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_PL_ZES);
			break;

		case 1:
			eps_sts= eps_en_chnl(HW_PL_ZES,OFF);
			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_PL_ZES].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_PL_ZES].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_PL_ZES,PWR_ON);
				}
				else
					sat_dev_sts[HW_PL_ZES].hw_sts = PWR_OFF;
			}
			break;
		}
	}

	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN
		DEBUG_CPRINT(("PL_ZE5_PWR ERR=%d\n",eps_dev_crnt_tmr[HW_PL_ZES].state));
		log_id_with_one_arg(LOG_ERROR,LOG_EPS,PL_ZE5_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_PL_ZES].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_PL_ZES].hw_sts = PWR_ERR;
	}
}

#else
/**
 * @brief This API controls st300 power on/off sequence
 *
 */
void eps_pl_st300_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_PL_STS300].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_PL_STS300].state)
		{
		case 0:
			eps_sts= eps_en_chnl(HW_PL_STS300,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_PL_STS300);
			break;

		case 1:
			sat_dev_sts[HW_PL_STS300].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_PL_STS300 ,EPS_PWR_ON);
			log_id(LOG_INFO_L2,LOG_EPS,PL_STS300_HW_STS_PWR_ON);
			break;
		}
	}
	else if((sat_dev_sts[HW_PL_STS300].hw_sts == PWR_SD) || (sat_dev_sts[HW_PL_STS300].hw_sts == PWR_RSTRT))
	{
		switch(eps_dev_crnt_tmr[HW_PL_STS300].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_PL_STS300,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_PL_STS300);
			break;

		case 1:
			eps_sts= eps_en_chnl(HW_PL_STS300,OFF);
			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_PL_STS300].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_PL_STS300].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_PL_STS300,PWR_ON);
				}
				else
					sat_dev_sts[HW_PL_STS300].hw_sts = PWR_OFF;
				log_id(LOG_INFO_L2,LOG_EPS,PL_STS300_HW_STS_PWR_OFF);
			}
			break;
		}
	}

	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN

		log_id_with_one_arg(LOG_ERROR,LOG_EPS,PL_STS300_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_PL_STS300].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_PL_STS300].hw_sts = PWR_ERR;
	}
}


/**
 * @brief This API controls scanway power on/off sequence
 *
 */
void eps_pl_scanway_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_PL_SCANWAY].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_PL_SCANWAY].state)
		{
		case 0:
			eps_sts= eps_en_chnl(HW_PL_SCANWAY,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_PL_SCANWAY);
			break;

		case 1:
			sat_dev_sts[HW_PL_SCANWAY].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_PL_SCANWAY ,EPS_PWR_ON);
			log_id(LOG_INFO_L2,LOG_EPS,PL_SCANWAY_HW_STS_PWR_ON);
			break;
		}
	}
	else if((sat_dev_sts[HW_PL_SCANWAY].hw_sts == PWR_SD) || (sat_dev_sts[HW_PL_SCANWAY].hw_sts == PWR_RSTRT))
	{
		switch(eps_dev_crnt_tmr[HW_PL_SCANWAY].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_PL_SCANWAY,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_PL_SCANWAY);
			break;

		case 1:
			eps_sts= eps_en_chnl(HW_PL_SCANWAY,OFF);
			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_PL_SCANWAY].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_PL_SCANWAY].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_PL_SCANWAY,PWR_ON);
				}
				else
					sat_dev_sts[HW_PL_SCANWAY].hw_sts = PWR_OFF;
				log_id(LOG_INFO_L2,LOG_EPS,PL_SCANWAY_HW_STS_PWR_OFF);
			}
			break;
		}
	}

	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN

		log_id_with_one_arg(LOG_ERROR,LOG_EPS,PL_SCANWAY_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_PL_SCANWAY].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_PL_SCANWAY].hw_sts = PWR_ERR;
	}
}

/**
 * @brief This API controls uhf power on/off sequence
 *
 */
void eps_pl_uhf_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_UHF].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_UHF].state)
		{
		case 0:
			eps_sts= eps_en_chnl(HW_UHF,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_UHF);
			break;

		case 1:
			sat_dev_sts[HW_UHF].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_UHF ,EPS_PWR_ON);
			log_id(LOG_INFO_L2,LOG_EPS,PL_UHF_HW_STS_PWR_ON);
			break;
		}
	}
	else if((sat_dev_sts[HW_UHF].hw_sts == PWR_SD) || (sat_dev_sts[HW_UHF].hw_sts == PWR_RSTRT))
	{
		switch(eps_dev_crnt_tmr[HW_UHF].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_UHF,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_UHF);
			break;

		case 1:
			eps_sts= eps_en_chnl(HW_UHF,OFF);
			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_UHF].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_UHF].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_UHF,PWR_ON);
				}
				else
					sat_dev_sts[HW_UHF].hw_sts = PWR_OFF;
				log_id(LOG_INFO_L2,LOG_EPS,PL_UHF_HW_STS_PWR_OFF);
			}
			break;
		}
	}

	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN

		log_id_with_one_arg(LOG_ERROR,LOG_EPS,PL_UHF_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_UHF].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_UHF].hw_sts = PWR_ERR;
	}
}

#endif


/**
 * @brief This API controls adcs power on/off sequence
 *
 */
void eps_adcs_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_ADCS].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_ADCS].state)
		{
		case 0:
#ifdef JANUS1
			eps_sts= eps_en_chnl(HW_ADCS0,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_ADCS);
			break;
#else
			eps_dev_crnt_tmr[HW_ADCS].state++;
#endif
		case 1:
			eps_sts= eps_en_chnl(HW_ADCS,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_ADCS);
			break;

		case 2:
			sat_dev_sts[HW_ADCS].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_ADCS ,EPS_PWR_ON);
			log_id(LOG_INFO_L2,LOG_EPS,ADCS_HW_STS_PWR_ON);
			break;
		}
	}
	else if((sat_dev_sts[HW_ADCS].hw_sts == PWR_SD) || (sat_dev_sts[HW_ADCS].hw_sts == PWR_RSTRT))
	{
		switch(eps_dev_crnt_tmr[HW_ADCS].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_ADCS,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_ADCS);
			break;

		case 1:
#ifdef JANUS1
			eps_obc_ch_state_ind(HW_ADCS,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_ADCS);
			break;

		case 2:
#endif
			eps_sts= eps_en_chnl(HW_ADCS,OFF);
			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_ADCS].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_ADCS].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_ADCS,PWR_ON);
				}
				else
					sat_dev_sts[HW_ADCS].hw_sts = PWR_OFF;
				log_id(LOG_INFO_L2,LOG_EPS,ADCS_HW_STS_PWR_OFF);
			}

			break;
		}
	}

	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN
		DEBUG_CPRINT(("PL_TRANS_PWR ERR=%d\n",eps_dev_crnt_tmr[HW_ADCS].state));
		log_id_with_one_arg(LOG_ERROR,LOG_EPS,PL_ADCS_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_ADCS].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_ADCS].hw_sts = PWR_ERR;
	}
}

/**
 * @brief This API controls thruster power on/off sequence
 *
 */
void eps_prop_thrstr_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_PROP_UNIT_THRUSTER].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_PROP_UNIT_THRUSTER].state)
		{
		case 0:
			eps_sts= eps_en_chnl(HW_PROP_UNIT_THRUSTER,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_PROP_UNIT_THRUSTER);
			break;

		case 1:
			sat_dev_sts[HW_PROP_UNIT_THRUSTER].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_PROP_UNIT_THRUSTER ,EPS_PWR_ON);
			log_id(LOG_INFO_L2,LOG_EPS,THRUSTER_HW_STS_PWR_ON);
			break;
		}
	}
	else if((sat_dev_sts[HW_PROP_UNIT_THRUSTER].hw_sts == PWR_SD) || (sat_dev_sts[HW_PROP_UNIT_THRUSTER].hw_sts == PWR_RSTRT))
	{
		switch(eps_dev_crnt_tmr[HW_PROP_UNIT_THRUSTER].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_PROP_UNIT_THRUSTER,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_PROP_UNIT_THRUSTER);
			break;

		case 1:
			eps_sts= eps_en_chnl(HW_PROP_UNIT_THRUSTER,OFF);
			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_PROP_UNIT_THRUSTER].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_PROP_UNIT_THRUSTER].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_PROP_UNIT_THRUSTER,PWR_ON);
				}
				else
					sat_dev_sts[HW_PROP_UNIT_THRUSTER].hw_sts = PWR_OFF;
				log_id(LOG_INFO_L2,LOG_EPS,THRUSTER_HW_STS_PWR_OFF);
			}
			break;
		}
	}
	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN
		DEBUG_CPRINT(("PL_TRANS_PWR ERR=%d\n",eps_dev_crnt_tmr[HW_PROP_UNIT_THRUSTER].state));
		log_id_with_one_arg(LOG_ERROR,LOG_EPS,PL_PROP_UNIT_THRUSTER_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_PROP_UNIT_THRUSTER].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_PROP_UNIT_THRUSTER].hw_sts = PWR_ERR;
	}
}

/**
 * @brief This API controls xband power on/off sequence
 *
 */
void eps_sband_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_S_BAND].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_S_BAND].state)
		{
		case 0:
			eps_sts= eps_en_chnl(HW_S_BAND,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_S_BAND);
			break;

		case 1:
			sat_dev_sts[HW_S_BAND].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_S_BAND ,EPS_PWR_ON);
			log_id(LOG_INFO_L2,LOG_EPS,S_BAND_HW_STS_PWR_ON);

			break;
		}
	}
	else if((sat_dev_sts[HW_S_BAND].hw_sts == PWR_SD) || (sat_dev_sts[HW_S_BAND].hw_sts == PWR_RSTRT))
	{
		switch(eps_dev_crnt_tmr[HW_S_BAND].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_S_BAND,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_S_BAND);
			break;

		case 1:
			eps_sts= eps_en_chnl(HW_S_BAND,OFF);
			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_S_BAND].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_S_BAND].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_S_BAND,PWR_ON);
				}
				else
					sat_dev_sts[HW_S_BAND].hw_sts = PWR_OFF;
				log_id(LOG_INFO_L2,LOG_EPS,S_BAND_HW_STS_PWR_OFF);
			}

			break;
		}
	}

	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN
		DEBUG_CPRINT(("SBAND_PWR ERR=%d\n",eps_dev_crnt_tmr[HW_S_BAND].state));
		log_id_with_one_arg(LOG_ERROR,LOG_EPS,S_BAND_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_S_BAND].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_S_BAND].hw_sts = PWR_ERR;
	}
}

/**
 * @brief This API controls sband power on/off sequence
 *
 */
void eps_xband_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_X_BAND].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_X_BAND].state)
		{
		case 0:
			eps_sts= eps_en_chnl(HW_X_BAND,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_X_BAND);
			break;
#if 0
		case 1:
			eps_sts = eps_set_chnl_state_xband(1,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_X_BAND);
			break;
#endif
		case 1:
			sat_dev_sts[HW_X_BAND].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_X_BAND ,EPS_PWR_ON);
			log_id(LOG_INFO_L2,LOG_EPS,X_BAND_HW_STS_PWR_ON);
			break;
		}
	}
	else if((sat_dev_sts[HW_X_BAND].hw_sts == PWR_SD) || (sat_dev_sts[HW_X_BAND].hw_sts == PWR_RSTRT))
	{
		switch(eps_dev_crnt_tmr[HW_X_BAND].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_X_BAND ,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_X_BAND);
			break;
#if 0
		case 1:
			eps_sts=eps_set_chnl_state_xband(1,OFF);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_X_BAND);
			break;
#endif
		case 1:
			eps_sts= eps_en_chnl(HW_X_BAND,OFF);
			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_X_BAND].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_X_BAND].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_X_BAND,PWR_ON);
				}
				else
					sat_dev_sts[HW_X_BAND].hw_sts = PWR_OFF;
				log_id(LOG_INFO_L2,LOG_EPS,X_BAND_HW_STS_PWR_OFF);
			}

			break;
		}
	}

	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN
		DEBUG_CPRINT(("X_BAND_PWR ERR=%d\n",eps_dev_crnt_tmr[HW_S_BAND].state));
		log_id_with_one_arg(LOG_ERROR,LOG_EPS,XBAND_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_X_BAND].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_X_BAND].hw_sts = PWR_ERR;
	}
}

/**
 * @brief This API controls edge power on/off sequence
 *
 */
void eps_edge_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_EDGE_BRD].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_EDGE_BRD].state)
		{
		case 0:
			eps_sts = eps_set_chnl_state_edge(0,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_EDGE_BRD);

			break;

		case 1:
			eps_sts = eps_set_chnl_state_edge(1,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_EDGE_BRD);
			break;

		case 2:
			eps_sts = eps_set_chnl_state_edge(2,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_EDGE_BRD);
			break;

		case 3:
			eps_sts = eps_set_chnl_state_edge(3,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_EDGE_BRD);
			break;

		case 4:
			sat_dev_sts[HW_EDGE_BRD].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_EDGE_BRD ,EPS_PWR_ON);
			log_id(LOG_INFO_L2,LOG_EPS,EDGE_BRD_HW_STS_PWR_ON);

			break;
		}
	}
	else if((sat_dev_sts[HW_EDGE_BRD].hw_sts == PWR_SD) || (sat_dev_sts[HW_EDGE_BRD].hw_sts == PWR_RSTRT))
	{
		switch(eps_dev_crnt_tmr[HW_EDGE_BRD].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_EDGE_BRD ,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_EDGE_BRD);
			break;

		case 1:
			eps_sts=eps_set_chnl_state_edge(3,OFF);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_EDGE_BRD);
			break;

		case 2:
			eps_sts=eps_set_chnl_state_edge(2,OFF);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_EDGE_BRD);
			break;

		case 3:
			eps_sts=eps_set_chnl_state_edge(1,OFF);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_EDGE_BRD);
			break;

		case 4:
			eps_sts=eps_set_chnl_state_edge(0,OFF);
			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_EDGE_BRD].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_EDGE_BRD].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_EDGE_BRD,PWR_ON);
				}
				else
					sat_dev_sts[HW_EDGE_BRD].hw_sts = PWR_OFF;
				log_id(LOG_INFO_L2,LOG_EPS,EDGE_BRD_HW_STS_PWR_OFF);
			}
			break;
		}
	}
	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN
		DEBUG_CPRINT(("EDGE_PWR ERR=%d\n",eps_dev_crnt_tmr[HW_EDGE_BRD].state));
		log_id_with_one_arg(LOG_ERROR,LOG_EPS,EDGE_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_EDGE_BRD].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_EDGE_BRD].hw_sts = PWR_ERR;
	}
}

/**
 * @brief This API controls obc power on/off sequence
 *
 */
void eps_obc_ps_gps_pwr_seq()
{
	eps_err_sts eps_sts = EPS_ERR;
#ifdef DRISHTI_EN
        if(sat_dev_sts[HW_OBC_PS_GPS_STD_PL_BRD].hw_sts == PWR_BOOT)
        {
                switch(eps_dev_crnt_tmr[HW_OBC_PS_GPS_STD_PL_BRD].state)
                {
                case 0:
                        eps_sts= eps_en_chnl(HW_OBC_PS_GPS_STD_PL_BRD,ON);
                        if(eps_sts == EPS_SUCCESS)
                                eps_pwr_tmr_cntr_updt(HW_OBC_PS_GPS_STD_PL_BRD);
                        break;
                case 1:
                        sat_dev_sts[HW_OBC_PS_GPS_STD_PL_BRD].hw_sts = PWR_ON;
                        eps_obc_ch_state_ind(HW_OBC_PS_GPS_STD_PL_BRD ,EPS_PWR_ON);
                        break;
                }
        }
#endif


	if(sat_dev_sts[HW_OBC_PS_GPS_STD_PL_BRD].hw_sts == PWR_SD || sat_dev_sts[HW_OBC_PS_GPS_STD_PL_BRD].hw_sts == PWR_RSTRT)
	{
		switch(eps_dev_crnt_tmr[HW_OBC_PS_GPS_STD_PL_BRD].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_OBC_PS_GPS_STD_PL_BRD ,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_OBC_PS_GPS_STD_PL_BRD);
			break;

		case 1:
			if(eps_en_chnl(HW_OBC_PS_GPS_STD_PL_BRD,OFF) != EPS_SUCCESS)
			{
#ifdef EPS_DBG_EN
				//DEBUG_CPRINT(("OBC_PWR_OFF_ERR\n"));
				log_id(LOG_ERROR,LOG_EPS,OBC_PWR_OFF_ERR);
				eps_sts_err_print(eps_sts);
#endif
				sat_dev_sts[HW_OBC_PS_GPS_STD_PL_BRD].hw_sts = PWR_ERR;
                        }
#ifdef DRISHTI_EN
                        else
                        {
                            if(sat_dev_sts[HW_OBC_PS_GPS_STD_PL_BRD].hw_sts == PWR_RSTRT)
                            {
                                sat_dev_sts[HW_OBC_PS_GPS_STD_PL_BRD].hw_sts = PWR_OFF;
                                eps_ctrl_en_chnl(HW_OBC_PS_GPS_STD_PL_BRD,PWR_ON);
                            }
                            else
                            {
                                sat_dev_sts[HW_OBC_PS_GPS_STD_PL_BRD].hw_sts = PWR_OFF;
                            }
                        }
#endif
                        break;
                }
        }
}

/**
 * @brief This API controls payload server power on/off sequence
 *
 */
void eps_ps_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_PL_SERVER].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_PL_SERVER].state)
		{
		case 0:
			eps_sts = eps_set_chnl_state_pl_srvr(0,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_PL_SERVER);
			break;

		case 1:
			eps_sts = eps_set_chnl_state_pl_srvr(1,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_PL_SERVER);
			break;

		case 2:
			eps_sts = eps_set_chnl_state_pl_srvr(2,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_PL_SERVER);
			break;

		case 3:
			sat_dev_sts[HW_PL_SERVER].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_PL_SERVER ,EPS_PWR_ON);
			log_id(LOG_INFO_L2,LOG_EPS,PS_BRD_HW_STS_PWR_ON);

			break;
		}
	}
	else if((sat_dev_sts[HW_PL_SERVER].hw_sts == PWR_SD) || (sat_dev_sts[HW_PL_SERVER].hw_sts == PWR_RSTRT))
	{

		switch(eps_dev_crnt_tmr[HW_PL_SERVER].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_PL_SERVER ,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_PL_SERVER);
			break;

		case 1:
			eps_sts = eps_set_chnl_state_pl_srvr(2,OFF);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_PL_SERVER);
			break;

		case 2:
			eps_sts = eps_set_chnl_state_pl_srvr(1,OFF);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_PL_SERVER);
			break;

		case 3:
			eps_sts = eps_set_chnl_state_pl_srvr(0,OFF);

			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_PL_SERVER].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_PL_SERVER].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_PL_SERVER,PWR_ON);
				}
				else
					sat_dev_sts[HW_PL_SERVER].hw_sts = PWR_OFF;
				log_id(LOG_INFO_L2,LOG_EPS,PS_BRD_HW_STS_PWR_OFF);
			}
			break;
		}
	}

	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN
		DEBUG_CPRINT(("PL_SRVR_PWR ERR=%d\n",eps_dev_crnt_tmr[HW_PL_SERVER].state));
		log_id_with_one_arg(LOG_ERROR,LOG_EPS,PL_SRVR_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_PL_SERVER].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_PL_SERVER].hw_sts = PWR_ERR;
	}
}

/**
 * @brief This API controls hrm power on/off sequence
 *
 */
void eps_hrm_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;
	uint8_t eps_hrm_rls_sts = 0;

	eps_get_out_chnl_sts_s out_chnl_rd;
	switch(eps_dev_crnt_tmr[HW_HRM].state)
	{
	case 0:   //checking release status
		hrm_err_cntr=0;
		eps_pwr_tmr_cntr_updt(HW_HRM);
		break;

	case 1:   //checking release status
		eps_get_chnl_params(&out_chnl_rd);
#if 0
		eps_hrm_rls_sts 	  			= out_chnl_rd.hrm_rls_sts;
#else
		eps_hrm_rls_sts 	  			= out_chnl_rd.hrm_rls_left << 0x01 | out_chnl_rd.hrm_rls_right;
#endif
		eps_hlth_info.dev_hw_sts	   |= (uint16_t)eps_hrm_rls_sts << MAX_SAT_DEV_CNT;
		if(eps_sts == EPS_SUCCESS)
		{
			if(eps_hrm_rls_sts == 0)
			{
				if(hrm_err_cntr++ >= pwr_tmr[HW_HRM].off_tmr.max_st_cnt)
					sat_dev_sts[HW_HRM].hw_sts = PWR_ERR;
				else
				{
					eps_sts= eps_en_chnl(HW_HRM,OFF);
					if(eps_sts == EPS_SUCCESS)
						eps_pwr_tmr_cntr_updt(HW_HRM);
				}
			}
			else
				sat_dev_sts[HW_HRM].hw_sts = PWR_ON;
		}
#ifdef EPS_DBG_EN
		else
		{
			eps_sts_err_print(eps_sts);
		}
#endif
		break;

	case 2:
		eps_sts= eps_en_chnl(HW_HRM,ON);
		if(eps_sts == EPS_SUCCESS)
		{
			eps_dev_crnt_tmr[HW_HRM].state = 0;
			eps_pwr_tmr_cntr_updt(HW_HRM);

		}
#ifdef EPS_DBG_EN
		else
		{
			DEBUG_CPRINT(("HRM CH EN ERR\n"));
			log_id(LOG_ERROR,LOG_EPS,HRM_CH_EN_ERR);
			eps_sts_err_print(eps_sts);
		}
#endif
		break;
	}
}

/**
 * @brief This API controls gps power on/off sequence
 *
 */
void eps_gps_pwr_seq()
{
	eps_err_sts eps_sts = EPS_SUCCESS;

	if(sat_dev_sts[HW_GPS].hw_sts == PWR_BOOT)
	{
		switch(eps_dev_crnt_tmr[HW_GPS].state)
		{
		case 0:
			eps_sts = eps_set_chnl_state_gps(0,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_GPS);
			break;

		case 1:
			eps_sts = eps_set_chnl_state_gps(1,ON);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_GPS);
			break;

		case 2:
			sat_dev_sts[HW_GPS].hw_sts = PWR_ON;
			eps_obc_ch_state_ind(HW_GPS ,EPS_PWR_ON);

			log_id(LOG_INFO_L2,LOG_EPS,GPS_BRD_HW_STS_PWR_ON);
			break;
		}
	}
	else if((sat_dev_sts[HW_GPS].hw_sts == PWR_SD) || (sat_dev_sts[HW_GPS].hw_sts == PWR_RSTRT))
	{
		switch(eps_dev_crnt_tmr[HW_GPS].state)
		{
		case 0:
			eps_obc_ch_state_ind(HW_GPS ,EPS_PWR_OFF);
			eps_pwr_tmr_cntr_updt(HW_GPS);
			break;

		case 1:
			eps_sts = eps_set_chnl_state_gps(1,OFF);
			if(eps_sts == EPS_SUCCESS)
				eps_pwr_tmr_cntr_updt(HW_GPS);
			break;

		case 2:
			eps_sts=eps_set_chnl_state_gps(0,OFF);
			if(eps_sts == EPS_SUCCESS)
			{
				if(sat_dev_sts[HW_GPS].hw_sts == PWR_RSTRT)
				{
					sat_dev_sts[HW_GPS].hw_sts = PWR_OFF;
					eps_ctrl_en_chnl(HW_GPS,PWR_ON);
				}
				else
					sat_dev_sts[HW_GPS].hw_sts = PWR_OFF;

				log_id(LOG_INFO_L2,LOG_EPS,GPS_BRD_HW_STS_PWR_OFF);
			}

			break;
		}
	}

	if(eps_sts != EPS_SUCCESS)
	{
#ifdef EPS_DBG_EN
		DEBUG_CPRINT(("GPS_PWR ERR=%d\n",eps_dev_crnt_tmr[HW_GPS].state));
		log_id_with_one_arg(LOG_ERROR,LOG_EPS,GPS_PWR_ERR__u8_,eps_dev_crnt_tmr[HW_GPS].state);
		eps_sts_err_print(eps_sts);
#endif
		sat_dev_sts[HW_GPS].hw_sts = PWR_ERR;
	}
}

/**
 * @brief This API controls payload power on/off sequence
 *
 */
void eps_pwr_seq_st(eps_ch_s ch_no)
{
	switch(ch_no)
	{
	case HW_PL_TRANSCELESTIAL:	   eps_pl_trans_pwr_seq();		break;
	case HW_X_BAND:                eps_xband_pwr_seq();			break;
	case HW_S_BAND:                eps_sband_pwr_seq();			break;
#ifdef JANUS1
	case HW_PL_ZES:                eps_pl_ze5_pwr_seq();		break;
	case HW_PL_SAYARLABS:          eps_pl_syrlbs_pwr_seq();		break;
#else
	case HW_PL_STS300:  		   eps_pl_st300_pwr_seq();		 break;
	case HW_PL_SCANWAY:  		   eps_pl_scanway_pwr_seq();		 break;
	case HW_UHF:				   eps_pl_uhf_pwr_seq();		 break;
#endif
	case HW_ADCS:                  eps_adcs_pwr_seq();			break;
	case HW_PROP_UNIT_THRUSTER:    eps_prop_thrstr_pwr_seq();	break;
	case HW_PL_NETRA:              eps_pl_netra_pwr_seq();		break;
	case HW_EDGE_BRD:              eps_edge_pwr_seq();			break;
	case HW_OBC_PS_GPS_STD_PL_BRD: eps_obc_ps_gps_pwr_seq();	break;
	case HW_PL_SERVER:             eps_ps_pwr_seq();			break;
	case HW_GPS:				   eps_gps_pwr_seq();			break;
	case HW_HRM:
	{
		if(EPS_HRM_ON_DEFLT)
		{
			eps_hrm_pwr_seq();
		}
	}
	break;
	default:
		break;
	}
}

/*
 * @brief EPS communication failure callback function
 */
void eps_com_fail_cb()
{
	eps_com_fail_cnt--;
	eps_err_sts_e eps_err_sts;
	eps_get_out_chnl_sts_s get_chnl_state;
	if(eps_com_fail_cnt==0)
	{
		eps_fw_boot_dis_mcu2();
		eps_com_fail_cnt=EPS_MAX_TM_MIN;
	}

	eps_err_sts = eps_get_chnl_params(&get_chnl_state);
	if(eps_err_sts != EPS_COM_FAIL)
	{
		eps_com_fail_flg=0;
		eps_chnl_on_off_trig_after_com_scs(&get_chnl_state);
	}
	else
	{
		// No Action
	}
}

/*
 * @brief This function trigger the channel power ON
 * after communication moves to stable status
 */
void eps_chnl_on_off_trig_after_com_scs(eps_get_out_chnl_sts_s *get_chnl_state)
{
	eps_ctrl_verify_chnl_state_nvm(get_chnl_state,channel_status);

	if(EPS_HRM_ON_DEFLT)
	{
		log_id(LOG_INFO_L1,LOG_EPS,HRM_WAS_TURNING_ON);
		os_delay(10);
		eps_ctrl_en_chnl(HW_HRM,EPS_PWR_ON);
		os_delay(10);
	}

	eps_ctrl_send_ipc_msg_pld(EPS_TASK, EPS_BTRY_MODE_CHNL_STATE,0,NULL,0);
	eps_pwr_up_chnl_after_fw_upd();
}

/**
 * @brief  This API initialize the output channel default parameters and power timer required.
 * 		  This is executed once during start of the program.
 *
 */
void eps_ctrl_dev_init()
{
#if EPS_CH_ON_AFTR_RSTRT
	uint8_t chnl_cnt = 0,chnl_st;
#endif
	eps_ctrl_dev_defaults();
#ifndef DRISHTI_EN
	sat_dev_sts[HW_OBC_PS_GPS_STD_PL_BRD].hw_sts = PWR_ON;
#endif
	eps_get_out_chnl_sts_s get_chnl_state;
	os_timer_create(&eps_pwr_tmr,"eps_pwr_tmr",PERIODIC,eps_pwr_tmr_cb,NULL);
	eps_err_sts_e eps_err_sts;
	eps_err_sts = eps_get_chnl_params(&get_chnl_state);
	if(eps_err_sts == EPS_COM_FAIL)
	{
		eps_com_fail_flg = 1;
	}
	else
	{
		eps_chnl_on_off_trig_after_com_scs(&get_chnl_state);
	}

#if EPS_CH_ON_AFTR_RSTRT
	if(sat_btry_info.status > HW_BTRY_SAFE)
	{
		for(chnl_cnt=0;chnl_cnt<HW_GPS;chnl_cnt++)
		{
			nvm_parameter_read(NVM_DATA,(NVM_HW_PL_TRANSCELESTIAL+chnl_cnt),(uint8_t*)&chnl_st);
			if(chnl_st==EPS_PWR_ON)
				eps_ctrl_en_chnl(chnl_cnt,EPS_PWR_ON);
		}
	}
#endif
}
