/*
 * @file exo_io_al_stm32f7xx_i2c.h
 *
 * @brief This file contains structures,enumerations
 * and function declaration for I2C interface
 *
 * @copyright Copyright 2023 Antaris, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#ifndef IO_AL_STM32F7xx_I2C_H
#define IO_AL_STM32F7xx_I2C_H


#include "exo_types.h"
#include "exo_io_al_fmc_nor_flash_common.h"
#include "exo_io_al_common.h"

hal_ret_sts io_hal_stm32f7xx_fmc_nor_init(ioal_fmc_nor_hdle* ioal_nor);
hal_ret_sts io_hal_stm32f7xx_fmc_nor_program_buffer(ioal_fmc_nor_hdle *ioal_nor, uint32 address, uint8 *data, uint32 buff_size);
hal_ret_sts io_hal_stm32f7xx_fmc_nor_program(ioal_fmc_nor_hdle *ioal_nor, uint32 address, uint16* data);
hal_ret_sts io_hal_stm32f7xx_fmc_nor_read(ioal_fmc_nor_hdle *ioal_nor, uint32* address, uint16* data);
hal_ret_sts io_hal_stm32f7xx_fmc_nor_read_buffer(ioal_fmc_nor_hdle *ioal_nor, uint32 address, uint8 *data, uint32 buff_size);
hal_ret_sts io_hal_stm32f7xx_fmc_nor_erase_block(ioal_fmc_nor_hdle *ioal_nor, uint32 block_addr);
hal_ret_sts io_hal_stm32f7xx_fmc_nor_erase_chip(ioal_fmc_nor_hdle *ioal_nor);
ioal_nor_state_t io_hal_stm32f7xx_fmc_nor_get_state(ioal_fmc_nor_hdle *ioal_nor);
ioal_nor_status_t io_hal_stm32f7xx_fmc_nor_get_status(ioal_fmc_nor_hdle *ioal_nor,uint32 address, uint32 timeout);
hal_ret_sts io_hal_stm32f7xx_fmc_nor_write_enable(ioal_fmc_nor_hdle *ioal_nor);
hal_ret_sts io_hal_stm32f7xx_fmc_nor_write_disable(ioal_fmc_nor_hdle *ioal_nor);
hal_ret_sts io_hal_stm32f7xx_fmc_nor_return_to_read_mode(ioal_fmc_nor_hdle *ioal_nor);
hal_ret_sts io_hal_stm32f7xx_fmc_nor_read_id(ioal_fmc_nor_hdle *ioal_nor, ioal_nor_id_t *id);
hal_ret_sts io_hal_stm32f7xx_fmc_nor_read_cfi(ioal_fmc_nor_hdle *ioal_nor, ioal_nor_cfi_t* cfi);


#define io_hal_common_fmc_nor_init io_hal_stm32f7xx_fmc_nor_init
#define io_hal_common_fmc_nor_program_buffer io_hal_stm32f7xx_fmc_nor_program_buffer
#define io_hal_common_fmc_nor_program io_hal_stm32f7xx_fmc_nor_program
#define io_hal_common_fmc_nor_read io_hal_stm32f7xx_fmc_nor_read
#define io_hal_common_fmc_nor_read_buffer io_hal_stm32f7xx_fmc_nor_read_buffer
#define io_hal_common_fmc_nor_erase_block io_hal_stm32f7xx_fmc_nor_erase_block
#define io_hal_common_fmc_nor_erase_chip io_hal_stm32f7xx_fmc_nor_erase_chip
#define io_hal_common_fmc_nor_get_state io_hal_stm32f7xx_fmc_nor_get_state
#define io_hal_common_fmc_nor_get_status io_hal_stm32f7xx_fmc_nor_get_status
#define io_hal_common_fmc_nor_write_enable io_hal_stm32f7xx_fmc_nor_write_enable
#define io_hal_common_fmc_nor_write_disable io_hal_stm32f7xx_fmc_nor_write_disable
#define io_hal_common_fmc_nor_return_to_read_mode io_hal_stm32f7xx_fmc_nor_return_to_read_mode
#define io_hal_common_fmc_nor_read_id io_hal_stm32f7xx_fmc_nor_read_id
#define io_hal_common_fmc_nor_read_cfi io_hal_stm32f7xx_fmc_nor_read_cfi

#endif
