/**
 * @file nvm.c
 *
 * @brief This file contains functions definitions for the NVM framework
 *
 * @copyright Copyright 2023 Antaris, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include "exo_types.h"
#include "system_init_exit.h"
#include "exo_common.h"
#include "exo_osal.h"
#include "exo_io_al_sos_timer.h"
#include "exo_hal_io_al_common.h"
#include "exo_osal_mem_cpy.h"
#include "nvm.h"
#include "comms_csw.h"
#include "crc_cal.h"
#include "exo_types.h"
#include "err_handler.h"
#include "version.h"
#include "logger.h"
static uint32_t nvm_length=0;
static uint8_t nvm_version;
static uint8_t nvm_dirty_flag;
volatile uint8_t disable_commit;

extern volatile uint8_t system_error;
extern volatile uint8_t nvm_force_commit_flag;

volatile uint8_t sys_assert_sts=0;

static os_sem_handle_ptr commit_sem;
static os_sem_handle_ptr nvm_write_sem;
static os_timer_handle_ptr nvm_commit_timer;
static e_nvm_drv_state nvm_drv_state = NVM_DRV_INVALID;

static uint16_t nvm_parm_rd_only_idx_by_id[54]={0};
static uint32_t nvm_parm_idx_by_id[NVM_MAX_PARM+1] = {0};
static uint8_t PLACE_IN_EXT_RAM_MEM primary_nvm_buff[NVM_MAX_BUFF_SIZE] ={0xFF};
static uint8_t PLACE_IN_EXT_RAM_MEM temp_nvm_buff[NVM_MAX_BUFF_SIZE] ={0xFF};
//static uint32 PLACE_IN_FIXED_DATA nvm_preload = 0xFFFFFFFF;

/// Array to store read only NVM parameter length in bits
const uint16_t nvm_rd_only_data_len_by_id[54]= {

		[NVM_RD_MAGIC_NUM-NVM_MAX_PARM]=8,
};

#ifndef LINUX_TEMP_PORT

#ifdef COREBOARD
/* Use FMC flash address 0x60000000 for NVM in coreboard, size 256kb
 * Bank 1 start address = 0x60000000, 128kb
 * Bank 2 start address = 0x60020000, 128kb
 *  */
#define PLACE_IN_EXT_FLASH_NVM __attribute__((aligned(128*1024))) __attribute__ ((section (".ext_fmcflash_nvm")))
#else
/* Use QSPI flash address 0x90000000 for NVM in discovery, size 256kb
 * Bank 1 start address = 0x90000000, 128kb
 * Bank 2 start address = 0x90020000, 128kb
 *  */
#define PLACE_IN_EXT_FLASH_NVM __attribute__((aligned(4*1024))) __attribute__ ((section (".ext_qspiflash_nvm")))
#endif

/* Allocated external flash for NVM module 128 kb*/
static uint8_t PLACE_IN_EXT_FLASH_NVM ext_mem_flash_nvm_bank1[1024*128];
/* Allocated external flash for NVM module 128 kb*/
static uint8_t PLACE_IN_EXT_FLASH_NVM ext_mem_flash_nvm_bank2[1024*128];

#define NVM_FLASH_PARTITION_1_ADDR (uint32_t)ext_mem_flash_nvm_bank1
#define NVM_FLASH_PARTITION_2_ADDR (uint32_t)ext_mem_flash_nvm_bank2

#endif


#ifdef LINUX_TEMP_PORT
#define NVM_FLASH_PARTITION_1_ADDR (uint32_t) 0
#define NVM_FLASH_PARTITION_2_ADDR (uint32_t) 0
#endif



/// Array to store read/write NVM parameter length in bits
static uint16_t nvm_data_parm_len_by_id[NVM_MAX_PARM] = {
		[NVM_MAGIC_NUM]=16,
		[NVM_REV_NUM]=16,
		[NVM_VERSION]=8,
		[NVM_ZONE_FLAG]=8,
		[CONOPS_SCH_EVNT_PENDING_STS]=8,
		[CONOPS_SCH_CRNT_EVNT]=8,
		[CONOPS_SCH_LUT_INFO_0]=160,
		[CONOPS_SCH_LUT_INFO_1]=160,
		[CONOPS_SCH_EVNT_BUFF_0]=49152,
		[CONOPS_SCH_EVNT_BUFF_1]=49152,
		[NVM_IPCC_SEC_CFG]=8,
		[NVM_TC_TM_SEC_CFG]=8,
		[NVM_OTSU_GSCONT_FAIL_TIMEOUT]=32,
		[NVM_OTSU_REBOOT_CONFIG]=192,
		[NVM_OTSU_CONFIG]=8,
		[NVM_OTSU_NW_FRMW_STS]=8,
		[NVM_OTSU_FTM_FILE_CONTXT_DATA]=128,
		[NVM_OTSU_FTM_CONTXT_DATA]=1600,
		[EPS_ELIGIBLE_CHNL]=16,
		[EPS_CHNL_OVR_CUR_ERR]=16,
		[EPS_BTRY_THRSHLD]=96,
		[EPS_PWR_TMR1]=336,
		[EPS_PWR_TMR2]=336,
		[EPS_PWR_TMR3]=336,
		[EPS_PWR_TMR4]=336,
		[EPS_PWR_TMR5]=336,
		[EPS_PWR_TMR6]=336,
		[EPS_PWR_TMR7]=336,
		[EPS_PWR_TMR8]=336,
		[EPS_PWR_TMR9]=336,
		[EPS_PWR_TMR10]=336,
		[EPS_PWR_TMR11]=336,
		[EPS_PWR_TMR12]=336,
		[EPS_PWR_TMR13]=336,
		[EPS_PWR_TMR14]=336,
		[EPS_BTRY_CH_MAP]=104,
		[EPS_COM_FAIL_TIMEOUT]=16,
		[NVM_TEMP_SENSOR_MCP9843_GPS_CFG]=160,
		[NVM_TEMP_SENSOR_MCP9843_PS_CFG]=160,
		[NVM_TEMP_SENSOR_MCP9843_EDGE_CFG]=160,
		[NVM_TEMP_SENSOR_MCP9843_OBC_CFG]=160,
		[NVM_DT_DS620_SPE01_CFG]=160,
		[NVM_DT_DS620_SPE02_CFG]=160,
		[NVM_DT_DS620_SPW01_CFG]=160,
		[NVM_DT_DS620_SPW02_CFG]=160,
		[NVM_DT_DS620_SPB01_CFG]=160,
		[NVM_DT_DS620_PS_CFG]=160,
		[NVM_DT_DS620_EDGE_CFG]=160,
		[NVM_POWER_SENSE_MONITOR_OBC_CFG]=192,
		[NVM_POWER_SENSE_MONITOR_PS_CFG]=192,
		[NVM_HSC_ADM1176_EDGE_CFG]=160,
		[NVM_HSC_ADM1176_PS_1_CFG]=160,
		[NVM_HSC_ADM1176_PS_2_CFG]=160,
		[NVM_SNS_CFG_STS]=8,
		[NVM_RST_RSN_IDX]=8,
		[NVM_RST_CNT]=16,
		[NVM_RST_RSN_BUFF]=1920,
		[NVM_SBAND_NAME]=160,
		[NVM_SBAND_BOOT_COUNT]=32,
		[NVM_SBAND_GWDT_INIT]=32,
		[NVM_SBAND_CSP_ADDRESS]=8,
		[NVM_SBAND_CSP_ROUTES]=800,
		[NVM_SBAND_CAN_RATE]=32,
		[NVM_SBAND_CAN_PROMISC]=8,
		[NVM_SBAND_UART_RATE]=32,
		[NVM_SBAND_UART_MULTIDROP]=8,
		[NVM_SBAND_IP_STACK_ENABLE]=8,
		[NVM_SBAND_ETH_IP_ADDRESS]=400,
		[NVM_SBAND_ETH_NET_PREFIX_BIT]=8,
		[NVM_SBAND_ETH_GATEWAY_IP_ADDRESS]=400,
		[NVM_SBAND_SPACELINK_IP_ADDRESS]=400,
		[NVM_SBAND_SPACELINK_NET_PREFIX_BIT]=8,
		[NVM_SBAND_SPACELINK_GATEWAY_IP_ADDRESS]=400,
		[NVM_SBAND_PWR_SNS_GAIN]=32,
		[NVM_SBAND_PWR_SNS_INTERCEPT]=32,
		[NVM_SBAND_VCTCXO]=16,
		[NVM_SBAND_TRANS_FREQ]=32,
		[NVM_SBAND_TRANS_MOD_TYP]=8,
		[NVM_SBAND_TRANS_SYMB_RATE]=32,
		[NVM_SBAND_TRANS_ROLL_OFF]=8,
		[NVM_SBAND_TRANS_PWR]=32,
		[NVM_SBAND_ALC_MODE]=8,
		[NVM_SBAND_TRANS_EN_REED_SOLOMON]=8,
		[NVM_SBAND_TRANS_EN_CONVOLUTIONAL]=8,
		[NVM_SBAND_TRANS_EN_RANDOMIZATION]=8,
		[NVM_SBAND_TRANS_EN_CRC_CHECKSUM]=8,
		[NVM_SBAND_IDLE_TIME]=16,
		[NVM_SBAND_PAYLOAD_SIZE]=16,
		[NVM_SBAND_SATEELITE_ID]=16,
		[NVM_SBAND_ENCRYPT_KEY]=256,
		[NVM_SBAND_ENCRYPT_FRAME]=8,
		[NVM_SBAND_TRANS_CRYPTO_AUTH]=8,
		[NVM_SBAND_PA_TEMP_LIMIT]=8,
		[NVM_SBAND_RECEIVE_FREQ]=32,
		[NVM_SBAND_MODULATION_TYP]=8,
		[NVM_SBAND_RECEIVE_SYMB_RATE]=32,
		[NVM_SBAND_RECEIVE_ROLL_OFF]=8,
		[NVM_SBAND_AFC_EN]=8,
		[NVM_SBAND_AFC_RANGE]=32,
		[NVM_SBAND_RECEIVE_EN_REED_SOLOMON]=8,
		[NVM_SBAND_RECEIVE_EN_CONVOLUTIONAL]=8,
		[NVM_SBAND_RECEIVE_EN_RANDOMIZATION]=8,
		[NVM_SBAND_RECEIVE_EN_CRC_CHECKSUM]=8,
		[NVM_SBAND_RECEIVE_PAYLOAD_SIZE]=16,
		[NVM_SBAND_RECEIVE_SATELLITE_ID]=16,
		[NVM_SBAND_DECRYPT_KEY]=256,
		[NVM_SBAND_DECRYPT_FRAME]=8,
		[NVM_SBAND_RECIEVE_CRYPTO_AUTH]=8,
        [NVM_UHF_TX_CHAN_NUM]=8,
        [NVM_UHF_TX_MOD_TYPE]=8,
        [NVM_UHF_TX_SYNC_MODE]=8,
        [NVM_UHF_TX_ENABLE_DC_FILTER]=8,
        [NVM_UHF_TX_FEC_ENB]=8,
        [NVM_UHF_TX_PREAM_NUM]=8,
        [NVM_UHF_TX_MANCHESTER_ENB]=8,
        [NVM_UHF_TX_RSVD]=8,
        [NVM_UHF_TX_BASE_FREQ]=32,
        [NVM_UHF_TX_IF_FREQ]=32,
        [NVM_UHF_TX_CHAN_SPACING]=32,
        [NVM_UHF_TX_FREQ_OFFSET]=32,
        [NVM_UHF_TX_DATA_RATE]=32,
        [NVM_UHF_TX_CHAN_BW]=32,
        [NVM_UHF_TX_FREQ_DEV]=32,
        [NVM_UHF_RX_CHAN_NUM]=8,
        [NVM_UHF_RX_MOD_TYPE]=8,
        [NVM_UHF_RX_SYNC_MOD]=8,
        [NVM_UHF_RX_ENB_DC_FILTER]=8,
        [NVM_UHF_RX_FEC_ENB]=8,
        [NVM_UHF_RX_PREM_NUM]=8,
        [NVM_UHF_RX_MANCHESTER_ENB]=8,
        [NVM_UHF_RX_ATTENUATION]=8,
        [NVM_UHF_RX_BASE_FREQ]=32,
        [NVM_UHF_RX_IF_FREQ]=32,
        [NVM_UHF_RX_CHAN_SPACING]=32,
        [NVM_UHF_RX_FREQ_OFFSET]=32,
        [NVM_UHF_RX_DATA_RATE]=32,
        [NVM_UHF_RX_CHAN_BW]=32,
        [NVM_UHF_RX_FREQ_DEV]=32,
        [NVM_UHF_RX_SYNC_TIME_OUT]=32,
        [NVM_UHF_PWR_MAX_DVGA_GAIN]=8,
        [NVM_UHF_PWR_MAX_LNA_GAIN]=8,
        [NVM_UHF_PWR_LNA_SEL]=8,
        [NVM_UHF_PWR_FILTER_LEN]=8,
        [NVM_UHF_PWR_PWR_TABLE_SEL]=8,
        [NVM_UHF_PWR_RF_OUTPUT_PWR]=8,
        [NVM_UHF_TX_PKT_DEMOD_SYNC_WORD]=16,
        [NVM_UHF_TX_PKT_MAX_PKT_LEN]=8,
        [NVM_UHF_TX_PKT_WHITE_ENB]=8,
        [NVM_UHF_TX_PKT_FORMAT]=8,
        [NVM_UHF_TX_PKT_CRC_ENB]=8,
        [NVM_UHF_TX_PKT_LEN_CFG]=8,
        [NVM_UHF_TX_PKT_DEV_ADDR]=8,
        [NVM_UHF_RX_PKT_DEMOD_SYNC_WORD]=16,
        [NVM_UHF_RX_PKT_MAX_PKT_LEN]=8,
        [NVM_UHF_RX_PKT_WHITE_ENB]=8,
        [NVM_UHF_RX_PKT_FORMAT]=8,
        [NVM_UHF_RX_PKT_CRC_ENB]=8,
        [NVM_UHF_RX_PKT_LEN_CFG]=8,
        [NVM_UHF_RX_PKT_DEV_ADDR]=8,
        [NVM_UHF_GS_FIRST_CONTACT]=8,
        [NVM_UHF_OTSU_FIRST_CONTACT]=8,
        [NVM_UHF_BEACON_TX_TIMEOUT]=8,
        [NVM_UHF_BEACON_TX_INTERVAL]=8,
        [NVM_UHF_BEACON_MODE_TIMEOUT]=32,
        [NVM_UHF_BEACON_PAYLOAD_LEN]=8,
        [NVM_UHF_TX_WIN_TIMEOUT]=8,
        [NVM_UHF_RX_WIN_TIMEOUT]=8,
        [NVM_UHF_LAST_UPTIME]=32,
        [NVM_UHF_FW_AES_KEY]=256,
        [NVM_SBAND_RX_FREQ]=32,
        [NVM_SBAND_RX_TYPE]=8,
        [NVM_SBAND_RX_RATE]=32,
        [NVM_SBAND_RX_ROLLOFF]=8,
        [NVM_SBAND_RX_AFC]=32,
        [NVM_SBAND_RX_RS]=8,
        [NVM_SBAND_RX_CC]=8,
        [NVM_SBAND_RX_RAND]=8,
        [NVM_SBAND_RX_CRC]=8,
        [NVM_SBAND_RX_SIZE]=16,
        [NVM_SBAND_RX_ID]=16,
        [NVM_SBAND_RX_RSVD1]=32,
        [NVM_SBAND_RX_FRAMES]=32,
        [NVM_SBAND_RX_DETECTED]=32,
        [NVM_SBAND_RX_RSSI]=32,
        [NVM_SBAND_RX_FREQERR]=32,
        [NVM_SBAND_RX_SYMERR]=32,
        [NVM_SBAND_RX_RSVD2]=32,
        [NVM_SBAND_RX_RSVD3]=8,
        [NVM_SBAND_RX_RSVD4]=8,
        [NVM_SBAND_TX_FREQ]=32,
        [NVM_SBAND_TX_TYPE]=8,
        [NVM_SBAND_TX_RATE]=32,
        [NVM_SBAND_TX_ROLLOFF]=8,
        [NVM_SBAND_TX_POUT]=32,
        [NVM_SBAND_TX_ALC]=8,
        [NVM_SBAND_TX_RS]=8,
        [NVM_SBAND_TX_CC]=8,
        [NVM_SBAND_TX_RAND]=8,
        [NVM_SBAND_TX_CRC]=16,
        [NVM_SBAND_TX_IDLETIME]=16,
        [NVM_SBAND_TX_SIZE]=16,
        [NVM_SBAND_TX_ID]=16,
        [NVM_SBAND_TX_RSVD1]=32,
        [NVM_SBAND_TMP_LIMIT]=8,
        [NVM_SBAND_TX_FRAMES]=32,
        [NVM_SBAND_TX_RSVD2]=32,
        [NVM_SBAND_TX_RSVD3]=32,
        [NVM_SBAND_IP_STAK_ENABLE]=8,
        [NVM_SBAND_IQS_DEV_IP]=120,
        [NVM_SBAND_IQS_DEV_PORT]=64,
        [NVM_SBAND_ETH_PREFIX_RSVD]=8,
        [NVM_SBAND_IQS_DEV_IP_TEMP]=120,
        [NVM_SBAND_IQS_DEV_PORT_UDP]=64,
        [NVM_SBAND_IQS_DEV_IP_UDP]=120,
        [NVM_SBAND_NET_PREFIX_RSVD]=8,
        [NVM_SBAND_LEOPS_PRD_KEY]=288,
        [NVM_SBAND_CONOPS_PRD_KEY]=288,
        [NVM_SBAND_RX_GAIN]=32,
        [NVM_SBAND_IDX_GAIN]=32,
        [NVM_SBAND_PWR_MIN]=32,
        [NVM_SBAND_PWR_MAX]=32,
        [NVM_SBAND_RX_CHAN_NUM]=8,
        [NVM_SBAND_MTU_SIZE]=32,
        [NVM_SBAND_PWR_ATTN_LUT]=120,
        [NVM_SBAND_TX_ATTN_GAIN]=32,
        [NVM_SBAND_FPGA_VER]=56,
        [NVM_SBAND_SWAP_VER]=56,
        [NVM_SBAND_CPU_VER]=56,
        [NVM_SBAND_GS_FIRST_CONTACT]=8,
        [NVM_SBAND_OTSU_FIRST_CONTACT]=8,
        [NVM_SBAND_BEACON_TX_TIMEOUT]=8,
        [NVM_SBAND_TX_WIN_TIMEOUT]=8,
		[BOOT_STS]=8,
		[NVM_HW_PL_TRANSCELESTIAL]=8,
		[NVM_HW_X_BAND]=8,
		[NVM_HW_S_BAND]=8,
		[NVM_HW_ADCS0]=8,
		[NVM_HW_ADCS]=8,
		[NVM_HW_PROP_UNIT_THRUSTER]=8,
		[NVM_HW_PL_ZES]=8,
		[NVM_HW_PL_SAYARLABS]=8,
		[NVM_HW_PL_NETRA]=8,
		[NVM_HW_EDGE_BRD]=8,
		[NVM_HW_OBC_PS_GPS_STD_PL_BRD]=8,
		[NVM_HW_HRM]=8,
		[NVM_HW_PL_SERVER]=8,
		[NVM_HW_GPS]=8,
		[NVM_SW_PL_TRANSCELESTIAL]=8,
		[NVM_SW_X_BAND]=8,
		[NVM_SW_S_BAND]=8,
		[NVM_SW_ADCS0]=8,
		[NVM_SW_ADCS]=8,
		[NVM_SW_PROP_UNIT_THRUSTER]=8,
		[NVM_SW_PL_ZES]=8,
		[NVM_SW_PL_SAYARLABS]=8,
		[NVM_SW_PL_NETRA]=8,
		[NVM_SW_EDGE_BRD]=8,
		[NVM_SW_OBC_PS_GPS_STD_PL_BRD]=8,
		[NVM_SW_HRM]=8,
		[NVM_SW_PL_SERVER]=8,
		[NVM_SW_GPS]=8,
		[NVM_SW_TC_TM]=8,
		[NVM_SW_SCH]=8,
		[NVM_SW_OTSU]=8,
		[NVM_GS_FIRST_CONTACT]=8,
		[NVM_GS_OTSU_CONTACT]=8,
		[RTC_TIME_DATE_TEMPORARY]=64,
		[RTC_TIME_DATE_PERMANENT]=64,
		[NVM_EPS_MCU1_FW_SIZE]=32,
		[NVM_EPS_MCU1_FW_CHECKSUM]=32,
		[NVM_EPS_MCU1_FW_AVAILABLITY]=8,
		[NVM_EPS_MCU2_FW_SIZE]=32,
		[NVM_EPS_MCU2_FW_CHECKSUM]=32,
		[NVM_EPS_MCU2_FW_AVAILABLITY]=8,
		[EPS_CHNL_PWR_STE]=16,
		[EPS_OP_CHNL_FW_MJR_VERS]=8,
		[EPS_OP_CHNL_FW_MNR_VERS]=8,
		[EPS_OP_CHNL_FW_PATCH_VERS]=8,
		[EPS_CONV_BRD_FW_MJR_VERS]=8,
		[EPS_CONV_BRD_FW_MNR_VERS]=8,
		[EPS_CONV_BRD_FW_PATCH_VERS]=8,
[NVM_EPS_MCU1_BCKUP_FW_SIZE]=32,
		[NVM_EPS_MCU1_BCKUP_FW_CHECKSUM]=32,
		[NVM_EPS_MCU1_BCKUP_FW_AVAILABLITY]=8,
		[NVM_EPS_MCU2_BCKUP_FW_SIZE]=32,
		[NVM_EPS_MCU2_BCKUP_FW_CHECKSUM]=32,
		[NVM_EPS_MCU2_BCKUP_FW_AVAILABLITY]=8,
		[NVM_EPS_MCU1_SEC_FW_MJR_VERS]=8,
		[NVM_EPS_MCU1_SEC_FW_MNR_VERS]=8,
		[NVM_EPS_MCU1_SEC_FW_PATCH_VERS]=8,
		[NVM_EPS_MCU2_SEC_FW_MJR_VERS]=8,
		[NVM_EPS_MCU2_SEC_FW_MNR_VERS]=8,
		[NVM_EPS_MCU2_SEC_FW_PATCH_VERS]=8,
		[NVM_EPS_MCU1_BCKUP_FW_MJR_VERS]=8,
		[NVM_EPS_MCU1_BCKUP_FW_MNR_VERS]=8,
		[NVM_EPS_MCU1_BCKUP_FW_PATCH_VERS]=8,
		[NVM_EPS_MCU2_BCKUP_FW_MJR_VERS]=8,
		[NVM_EPS_MCU2_BCKUP_FW_MNR_VERS]=8,
		[NVM_EPS_MCU2_BCKUP_FW_PATCH_VERS]=8,
		[NVM_ADCS_FW_STATUS]=8,
		[NVM_ADCS_FW_SIZE]=32,
		[NVM_ADCS_FW_CRC]=16,
		[NVM_ADCS_DEFAULT_INTERFACE]=8,
		[NVM_ADCS_AUTO_COMMISIONING]=8,
		[DBG_CB_IDX]=8,
		[DBG_CB_0]=2048,
		[DBG_CB_1]=2048,
		[DBG_CB_2]=2048,
		[DBG_CB_3]=2048,
		[DBG_CB_4]=2048,
		[DBG_CB_5]=2048,
		[DBG_CB_6]=2048,
		[DBG_CB_7]=2048,
		[DBG_CB_8]=2048,
		[DBG_CB_9]=2048,
		[DBG_CB_10]=2048,
		[DBG_CB_11]=2048,
		[DBG_CB_12]=2048,
		[DBG_CB_13]=2048,
		[DBG_CB_14]=2048,
		[DBG_CB_15]=2048,
		[DBG_CB_16]=2048,
		[DBG_CB_17]=2048,
		[DBG_CB_18]=2048,
		[DBG_CB_19]=2048,
		[NVM_REBOOT_RSN_BUFF]=960,
		[NVM_REBOOT_RSN_IDX]=8,
		[NVM_SSD_PL_HEAT_CTRL]=8,
		[NVM_SSD_EDGE_HEAT_CTRL]=8,
		[NVM_MIN_RBT_TIME]=32,
		[NVM_TLE_BUFF]=512,
		[NVM_OTSU_GS_SYNC_INT_TIM_CTR]=32,
		[NVM_TC_TM_ENCRYP_KEY]=2048,
		[NVM_EPS_FTM_FILE_CONTXT_DATA]=128,
		[NVM_EPS_FTM_CONTXT_DATA] =1600,
		[NVM_ADCS_FTM_FILE_CONTXT_DATA]=128,
		[NVM_ADCS_FTM_CONTXT_DATA] =1600,
		[NVM_COMMS_FTM_FILE_CONTXT_DATA]=128,
		[NVM_COMMS_FTM_CONTXT_DATA] =1600,
		[NVM_LOGGER_BACKUP_DATA] =48,
		[NVM_LOGGER_BACKUP_CFG] =8,
		[NVM_LOGGER_BACKUP_SAVE_THRLD] =8,
		[NVM_EDGE_SSD_SLOT_CFG] = 8,
		[NVM_PS_SSD_SLOT_CFG] =8,
		[NVM_PERIODICITY] = 32,
		[NVM_PS_HEAT_COIL_PRDCTY] = 32,
		[NVM_EDGE_HEAT_COIL_PRDCTY] = 32,
		[NVM_LOGGER_LOG_LEVEL_CFG] = 96,
        [NVM_LOGGER_LOG_LEVEL_CHKSUM] = 32,
        [NVM_ERR_IO] = 32,
        [NVM_ERR_AHW_SET_1] = 32,
        [NVM_ERR_AHW_SET_2] = 32,
        [NVM_ERR_SYSTEM] = 32,
        [NVM_ERR_SERVICES] = 32,      //237 BYTES
        [NVM_ERR_COMMS] = 32,
        [NVM_ERR_ADCS_MODULE] = 32,
        [NVM_ERR_EPS] = 32,
        [NVM_ERR_RESV_1] = 32,
        [NVM_ERR_HISTORY_SAVE_CURRENT_INDX_CNTR] = 8,
        [NVM_ERR_HIS_0] = 80,
        [NVM_ERR_HIS_1] = 80,
        [NVM_ERR_HIS_2] = 80,
        [NVM_ERR_HIS_3] = 80,
        [NVM_ERR_HIS_4] = 80,
        [NVM_ERR_HIS_5] = 80,
        [NVM_ERR_HIS_6] = 80,
        [NVM_ERR_HIS_7] = 80,
        [NVM_ERR_HIS_8] = 80,
        [NVM_ERR_HIS_9] = 80,
        [NVM_ERR_HIS_10] = 80,
        [NVM_ERR_HIS_11] = 80,
        [NVM_ERR_HIS_12] = 80,
        [NVM_ERR_HIS_13] = 80,
        [NVM_ERR_HIS_14] = 80,
        [NVM_ERR_HIS_15] = 80,
        [NVM_ERR_HIS_16] = 80,
        [NVM_ERR_HIS_17] = 80,
        [NVM_ERR_HIS_18] = 80,
        [NVM_ERR_HIS_19] = 80,
		[NVM_GPS_LOC_NTFY_PRDCTY] = 16,
		[NVM_GPS_TLE_NTFY_PRDCTY] = 16,
		[NVM_GPS_SYNC_TIME_PRDCTY] = 32,
   [NVM_UHF_FW_SIZE]= 32,
		[NVM_UHF_FW_CRC]= 32,
		[SDR_CFG_NUM_SDR]= 8,
		[SDR_CFG_RADIO_ID_1]= 8,
		[SDR_CFG_STS_1]= 8,
		[SDR_CFG_DUPLEX_TYPE_1]= 8,
		[SDR_CFG_NUM_RX_1]= 8,
		[SDR_CFG_NUM_TX_1]= 8,
		[SDR_CFG_COMBINED_RX_SUPPORT_1]= 8,
		[SDR_CFG_COMBINED_TX_SUPPORT_1]= 8,
		[SDR_CFG_MIN_FREQUENCY_1]= 32,
		[SDR_CFG_MAX_FREQUENCY_1]= 32,
		[SDR_CFG_MIN_FREQUENCY_RX_1]= 32,
		[SDR_CFG_MAX_FREQUENCY_RX_1]= 32,
		[SDR_CFG_RESERVED_1]= 32,
		[SDR_BEACON_NORMAL_ENB_TMR_1]= 32,
		[SDR_BEACON_NORMAL_PRD_TMR_1]= 32,
		[SDR_BEACON_NORMAL_REP_TMR_1]= 32,
		[SDR_BEACON_SAFE_ENB_TMR_1]= 32,
		[SDR_BEACON_SAFE_PRD_TMR_1]= 32,
		[SDR_BEACON_SAFE_REP_TMR_1]= 32,
		[SDR_NORMAL_TM_TMR_1]= 32,
		[SDR_NORMAL_TX_ON_TMR_1]= 32,
		[SDR_NORMAL_RX_ON_TMR_1]= 32,
		[SDR_SAFE_TM_TMR_1]= 32,
		[SDR_SAFE_TX_ON_TMR_1]= 32,
		[SDR_SAFE_RX_ON_TMR_1]= 32,
		[SDR_TX_DATA_REP_CNT_1]= 32,
		[SDR_RSSI_READ_TMR_1]= 32,
		[SDR_VALID_RSSI_CNT_1]= 8,
		[SDR_INV_RSSI_CNT_1]= 8,
		[SDR_RSSI_MIN_1]= 32,
		[SDR_RSSI_TYPE_1]= 32,
		[SDR_RSSI_PRD_TMR_1]= 32,
		[SDR_RSSI_SHORT_RX_ON_TMR_1]= 32,
		[SDR_RSSI_LONG_RX_ON_TMR_1]= 32,
		[SDR_TM_AUTO_READ_STS_1]= 8,
		[SDR_TM_PERIODICITY_1]= 32,
		[SDR_TM_SHORT_STORAGE_DURATION_1]= 32,
		[SDR_TM_LONG_STORAGE_DURATION_1]= 32,
                [SDR_TEMP_SENS_TYP_THRS_1_1]= 16,
                [SDR_TEMP_SENS_TYP_THRS_1_2]= 16,
                [SDR_TEMP_SENS_TYP_THRS_1_3]= 16,
                [SDR_TEMP_SENS_TYP_THRS_1_4]= 16,
                [SDR_TEMP_SENS_TYP_THRS_1_5]= 16,
                [SDR_TEMP_SENS_TYP_THRS_1_6]= 16,
                [SDR_TEMP_SENS_MIN_THRS_1_1]= 16,
                [SDR_TEMP_SENS_MIN_THRS_1_2]= 16,
                [SDR_TEMP_SENS_MIN_THRS_1_3]= 16,
                [SDR_TEMP_SENS_MIN_THRS_1_4]= 16,
                [SDR_TEMP_SENS_MIN_THRS_1_5]= 16,
                [SDR_TEMP_SENS_MIN_THRS_1_6]= 16,
                [SDR_TEMP_SENS_MAX_THRS_1_1]= 16,
                [SDR_TEMP_SENS_MAX_THRS_1_2]= 16,
                [SDR_TEMP_SENS_MAX_THRS_1_3]= 16,
                [SDR_TEMP_SENS_MAX_THRS_1_4]= 16,
                [SDR_TEMP_SENS_MAX_THRS_1_5]= 16,
                [SDR_TEMP_SENS_MAX_THRS_1_6]= 16,
                [SDR_VOLT_SENS_TYP_THRS_1_1]= 16,
                [SDR_VOLT_SENS_TYP_THRS_1_2]= 16,
                [SDR_VOLT_SENS_TYP_THRS_1_3]= 16,
                [SDR_VOLT_SENS_TYP_THRS_1_4]= 16,
                [SDR_VOLT_SENS_TYP_THRS_1_5]= 16,
                [SDR_VOLT_SENS_TYP_THRS_1_6]= 16,
                [SDR_VOLT_SENS_MIN_THRS_1_1]= 16,
                [SDR_VOLT_SENS_MIN_THRS_1_2]= 16,
                [SDR_VOLT_SENS_MIN_THRS_1_3]= 16,
                [SDR_VOLT_SENS_MIN_THRS_1_4]= 16,
                [SDR_VOLT_SENS_MIN_THRS_1_5]= 16,
                [SDR_VOLT_SENS_MIN_THRS_1_6]= 16,
                [SDR_VOLT_SENS_MAX_THRS_1_1]= 16,
                [SDR_VOLT_SENS_MAX_THRS_1_2]= 16,
                [SDR_VOLT_SENS_MAX_THRS_1_3]= 16,
                [SDR_VOLT_SENS_MAX_THRS_1_4]= 16,
                [SDR_VOLT_SENS_MAX_THRS_1_5]= 16,
                [SDR_VOLT_SENS_MAX_THRS_1_6]= 16,
                [SDR_CUR_SENS_TYP_THRS_1_1]= 16,
                [SDR_CUR_SENS_TYP_THRS_1_2]= 16,
                [SDR_CUR_SENS_TYP_THRS_1_3]= 16,
                [SDR_CUR_SENS_TYP_THRS_1_4]= 16,
                [SDR_CUR_SENS_TYP_THRS_1_5]= 16,
                [SDR_CUR_SENS_TYP_THRS_1_6]= 16,
                [SDR_CUR_SENS_MIN_THRS_1_1]= 16,
                [SDR_CUR_SENS_MIN_THRS_1_2]= 16,
                [SDR_CUR_SENS_MIN_THRS_1_3]= 16,
                [SDR_CUR_SENS_MIN_THRS_1_4]= 16,
                [SDR_CUR_SENS_MIN_THRS_1_5]= 16,
                [SDR_CUR_SENS_MIN_THRS_1_6]= 16,
                [SDR_CUR_SENS_MAX_THRS_1_1]= 16,
                [SDR_CUR_SENS_MAX_THRS_1_2]= 16,
                [SDR_CUR_SENS_MAX_THRS_1_3]= 16,
                [SDR_CUR_SENS_MAX_THRS_1_4]= 16,
                [SDR_CUR_SENS_MAX_THRS_1_5]= 16,
                [SDR_CUR_SENS_MAX_THRS_1_6]= 16,
		[SDR_CFG_RADIO_ID_2]= 8,
		[SDR_CFG_STS_2]= 8,
		[SDR_CFG_DUPLEX_TYPE_2]= 8,
		[SDR_CFG_NUM_RX_2]= 8,
		[SDR_CFG_NUM_TX_2]= 8,
		[SDR_CFG_COMBINED_RX_SUPPORT_2]= 8,
		[SDR_CFG_COMBINED_TX_SUPPORT_2]= 8,
		[SDR_CFG_MIN_FREQUENCY_2]= 32,
		[SDR_CFG_MAX_FREQUENCY_2]= 32,
		[SDR_CFG_MIN_FREQUENCY_RX_2]= 32,
		[SDR_CFG_MAX_FREQUENCY_RX_2]= 32,
		[SDR_CFG_RESERVED_2]= 32,
		[SDR_BEACON_NORMAL_ENB_TMR_2]= 32,
		[SDR_BEACON_NORMAL_PRD_TMR_2]= 32,
		[SDR_BEACON_NORMAL_REP_TMR_2]= 32,
		[SDR_BEACON_SAFE_ENB_TMR_2]= 32,
		[SDR_BEACON_SAFE_PRD_TMR_2]= 32,
		[SDR_BEACON_SAFE_REP_TMR_2]= 32,
		[SDR_NORMAL_TM_TMR_2]= 32,
		[SDR_NORMAL_TX_ON_TMR_2]= 32,
		[SDR_NORMAL_RX_ON_TMR_2]= 32,
		[SDR_SAFE_TM_TMR_2]= 32,
		[SDR_SAFE_TX_ON_TMR_2]= 32,
		[SDR_SAFE_RX_ON_TMR_2]= 32,
		[SDR_TX_DATA_REP_CNT_2]= 32,
		[SDR_RSSI_READ_TMR_2]= 32,
		[SDR_VALID_RSSI_CNT_2]= 8,
		[SDR_INV_RSSI_CNT_2]= 8,
		[SDR_RSSI_MIN_2]= 32,
		[SDR_RSSI_TYPE_2]= 32,
		[SDR_RSSI_PRD_TMR_2]= 32,
		[SDR_RSSI_SHORT_RX_ON_TMR_2]= 32,
		[SDR_RSSI_LONG_RX_ON_TMR_2]= 32,
		[SDR_TM_AUTO_READ_STS_2]= 8,
		[SDR_TM_PERIODICITY_2]= 32,
		[SDR_TM_SHORT_STORAGE_DURATION_2]= 32,
                [SDR_TM_LONG_STORAGE_DURATION_2]= 32,
                [SDR_TEMP_SENS_TYP_THRS_2_1]= 16,
                [SDR_TEMP_SENS_TYP_THRS_2_2]= 16,
                [SDR_TEMP_SENS_TYP_THRS_2_3]= 16,
                [SDR_TEMP_SENS_TYP_THRS_2_4]= 16,
                [SDR_TEMP_SENS_TYP_THRS_2_5]= 16,
                [SDR_TEMP_SENS_TYP_THRS_2_6]= 16,
                [SDR_TEMP_SENS_MIN_THRS_2_1]= 16,
                [SDR_TEMP_SENS_MIN_THRS_2_2]= 16,
                [SDR_TEMP_SENS_MIN_THRS_2_3]= 16,
                [SDR_TEMP_SENS_MIN_THRS_2_4]= 16,
                [SDR_TEMP_SENS_MIN_THRS_2_5]= 16,
                [SDR_TEMP_SENS_MIN_THRS_2_6]= 16,
                [SDR_TEMP_SENS_MAX_THRS_2_1]= 16,
                [SDR_TEMP_SENS_MAX_THRS_2_2]= 16,
                [SDR_TEMP_SENS_MAX_THRS_2_3]= 16,
                [SDR_TEMP_SENS_MAX_THRS_2_4]= 16,
                [SDR_TEMP_SENS_MAX_THRS_2_5]= 16,
                [SDR_TEMP_SENS_MAX_THRS_2_6]= 16,
                [SDR_VOLT_SENS_TYP_THRS_2_1]= 16,
                [SDR_VOLT_SENS_TYP_THRS_2_2]= 16,
                [SDR_VOLT_SENS_TYP_THRS_2_3]= 16,
                [SDR_VOLT_SENS_TYP_THRS_2_4]= 16,
                [SDR_VOLT_SENS_TYP_THRS_2_5]= 16,
                [SDR_VOLT_SENS_TYP_THRS_2_6]= 16,
                [SDR_VOLT_SENS_MIN_THRS_2_1]= 16,
                [SDR_VOLT_SENS_MIN_THRS_2_2]= 16,
                [SDR_VOLT_SENS_MIN_THRS_2_3]= 16,
                [SDR_VOLT_SENS_MIN_THRS_2_4]= 16,
                [SDR_VOLT_SENS_MIN_THRS_2_5]= 16,
                [SDR_VOLT_SENS_MIN_THRS_2_6]= 16,
                [SDR_VOLT_SENS_MAX_THRS_2_1]= 16,
                [SDR_VOLT_SENS_MAX_THRS_2_2]= 16,
                [SDR_VOLT_SENS_MAX_THRS_2_3]= 16,
                [SDR_VOLT_SENS_MAX_THRS_2_4]= 16,
                [SDR_VOLT_SENS_MAX_THRS_2_5]= 16,
                [SDR_VOLT_SENS_MAX_THRS_2_6]= 16,
                [SDR_CUR_SENS_TYP_THRS_2_1]= 16,
                [SDR_CUR_SENS_TYP_THRS_2_2]= 16,
                [SDR_CUR_SENS_TYP_THRS_2_3]= 16,
                [SDR_CUR_SENS_TYP_THRS_2_4]= 16,
                [SDR_CUR_SENS_TYP_THRS_2_5]= 16,
                [SDR_CUR_SENS_TYP_THRS_2_6]= 16,
                [SDR_CUR_SENS_MIN_THRS_2_1]= 16,
                [SDR_CUR_SENS_MIN_THRS_2_2]= 16,
                [SDR_CUR_SENS_MIN_THRS_2_3]= 16,
                [SDR_CUR_SENS_MIN_THRS_2_4]= 16,
                [SDR_CUR_SENS_MIN_THRS_2_5]= 16,
                [SDR_CUR_SENS_MIN_THRS_2_6]= 16,
                [SDR_CUR_SENS_MAX_THRS_2_1]= 16,
                [SDR_CUR_SENS_MAX_THRS_2_2]= 16,
                [SDR_CUR_SENS_MAX_THRS_2_3]= 16,
                [SDR_CUR_SENS_MAX_THRS_2_4]= 16,
                [SDR_CUR_SENS_MAX_THRS_2_5]= 16,
                [SDR_CUR_SENS_MAX_THRS_2_6]= 16,
		[SDR_CFG_RADIO_ID_3]= 8,
		[SDR_CFG_STS_3]= 8,
		[SDR_CFG_DUPLEX_TYPE_3]= 8,
		[SDR_CFG_NUM_RX_3]= 8,
		[SDR_CFG_NUM_TX_3]= 8,
		[SDR_CFG_COMBINED_RX_SUPPORT_3]= 8,
		[SDR_CFG_COMBINED_TX_SUPPORT_3]= 8,
		[SDR_CFG_MIN_FREQUENCY_3]= 32,
		[SDR_CFG_MAX_FREQUENCY_3]= 32,
		[SDR_CFG_MIN_FREQUENCY_RX_3]= 32,
		[SDR_CFG_MAX_FREQUENCY_RX_3]= 32,
		[SDR_CFG_RESERVED_3]= 32,
		[SDR_BEACON_NORMAL_ENB_TMR_3]= 32,
		[SDR_BEACON_NORMAL_PRD_TMR_3]= 32,
		[SDR_BEACON_NORMAL_REP_TMR_3]= 32,
		[SDR_BEACON_SAFE_ENB_TMR_3]= 32,
		[SDR_BEACON_SAFE_PRD_TMR_3]= 32,
		[SDR_BEACON_SAFE_REP_TMR_3]= 32,
		[SDR_NORMAL_TM_TMR_3]= 32,
		[SDR_NORMAL_TX_ON_TMR_3]= 32,
		[SDR_NORMAL_RX_ON_TMR_3]= 32,
		[SDR_SAFE_TM_TMR_3]= 32,
		[SDR_SAFE_TX_ON_TMR_3]= 32,
		[SDR_SAFE_RX_ON_TMR_3]= 32,
		[SDR_TX_DATA_REP_CNT_3]= 32,
		[SDR_RSSI_READ_TMR_3]= 32,
		[SDR_VALID_RSSI_CNT_3]= 8,
		[SDR_INV_RSSI_CNT_3]= 8,
		[SDR_RSSI_MIN_3]= 32,
		[SDR_RSSI_TYPE_3]= 32,
		[SDR_RSSI_PRD_TMR_3]= 32,
		[SDR_RSSI_SHORT_RX_ON_TMR_3]= 32,
		[SDR_RSSI_LONG_RX_ON_TMR_3]= 32,
		[SDR_TM_AUTO_READ_STS_3]= 8,
		[SDR_TM_PERIODICITY_3]= 32,
		[SDR_TM_SHORT_STORAGE_DURATION_3]= 32,
		[SDR_TM_LONG_STORAGE_DURATION_3]= 32,
                [SDR_TEMP_SENS_TYP_THRS_3_1]= 16,
                [SDR_TEMP_SENS_TYP_THRS_3_2]= 16,
                [SDR_TEMP_SENS_TYP_THRS_3_3]= 16,
                [SDR_TEMP_SENS_TYP_THRS_3_4]= 16,
                [SDR_TEMP_SENS_TYP_THRS_3_5]= 16,
                [SDR_TEMP_SENS_TYP_THRS_3_6]= 16,
                [SDR_TEMP_SENS_MIN_THRS_3_1]= 16,
                [SDR_TEMP_SENS_MIN_THRS_3_2]= 16,
                [SDR_TEMP_SENS_MIN_THRS_3_3]= 16,
                [SDR_TEMP_SENS_MIN_THRS_3_4]= 16,
                [SDR_TEMP_SENS_MIN_THRS_3_5]= 16,
                [SDR_TEMP_SENS_MIN_THRS_3_6]= 16,
                [SDR_TEMP_SENS_MAX_THRS_3_1]= 16,
                [SDR_TEMP_SENS_MAX_THRS_3_2]= 16,
                [SDR_TEMP_SENS_MAX_THRS_3_3]= 16,
                [SDR_TEMP_SENS_MAX_THRS_3_4]= 16,
                [SDR_TEMP_SENS_MAX_THRS_3_5]= 16,
                [SDR_TEMP_SENS_MAX_THRS_3_6]= 16,
                [SDR_VOLT_SENS_TYP_THRS_3_1]= 16,
                [SDR_VOLT_SENS_TYP_THRS_3_2]= 16,
                [SDR_VOLT_SENS_TYP_THRS_3_3]= 16,
                [SDR_VOLT_SENS_TYP_THRS_3_4]= 16,
                [SDR_VOLT_SENS_TYP_THRS_3_5]= 16,
                [SDR_VOLT_SENS_TYP_THRS_3_6]= 16,
                [SDR_VOLT_SENS_MIN_THRS_3_1]= 16,
                [SDR_VOLT_SENS_MIN_THRS_3_2]= 16,
                [SDR_VOLT_SENS_MIN_THRS_3_3]= 16,
                [SDR_VOLT_SENS_MIN_THRS_3_4]= 16,
                [SDR_VOLT_SENS_MIN_THRS_3_5]= 16,
                [SDR_VOLT_SENS_MIN_THRS_3_6]= 16,
                [SDR_VOLT_SENS_MAX_THRS_3_1]= 16,
                [SDR_VOLT_SENS_MAX_THRS_3_2]= 16,
                [SDR_VOLT_SENS_MAX_THRS_3_3]= 16,
                [SDR_VOLT_SENS_MAX_THRS_3_4]= 16,
                [SDR_VOLT_SENS_MAX_THRS_3_5]= 16,
                [SDR_VOLT_SENS_MAX_THRS_3_6]= 16,
                [SDR_CUR_SENS_TYP_THRS_3_1]= 16,
                [SDR_CUR_SENS_TYP_THRS_3_2]= 16,
                [SDR_CUR_SENS_TYP_THRS_3_3]= 16,
                [SDR_CUR_SENS_TYP_THRS_3_4]= 16,
                [SDR_CUR_SENS_TYP_THRS_3_5]= 16,
                [SDR_CUR_SENS_TYP_THRS_3_6]= 16,
                [SDR_CUR_SENS_MIN_THRS_3_1]= 16,
                [SDR_CUR_SENS_MIN_THRS_3_2]= 16,
                [SDR_CUR_SENS_MIN_THRS_3_3]= 16,
                [SDR_CUR_SENS_MIN_THRS_3_4]= 16,
                [SDR_CUR_SENS_MIN_THRS_3_5]= 16,
                [SDR_CUR_SENS_MIN_THRS_3_6]= 16,
                [SDR_CUR_SENS_MAX_THRS_3_1]= 16,
                [SDR_CUR_SENS_MAX_THRS_3_2]= 16,
                [SDR_CUR_SENS_MAX_THRS_3_3]= 16,
                [SDR_CUR_SENS_MAX_THRS_3_4]= 16,
                [SDR_CUR_SENS_MAX_THRS_3_5]= 16,
                [SDR_CUR_SENS_MAX_THRS_3_6]= 16,
		[SDR_CFG_RADIO_ID_4]= 8,
		[SDR_CFG_STS_4]= 8,
		[SDR_CFG_DUPLEX_TYPE_4]= 8,
		[SDR_CFG_NUM_RX_4]= 8,
		[SDR_CFG_NUM_TX_4]= 8,
		[SDR_CFG_COMBINED_RX_SUPPORT_4]= 8,
		[SDR_CFG_COMBINED_TX_SUPPORT_4]= 8,
		[SDR_CFG_MIN_FREQUENCY_4]= 32,
		[SDR_CFG_MAX_FREQUENCY_4]= 32,
		[SDR_CFG_MIN_FREQUENCY_RX_4]= 32,
		[SDR_CFG_MAX_FREQUENCY_RX_4]= 32,
		[SDR_CFG_RESERVED_4]= 32,
		[SDR_BEACON_NORMAL_ENB_TMR_4]= 32,
		[SDR_BEACON_NORMAL_PRD_TMR_4]= 32,
		[SDR_BEACON_NORMAL_REP_TMR_4]= 32,
		[SDR_BEACON_SAFE_ENB_TMR_4]= 32,
		[SDR_BEACON_SAFE_PRD_TMR_4]= 32,
		[SDR_BEACON_SAFE_REP_TMR_4]= 32,
		[SDR_NORMAL_TM_TMR_4]= 32,
		[SDR_NORMAL_TX_ON_TMR_4]= 32,
		[SDR_NORMAL_RX_ON_TMR_4]= 32,
		[SDR_SAFE_TM_TMR_4]= 32,
		[SDR_SAFE_TX_ON_TMR_4]= 32,
		[SDR_SAFE_RX_ON_TMR_4]= 32,
		[SDR_TX_DATA_REP_CNT_4]= 32,
		[SDR_RSSI_READ_TMR_4]= 32,
		[SDR_VALID_RSSI_CNT_4]= 8,
		[SDR_INV_RSSI_CNT_4]= 8,
		[SDR_RSSI_MIN_4]= 32,
		[SDR_RSSI_TYPE_4]= 32,
		[SDR_RSSI_PRD_TMR_4]= 32,
		[SDR_RSSI_SHORT_RX_ON_TMR_4]= 32,
		[SDR_RSSI_LONG_RX_ON_TMR_4]= 32,
		[SDR_TM_AUTO_READ_STS_4]= 8,
                [SDR_TM_PERIODICITY_4]= 32,
                [SDR_TM_SHORT_STORAGE_DURATION_4]= 32,
                [SDR_TM_LONG_STORAGE_DURATION_4]= 32,
                [SDR_TEMP_SENS_TYP_THRS_4_1]= 16,
                [SDR_TEMP_SENS_TYP_THRS_4_2]= 16,
                [SDR_TEMP_SENS_TYP_THRS_4_3]= 16,
                [SDR_TEMP_SENS_TYP_THRS_4_4]= 16,
                [SDR_TEMP_SENS_TYP_THRS_4_5]= 16,
                [SDR_TEMP_SENS_TYP_THRS_4_6]= 16,
                [SDR_TEMP_SENS_MIN_THRS_4_1]= 16,
                [SDR_TEMP_SENS_MIN_THRS_4_2]= 16,
                [SDR_TEMP_SENS_MIN_THRS_4_3]= 16,
                [SDR_TEMP_SENS_MIN_THRS_4_4]= 16,
                [SDR_TEMP_SENS_MIN_THRS_4_5]= 16,
                [SDR_TEMP_SENS_MIN_THRS_4_6]= 16,
                [SDR_TEMP_SENS_MAX_THRS_4_1]= 16,
                [SDR_TEMP_SENS_MAX_THRS_4_2]= 16,
                [SDR_TEMP_SENS_MAX_THRS_4_3]= 16,
                [SDR_TEMP_SENS_MAX_THRS_4_4]= 16,
                [SDR_TEMP_SENS_MAX_THRS_4_5]= 16,
                [SDR_TEMP_SENS_MAX_THRS_4_6]= 16,
                [SDR_VOLT_SENS_TYP_THRS_4_1]= 16,
                [SDR_VOLT_SENS_TYP_THRS_4_2]= 16,
                [SDR_VOLT_SENS_TYP_THRS_4_3]= 16,
                [SDR_VOLT_SENS_TYP_THRS_4_4]= 16,
                [SDR_VOLT_SENS_TYP_THRS_4_5]= 16,
                [SDR_VOLT_SENS_TYP_THRS_4_6]= 16,
                [SDR_VOLT_SENS_MIN_THRS_4_1]= 16,
                [SDR_VOLT_SENS_MIN_THRS_4_2]= 16,
                [SDR_VOLT_SENS_MIN_THRS_4_3]= 16,
                [SDR_VOLT_SENS_MIN_THRS_4_4]= 16,
                [SDR_VOLT_SENS_MIN_THRS_4_5]= 16,
                [SDR_VOLT_SENS_MIN_THRS_4_6]= 16,
                [SDR_VOLT_SENS_MAX_THRS_4_1]= 16,
                [SDR_VOLT_SENS_MAX_THRS_4_2]= 16,
                [SDR_VOLT_SENS_MAX_THRS_4_3]= 16,
                [SDR_VOLT_SENS_MAX_THRS_4_4]= 16,
                [SDR_VOLT_SENS_MAX_THRS_4_5]= 16,
                [SDR_VOLT_SENS_MAX_THRS_4_6]= 16,
                [SDR_CUR_SENS_TYP_THRS_4_1]= 16,
                [SDR_CUR_SENS_TYP_THRS_4_2]= 16,
                [SDR_CUR_SENS_TYP_THRS_4_3]= 16,
                [SDR_CUR_SENS_TYP_THRS_4_4]= 16,
                [SDR_CUR_SENS_TYP_THRS_4_5]= 16,
                [SDR_CUR_SENS_TYP_THRS_4_6]= 16,
                [SDR_CUR_SENS_MIN_THRS_4_1]= 16,
                [SDR_CUR_SENS_MIN_THRS_4_2]= 16,
                [SDR_CUR_SENS_MIN_THRS_4_3]= 16,
                [SDR_CUR_SENS_MIN_THRS_4_4]= 16,
                [SDR_CUR_SENS_MIN_THRS_4_5]= 16,
                [SDR_CUR_SENS_MIN_THRS_4_6]= 16,
                [SDR_CUR_SENS_MAX_THRS_4_1]= 16,
                [SDR_CUR_SENS_MAX_THRS_4_2]= 16,
                [SDR_CUR_SENS_MAX_THRS_4_3]= 16,
                [SDR_CUR_SENS_MAX_THRS_4_4]= 16,
                [SDR_CUR_SENS_MAX_THRS_4_5]= 16,
                [SDR_CUR_SENS_MAX_THRS_4_6]= 16,
		[RSVD_BIT_1]=8,
		[RSVD_BIT_2]=8,
		[RSVD_BIT_3]=8,
		[RSVD_BIT_4]=8,
		[RSVD_BIT_5]=8,
		[RSVD_BIT_6]=8,
		[RSVD_BIT_7]=8,
		[RSVD_BIT_8]=8,
		[RSVD_BIT_9]=8,
		[RSVD_BIT_10]=8,
		[RSVD_BIT_11]=8,
		[RSVD_BIT_12]=8,
		[RSVD_BIT_13]=8,
		[RSVD_BIT_14]=8,
		[RSVD_BIT_15]=8,
		[RSVD_BIT_16]=8,
		[RSVD_BIT_17]=8,
		[RSVD_BIT_18]=8,
		[RSVD_BIT_19]=8,
		[RSVD_BIT_20]=8,
		[RSVD_BIT_21]=8,
		[RSVD_BIT_22]=8,
		[RSVD_BIT_23]=8,
		[RSVD_BIT_24]=8,
		[RSVD_BIT_25]=8,
		[RSVD_BIT_26]=8,
		[RSVD_BIT_27]=8,
		[RSVD_BIT_28]=8,
		[RSVD_BIT_29]=8,
		[RSVD_BIT_30]=8,
		[RSVD_BIT_31]=8,
		[RSVD_BIT_32]=8,
		[RSVD_BIT_33]=8,
		[RSVD_BIT_34]=8,
		[RSVD_BIT_35]=8,
		[RSVD_BIT_36]=8,
		[RSVD_BIT_37]=8,
		[RSVD_BIT_38]=8,
		[RSVD_BIT_39]=8,
		[RSVD_BIT_40]=8,
		[RSVD_BIT_41]=8,
		[RSVD_BIT_42]=8,
		[RSVD_BIT_43]=8,
		[RSVD_BIT_44]=8,
		[RSVD_BIT_45]=8,
		[RSVD_BIT_46]=8,
		[RSVD_BIT_47]=8,
		[RSVD_BIT_48]=8,
		[RSVD_BIT_49]=8,
		[RSVD_BIT_50]=8,
		[RSVD_BIT_51]=8,
		[RSVD_BIT_52]=8,
		[RSVD_BIT_53]=8,
		[RSVD_BIT_54]=8,
		[RSVD_BIT_55]=8,
		[RSVD_BIT_56]=8,
		[RSVD_BIT_57]=8,
		[RSVD_BIT_58]=8,
		[RSVD_BIT_59]=8,
		[RSVD_BIT_60]=8,
		[RSVD_BIT_61]=8,
		[RSVD_BIT_62]=8,
		[RSVD_BIT_63]=8,
		[RSVD_BIT_64]=8,
		[RSVD_BIT_65]=8,
		[RSVD_BIT_66]=8,
		[RSVD_BIT_67]=8,
		[RSVD_BIT_68]=8,
		[RSVD_BIT_69]=8,
		[RSVD_BIT_70]=8,
		[RSVD_BIT_71]=8,
		[RSVD_BIT_72]=8,
		[RSVD_BIT_73]=8,
		[RSVD_BIT_74]=8,
		[RSVD_BIT_75]=8,
		[RSVD_BIT_76]=8,
		[RSVD_BIT_77]=8,
		[RSVD_BIT_78]=8,
		[RSVD_BIT_79]=8,
		[RSVD_BIT_80]=8,
		[RSVD_BIT_81]=8,
		[RSVD_BIT_82]=8,
		[RSVD_BIT_83]=8,
		[RSVD_BIT_84]=8,
		[RSVD_BIT_85]=8,
		[RSVD_BIT_86]=8,
		[RSVD_BIT_87]=8,
		[RSVD_BIT_88]=8,
		[RSVD_BIT_89]=8,
		[RSVD_BIT_90]=8,
		[RSVD_BIT_91]=8,
		[RSVD_BIT_92]=8,
		[RSVD_BIT_93]=8,
		[RSVD_BIT_94]=8,
		[RSVD_BIT_95]=8,
		[RSVD_BIT_96]=8,
		[RSVD_BIT_97]=8,
		[RSVD_BIT_98]=8,
		[RSVD_BIT_99]=8,
		[RSVD_BIT_100]=8,
		[NVM_CHECKSUM ]=32,
};

#ifdef LINUX_TEMP_PORT
/// Sensor NVM default values in byte array
const uint8_t sensor_nvm_defaults[]=
{
		0xd, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0x8c, 0x42, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0, 0x0,
		0xb, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0x8c, 0x42, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0, 0x0,
		0xc, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0x8c, 0x42, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0, 0x0,
		0xa, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0x8c, 0x42, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0, 0x0,
		0xe, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0x8c, 0x42, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0, 0x0,
		0xf, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0x8c, 0x42, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0, 0x0,
		0x12, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0x8c, 0x42, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0, 0x0,
		0x10, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0x8c, 0x42, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0, 0x0,
		0x11, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0x8c, 0x42, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0, 0x0,
		0x6, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0xa0, 0x41, 0x0, 0x0, 0x0, 0x0, 0x3, 0x0, 0x1, 0x1,
		0x5, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0xa0, 0x41, 0x0, 0x0, 0x0, 0x0, 0x3, 0x0, 0x1, 0x1,
		0x13, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0x50, 0x41, 0x28, 0xa, 0x0, 0x0, 0x0, 0x0, 0x80, 0x40, 0x1, 0x0, 0x0, 0x0,
		0x14, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0x50, 0x41, 0x28, 0xa, 0x0, 0x0, 0x0, 0x0, 0x80, 0x40, 0x1, 0x0, 0x0, 0x0,
		0x7, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0xc0, 0x40, 0x0, 0x0, 0x80, 0x40, 0x0, 0x0, 0x0, 0x0,
		0x9, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0x50, 0x41, 0x0, 0x0, 0x80, 0x40, 0x0, 0x0, 0x0, 0x0,
		0x8, 0x0, 0x0, 0x0, 0xe0, 0x93, 0x4, 0x0, 0x0, 0x0, 0xc0, 0x40, 0x0, 0x0, 0x80, 0x40, 0x0, 0x0, 0x0, 0x0, 0xA5
};

/// Sband NVM default values in byte array
const uint8_t sband_nvm_defaults[]={  0x73, 0x72, 0x73, 0x2d, 0x34, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x80, 0x51, 0x1, 0x0, 0x18, 0x30, 0x2f, 0x30, 0x20, 0x43, 0x41, 0x4e, 0x2c, 0x31, 0x30, 0x2f,
		0x31, 0x31, 0x20, 0x53, 0x50, 0x41, 0x43, 0x45, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x40, 0x42, 0xf, 0x0, 0x1, 0x40, 0x42, 0xf, 0x0, 0x0, 0x0, 0x31, 0x39, 0x32, 0x2e, 0x31, 0x36,
		0x38, 0x2e, 0x31, 0x30, 0x30, 0x2e, 0x32, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x18, 0x31, 0x39, 0x32, 0x2e, 0x31, 0x36, 0x38, 0x2e, 0x31, 0x30, 0x30, 0x2e, 0x31, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x31, 0x39, 0x32, 0x2e, 0x31, 0x36, 0x38, 0x2e, 0x32,
		0x30, 0x30, 0x2e, 0x32, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x18, 0x31,
		0x39, 0x32, 0x2e, 0x31, 0x36, 0x38, 0x2e, 0x32, 0x30, 0x30, 0x2e, 0x31, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa0, 0xc8, 0x98, 0x40, 0x75, 0x86, 0x20, 0x3d, 0xdc, 0x5, 0xa0, 0xd5, 0xa9,
		0x85, 0x0, 0x40, 0x42, 0xf, 0x0, 0x1, 0x0, 0x0, 0x4, 0x42, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1e, 0x0, 0xd9, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x50, 0xa0, 0x13, 0xbe, 0x79, 0x0, 0x20, 0xa1, 0x7, 0x0,
		0x1, 0x1, 0x98, 0x3a, 0x0, 0x0, 0x0, 0x1, 0x0, 0x1, 0xd9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
};

/// TC/TM manager encryption key in byte array
const uint8 tc_tm_mngr_key_default[] = { 0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
		0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f
};

/// EPS NVM default values in byte array
const uint8_t eps_nvm_buff[678]={0x00, 0x00, 0x20, 0x41, 0x66, 0x66, 0x2E, 0x41, 0xCD, 0xCC, 0x3C, 0x41, 0x00, 0x00, 0x48, 0x41, 0x02, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00,
		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00,
		0x00, 0x32, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
		0x01, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03,
		0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
		0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00,
		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
		0x02, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00,
		0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x0A, 0x00,
		0x02, 0x02, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00,
		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x14, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x0A, 0x00,
		0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		0x00, 0x03, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
		0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x1C, 0x0C, 0xFF, 0x3F, 0xFF,
		0x3F, 0x00, 0x04, 0x14, 0x04, 0x14, 0x04, 0x14, 0x04
};
#endif

static uint8_t nvm_header_check(uint8_t* nvm_buff_ptr);
static uint8_t nvm_crc_check(uint8_t* nvm_buff_ptr, uint16_t length);
static uint8_t nvm_crc_calc_and_store(uint8_t* nvm_buff_ptr, uint16_t length);


/**
 * @brief API to write the data to NVM buffer
 *
 * @param[in]  id_val - NVM parameter ID
 * @param[in]  bit_length - length of parameter in bits
 * @param[in]  data - pointer to the data
 * @param[in]  nvm_idx_len_by_id - pointer to array which contains parameter index
 * @param[out]  nvm_buff - pointer NVM buffer
 *
 * @return  Returns the success or error code
 *
 * @retval  INVALID_PARTITION_ID  -  partition type is invalid.
 *          NVM_INVALID_PTR - null pointer
 *          NVM_SUCCESS - NVM write success
 *
 */
static int8_t NVM_write(uint16_t id_val,uint16_t bit_length, uint8_t *data,const uint32_t *nvm_idx_len_by_id,uint8_t *nvm_buff);

/**
 * @brief API to read the data to NVM buffer
 *
 * @param[in]  id_val - NVM parameter ID
 * @param[in]  bit_length - length of parameter in bits
 * @param[out] data - pointer to the data
 * @param[in]  nvm_idx_len_by_id - pointer to array which contains parameter index
 * @param[in]  nvm_buff - pointer NVM buffer
 *
 * @return  Returns the success or error code
 *
 * @retval  INVALID_PARTITION_ID  -  partition type is invalid.
 *          NVM_INVALID_PTR - null pointer
 *          NVM_SUCCESS - NVM read success
 *
 */
static int8_t NVM_read(uint16_t id_val,uint16_t bit_length, uint8_t *data, const uint32_t *nvm_idx_len_by_id,uint8_t *nvm_buff);

/**
 * @brief API to copy NVM data from flash memory to the NVM buffer
 *
 * @param[in]  flash_intf_type - flash interface type ID
 * @param[in]  partition_addr  - NVM partition start address
 * @param[out] nvm_buff  - pointer to NVM buffer
 * @param[in]  nvm_len  -  NVM buffer length in bytes
 *
 * @retval int8_t - returns the success or error code
 */
#ifndef LINUX_TEMP_PORT
static int8_t read_nvm_partition_from_flashmem(uint32_t partition_addr, uint8_t* nvm_destination_buff, uint32_t nvm_partition_len);
#endif

/**
 * @brief API to copy NVM data from NVM buffer to the flash memory
 *
 * @param[in]  flash_intf_type - flash interface type ID
 * @param[in]  partition_addr  - NVM partition start address
 * @param[out] nvm_buff  - pointer to NVM buffer
 * @param[in]  nvm_len  -  NVM buffer length in bytes
 *
 * @retval int8_t - returns the success or error code
 */
#ifndef LINUX_TEMP_PORT
static int8_t write_nvm_partition_to_flashmem(uint32_t partition_addr, uint8_t* nvm_source_buff, uint32_t nvm_partition_len);
#endif

/**
 * @brief API to get the NVM parameter length in bytes
 *
 * @param[in]  nvm_id - NVM parameter ID
 *
 * @retval int16_t - parameter length in bytes
 */
static int16_t read_len_from_nvm_idf(uint16_t nvm_id);

///**
// * @brief API to calculate and store the checksum
// *
// * @param[in]  ptr - pointer to data buffer
// * @param[in]  buffer_len - buffer length in bytes
// * @param[in]  nvm_buffer - pointer to NVM buffer
// *
// */
//static void calculate_nvm_checksum(uint8_t *ptr,uint16_t buffer_len,uint8_t *nvm_buffer);

/**
 * @brief API to calculate and load the NVM parameter index
 */
static void nvm_para_init();


static int16_t read_len_from_nvm_idf(uint16_t nvm_id)
{
	if(nvm_id < NVM_MAX_PARM)
	{
		return nvm_data_parm_len_by_id[nvm_id];
	}
	else
	{
		return nvm_rd_only_data_len_by_id[nvm_id-NVM_MAX_PARM];
	}
}

/**
 * This function to write NVM data to ram
 */
static int8_t NVM_write(uint16_t id_val,uint16_t bit_length, uint8_t *data,const uint32_t *nvm_idx_len_by_id,uint8_t *nvm_buff)
{
	uint32_t bit_ofst  = nvm_idx_len_by_id[id_val];
	uint32_t byte_ofst = bit_ofst >>3;
	int32_t remain_bit_len = nvm_idx_len_by_id[id_val+1] - nvm_idx_len_by_id[id_val];
        int32_t remain_byte_len=0;
	uint8_t temp_src_data=0;
	uint8_t src_data_byte_bit_ofst_point=0;
	uint8_t dst_1st_byte_bit_align = nvm_idx_len_by_id[id_val] % 8;
	uint8_t mask=0;
	/** 1st byte unaligned write handling */
	if(dst_1st_byte_bit_align)
	{
		temp_src_data = *data;
		if((remain_bit_len+dst_1st_byte_bit_align)>=8)  // this condition for mask the particular bits
		{
			mask = (0xFF >> (8-dst_1st_byte_bit_align)); // | (0xFF << ((remain_bit_len%8)+dst_1st_byte_bit_align));
		}
		else
		{
			mask = (0xFF >> (8-dst_1st_byte_bit_align)) | (0xFF << ((remain_bit_len)+dst_1st_byte_bit_align));
		}
		nvm_buff[byte_ofst] = ((nvm_buff[byte_ofst] & (mask)) \
				| ((temp_src_data << dst_1st_byte_bit_align) & 0xFF));
		remain_bit_len = remain_bit_len - (8-dst_1st_byte_bit_align);
		if(remain_bit_len>0)
		{
			byte_ofst++;
			data++;
		}
		src_data_byte_bit_ofst_point = (8 - dst_1st_byte_bit_align);
	}
	else
	{
		temp_src_data = *data;
		data++;
	}
	if(remain_bit_len>0)
	{
		remain_byte_len = remain_bit_len >> 3 ;
	}
	/** Aligned byte(s) write handling */
	if(remain_bit_len>0)
	{
		while(remain_byte_len)
		{
			// prepare temp_data a whole byte from source (handle if source is unaligned
			if(src_data_byte_bit_ofst_point)
			{
				temp_src_data = (temp_src_data >> (8-dst_1st_byte_bit_align)) \
						| (((*data) << dst_1st_byte_bit_align) & 0xFF);
			}
			nvm_buff[byte_ofst]  = temp_src_data;
			remain_byte_len--;
			remain_bit_len = remain_bit_len - 8;

			if(remain_bit_len)
			{
				byte_ofst++;
				temp_src_data = *data;
				data++;
			}
		}
	}
	/** Last partial byte write handling */
	if(remain_bit_len>0)
	{
		nvm_buff[byte_ofst] = (nvm_buff[byte_ofst] & (0xFF << remain_bit_len)) | ((temp_src_data >> (src_data_byte_bit_ofst_point)));
		remain_bit_len = remain_bit_len - (8-src_data_byte_bit_ofst_point);
		if(remain_bit_len>0)
		{
			// data++ already happen & nvm_buffer mask is handled in the above condition
			nvm_buff[byte_ofst] = ((nvm_buff[byte_ofst]) | \
					((*data & (0xFF>>(8-(remain_bit_len)))) << (8-src_data_byte_bit_ofst_point)));
		}
	}
	return NVM_SUCCESS;
}

/**
 * This function to read NVM data from RAM
 */
static int8_t NVM_read(uint16_t id_val,uint16_t bit_length, uint8_t *data, const uint32_t *nvm_idx_len_by_id,uint8_t *nvm_buff)
{
	int8_t mask_len=0;
	uint32_t bit_ofst  = nvm_idx_len_by_id[id_val];
	uint32_t byte_ofst = bit_ofst >>3;
	int32_t remain_bit_len = nvm_idx_len_by_id[id_val+1] - nvm_idx_len_by_id[id_val];
	int32_t remain_byte_len=0;
	uint8_t dst_bit_ofst = 0;
	if(data==NULL)
	{
	}
	if(bit_length>remain_bit_len)
	{
	}
	else if(bit_length<remain_bit_len)
	{
		remain_bit_len=bit_length;
	}
	bit_ofst = bit_ofst - (byte_ofst<<3);
	if(remain_bit_len>8)
	{
		mask_len=8;
	}
	else
	{
		mask_len=remain_bit_len;
	}
	*data =  (nvm_buff[byte_ofst] >> bit_ofst) & (0x1FF >> (9 - mask_len));
	remain_bit_len = remain_bit_len - (8 - bit_ofst);
	dst_bit_ofst =  (8 - bit_ofst)%8;
	if(remain_bit_len>0)
	{
		remain_byte_len = remain_bit_len >> 3;
	}
	while(remain_byte_len)
	{
		byte_ofst++;  // byte position shifted to next position
		if(dst_bit_ofst)
		{
			*data = *data | (nvm_buff[byte_ofst] << dst_bit_ofst) ;
			data++;
			*data =  (nvm_buff[byte_ofst] >> (8 - dst_bit_ofst)) ;
		}
		else
		{
			data++;
			*data = nvm_buff[byte_ofst];
		}
		remain_bit_len = remain_bit_len -8;
		remain_byte_len--;
	}
	if(remain_bit_len>0)
	{
		byte_ofst++;
		if(dst_bit_ofst)
		{
			*data = *data | ((nvm_buff[byte_ofst] & (0xFF >> (8 - remain_bit_len)))<<dst_bit_ofst);
			remain_bit_len=remain_bit_len-(8-dst_bit_ofst);
		}
		if(remain_bit_len>0)
		{
			data++;
			if(dst_bit_ofst)
			{
				*data =  ((nvm_buff[byte_ofst]>>(8-dst_bit_ofst)) & (0xFF >> (8 - remain_bit_len)));
			}
			else
			{
				*data = ((nvm_buff[byte_ofst]) & (0xFF >> (8 - remain_bit_len)));
			}
		}
	}
	return NVM_SUCCESS;
}

#ifndef LINUX_TEMP_PORT
/**
 * This function to read NVM data from RAM
 */
static int8_t read_nvm_partition_from_flashmem(uint32_t partition_addr, uint8_t* nvm_destination_buff, uint32_t nvm_partition_len)
{
    int8_t ret=0;
	ret = os_memcpy_extmem((uint8_t*)nvm_destination_buff,(uint8_t*)partition_addr,nvm_partition_len,NULL,1,1);
	return ret;
}

/**
 * This function to read NVM data from RAM
 */
static int8_t write_nvm_partition_to_flashmem(uint32_t partition_addr, uint8_t* nvm_source_buff, uint32_t nvm_partition_len)
{
	int8_t ret = NVM_UNKNOWN_ERROR;
	ret = os_memcpy_extmem((uint8_t*)partition_addr,(uint8_t*)nvm_source_buff,nvm_partition_len,NULL,1,1);
	return ret;
}

#endif 

#ifdef LINUX_TEMP_PORT
/**
 * This function to read NVM data from RAM
 */
static int8_t read_nvm_partition_from_flashmem(uint32_t partition_addr, uint8_t* nvm_destination_buff, uint32_t nvm_partition_len)
{
	return 0;
}

/**
 * This function to read NVM data from RAM
 */
static int8_t write_nvm_partition_to_flashmem(uint32_t partition_addr, uint8_t* nvm_source_buff, uint32_t nvm_partition_len)
{
	return 0;
}

#endif 

/**
 * This function to read NVM data from RAM
 */
static void nvm_para_init()
{
	uint16_t i=0;
	for(i=0;i<(NVM_MAX_PARM-2);i++)
	{
		nvm_parm_idx_by_id[i+1]= nvm_data_parm_len_by_id[i]+nvm_parm_idx_by_id[i];
	}

	nvm_parm_idx_by_id[NVM_DUMMY_BYTES]= nvm_data_parm_len_by_id[NVM_DUMMY_BYTES-1]+nvm_parm_idx_by_id[NVM_DUMMY_BYTES-1];
	if(((nvm_parm_idx_by_id[NVM_DUMMY_BYTES] >>3) % 4) != 0)
	{
	   nvm_data_parm_len_by_id[NVM_DUMMY_BYTES] = (4 - ((nvm_parm_idx_by_id[NVM_DUMMY_BYTES] >>3) % 4)) * 8;
	}
	else
	{
	    nvm_data_parm_len_by_id[NVM_DUMMY_BYTES] = 0;
	}
	nvm_parm_idx_by_id[NVM_CHECKSUM]= nvm_data_parm_len_by_id[NVM_CHECKSUM-1]+nvm_parm_idx_by_id[NVM_CHECKSUM-1];
	nvm_parm_idx_by_id[NVM_MAX_PARM]= nvm_data_parm_len_by_id[NVM_MAX_PARM-1]+nvm_parm_idx_by_id[NVM_MAX_PARM-1];

	os_sem_create_bin(&commit_sem, "NVM_COMMIT_SEM");
	os_sem_give(commit_sem);
	os_sem_create_bin(&nvm_write_sem, "NVM_WRITE_SEM");
	os_sem_give(nvm_write_sem);

	nvm_length = ((nvm_parm_idx_by_id[NVM_MAX_PARM])>>3);
	for(i=0;i<=((NVM_RD_MAX_PARM-NVM_MAX_PARM)-1);i++)
	{
		nvm_parm_rd_only_idx_by_id[i+1]= nvm_rd_only_data_len_by_id[i]+nvm_parm_rd_only_idx_by_id[i];
	}
}

#ifdef LINUX_TEMP_PORT
void load_nvm_header()
{
	uint8_t checksum =0;

	primary_nvm_buff[0] = NVM_HEADER_MAGIC_BYTE;
	primary_nvm_buff[1] = NVM_REV_N0_MAJOR;
	primary_nvm_buff[2] = NVM_REV_N0_MINOR;
	os_memcpy(primary_nvm_buff+3,&nvm_length,4);

	for(int i=0; i<NVM_HEADER_LEN-1; i++)
	{
		checksum^= primary_nvm_buff[i];
	}
	primary_nvm_buff[7] = checksum;
}

/**
 * This function to read NVM data from RAM
 */
uint8_t load_nvm_defaults()
{
	uint16_t nvm_wr_magic_num=NVM_MAGIC_NUMBER;
	uint8_t nvm_wr_vrsn=NVM_DATA_VERSION;
#ifndef LINUX_TEMP_PORT        
	uint16_t nvm_rev=get_nvm_revision_no();
#else        
	uint16_t nvm_rev=0;
#endif	
    uint64_t rtc_prmt_tm=1676001960;
	uint32_t min_rbt_time=360;
	uint8_t ssd_sts =0;
	uint8_t sch_crnt_evnt =1;
	uint8_t eps_flg=0xA5;

	load_nvm_header();

	nvm_parameter_write(NVM_DATA,NVM_MAGIC_NUM,(uint8_t*)&nvm_wr_magic_num);
	nvm_parameter_write(NVM_DATA,NVM_REV_NUM,(uint8_t*)&nvm_rev);
	nvm_parameter_write(NVM_DATA,NVM_VERSION,(uint8_t*)&nvm_wr_vrsn);
	nvm_parameter_write(NVM_DATA,RTC_TIME_DATE_PERMANENT,(uint8_t*)&rtc_prmt_tm);
	nvm_parameter_write(NVM_DATA,NVM_MIN_RBT_TIME,(uint8_t*)&min_rbt_time);
	ssd_sts=1; //for SSD heat coil selection
	nvm_parameter_write(NVM_DATA,NVM_SSD_PL_HEAT_CTRL,(uint8_t*)&ssd_sts);
	nvm_parameter_write(NVM_DATA,NVM_SSD_EDGE_HEAT_CTRL,(uint8_t*)&ssd_sts);
	nvm_parameter_write(NVM_DATA,CONOPS_SCH_CRNT_EVNT,(uint8_t*)&sch_crnt_evnt);
	ssd_sts=1;  //for SSD slot selection
	nvm_parameter_write(NVM_DATA,RSVD_BIT_5,(uint8_t*)&ssd_sts);   //for edge board ssd slot selection
	nvm_parameter_write(NVM_DATA,RSVD_BIT_6,(uint8_t*)&ssd_sts);   //for ps board ssd slot selection
	nvm_parameter_write(NVM_DATA,RSVD_BIT_1,(uint8_t*)&eps_flg);
	os_memcpy(primary_nvm_buff+13195+8,sensor_nvm_defaults,329);
	os_memcpy(primary_nvm_buff+13859+8,sband_nvm_defaults,470);
	os_memcpy(primary_nvm_buff+19812+8,tc_tm_mngr_key_default,257);

	return 0;
}
#endif

/**
 * This API to replace the invalid NVM partition with valid NVM partition
 */
uint8_t replace_failed_partition(nvm_partition_type valid_partition, nvm_partition_type invalid_partition, uint8_t *nvm_buffer,uint16_t buffer_len)
{
	uint8_t *ptr;
	uint8_t return_check =1;
	ptr= os_malloc(buffer_len);
	if(valid_partition==NVM_FLASH_PARTITION_1)
	{
		return_check = read_nvm_partition_from_flashmem(NVM_FLASH_PARTITION_1_ADDR,ptr,buffer_len);
		return_check = write_nvm_partition_to_flashmem(NVM_FLASH_PARTITION_2_ADDR,ptr,buffer_len);
	}
	else
	{
		return_check = read_nvm_partition_from_flashmem(NVM_FLASH_PARTITION_2_ADDR,ptr,buffer_len);
		return_check = write_nvm_partition_to_flashmem(NVM_FLASH_PARTITION_1_ADDR,ptr,buffer_len);
	}
	os_memcpy(nvm_buffer, ptr, buffer_len);
	//calculate_nvm_checksum(ptr,buffer_len,nvm_buffer);
	os_free(ptr);
	return return_check;
}

/**
 * This API to initialize the NVM partition
 */
uint8_t NVM_data_init(nvm_partition_type partition, uint16_t buffer_len, uint8_t* nvm_vrsn)
{
	uint8_t *ptr;
	uint8_t ret=NVM_UNKNOWN_ERROR;
	ptr= os_malloc(buffer_len);
	if(partition==NVM_RAM_PARTITION)
	{
		memset(ptr,0,buffer_len);
		os_memcpy(ptr,primary_nvm_buff,buffer_len);
		ret = NVM_SUCCESS;
	}
	else if(partition==NVM_FLASH_PARTITION_1)
	{
		ret = read_nvm_partition_from_flashmem(NVM_FLASH_PARTITION_1_ADDR,ptr,buffer_len);
	}
	else if(partition==NVM_FLASH_PARTITION_2)
	{
		ret = read_nvm_partition_from_flashmem(NVM_FLASH_PARTITION_2_ADDR,ptr,buffer_len);
	}
	if (ret == NVM_SUCCESS)
	{
		if(nvm_header_check(ptr) == NVM_SUCCESS)
		{
			if(nvm_crc_check(ptr,buffer_len) == NVM_SUCCESS)
			{
                  *nvm_vrsn=ptr[NVM_VERSION+NVM_HEADER_LEN+1];
				   ret = NVM_SUCCESS;

			}
			else
			{
				ret = NVM_CRC_ERROR;
			}
		}
		else
		{
			ret = NVM_INVALID;
		}
	}
	os_free(ptr);
	ptr = NULL;
	return ret;
}

/**
 * This API to initialize the NVM
 */
uint8_t nvm_flash_drive_init(void)
{
	uint8_t partition_1_sts,partition_1_vrsn=0;
	uint8_t partition_2_sts,partition_2_vrsn=0;
	uint8_t ram_partition_sts,ram_partition_vrsn;
	uint16_t total_nvm_len;
	nvm_para_init();
	total_nvm_len= nvm_length+NVM_HEADER_LEN;
	os_timer_create(&nvm_commit_timer,"nvm_commit_tmr",PERIODIC,(ral_timer_cbfunc_t)nvm_commit,NULL);
	os_timer_start(nvm_commit_timer,NVM_COMMIT_PERIODICITY);

	partition_1_sts=NVM_data_init(NVM_FLASH_PARTITION_1,total_nvm_len,&partition_1_vrsn);
	partition_2_sts=NVM_data_init(NVM_FLASH_PARTITION_2,total_nvm_len,&partition_2_vrsn);
	ram_partition_sts=NVM_data_init(NVM_RAM_PARTITION,total_nvm_len,&ram_partition_vrsn);

	// 1st partition was failed but second was valid, so copy 2 to 1
	if((ram_partition_sts==INIT_TRUE)&&(partition_1_sts!=INIT_TRUE)&&(partition_2_sts!=INIT_TRUE))
	{
		write_nvm_partition_to_flashmem(NVM_FLASH_PARTITION_1_ADDR,(uint8_t*)primary_nvm_buff,total_nvm_len);
		os_delay(10);
		write_nvm_partition_to_flashmem(NVM_FLASH_PARTITION_2_ADDR,(uint8_t*)primary_nvm_buff,total_nvm_len);
		nvm_drv_state = NVM_DRV_SUCCESS;
	}
	else if((ram_partition_sts!=INIT_TRUE)&&(partition_1_sts!=INIT_TRUE)&&(partition_2_sts==INIT_TRUE))
	{
		nvm_drv_state = NVM_DRV_SUCCESS;
		replace_failed_partition(NVM_FLASH_PARTITION_2,NVM_FLASH_PARTITION_1,primary_nvm_buff,total_nvm_len);
	}
	// 2st partition was failed but second was valid, so copy 1 to 2
	else if((ram_partition_sts!=INIT_TRUE)&&(partition_1_sts==INIT_TRUE)&&(partition_2_sts!=INIT_TRUE))
	{
		nvm_drv_state = NVM_DRV_SUCCESS;
		replace_failed_partition(NVM_FLASH_PARTITION_1,NVM_FLASH_PARTITION_2,primary_nvm_buff,total_nvm_len);
	}
	else if((ram_partition_sts!=INIT_TRUE)&&(partition_1_sts==INIT_TRUE)&&(partition_2_sts==INIT_TRUE))
	{
		nvm_drv_state = NVM_DRV_SUCCESS;
		if((partition_1_vrsn>=partition_2_vrsn) || ((partition_1_vrsn==0)&&(partition_2_vrsn==0xFF)))
		{
			read_nvm_partition_from_flashmem(NVM_FLASH_PARTITION_1_ADDR,primary_nvm_buff,total_nvm_len);
		}
		else
		{
			read_nvm_partition_from_flashmem(NVM_FLASH_PARTITION_2_ADDR,primary_nvm_buff,total_nvm_len);
		}
	}
	else if((ram_partition_sts==INIT_TRUE)&&(partition_1_sts==INIT_TRUE)&&(partition_2_sts==INIT_TRUE))
	{
		if(((ram_partition_vrsn>partition_1_vrsn) && (ram_partition_vrsn>partition_2_vrsn)) ||     \
		   ((ram_partition_vrsn==0)&&(partition_2_vrsn==0xFF)&&(ram_partition_vrsn==0)&&(partition_1_vrsn==0xFF)))
		{
			write_nvm_partition_to_flashmem(NVM_FLASH_PARTITION_1_ADDR,(uint8_t*)primary_nvm_buff,total_nvm_len);
			os_delay(10);
			write_nvm_partition_to_flashmem(NVM_FLASH_PARTITION_2_ADDR,(uint8_t*)primary_nvm_buff,total_nvm_len);
		}
		else if((partition_1_vrsn>=partition_2_vrsn) || ((partition_1_vrsn==0)&&(partition_2_vrsn==0xFF)))
		{
			read_nvm_partition_from_flashmem(NVM_FLASH_PARTITION_1_ADDR,primary_nvm_buff,total_nvm_len);

		}
		else if((partition_2_vrsn>=partition_1_vrsn) || ((partition_2_vrsn==0)&&(partition_1_vrsn==0xFF)))
		{
			read_nvm_partition_from_flashmem(NVM_FLASH_PARTITION_2_ADDR,primary_nvm_buff,total_nvm_len);

		}
		else
		{

		}
		nvm_drv_state = NVM_DRV_SUCCESS;
	}
	else
	{
		/** NVM init cannot fail, Must need handle RO data based preload values */
#ifdef LINUX_TEMP_PORT
		nvm_load_defaults(primary_nvm_buff);
		nvm_drv_state = NVM_DRV_SUCCESS;
#else
		nvm_drv_state = NVM_DRV_INVALID;
#endif
	}
#if 0
	if(nvm_preload==0)
	{
		nvm_load_defaults(primary_nvm_buff);
		nvm_drv_state = NVM_DRV_SUCCESS;
		nvm_commit();
#ifdef WDT_ENABLE
		os_delay(1000);
		HAL_NVIC_SystemReset();
#else
		while(1);
#endif
	}
#endif
	return nvm_drv_state;
}


uint8_t nvm_init(void)
{
	e_nvm_drv_state ret;
	uint8_t *default_nvm_storage_addr;
	uint16_t total_nvm_len= nvm_length+NVM_HEADER_LEN;

	/*
	 * load from nvm ram buffer or bank1 or bank2
	 */
	ret = nvm_flash_drive_init();
	if(ret != NVM_DRV_SUCCESS)
	{
		/*
		 * load from location A
		 */
		log_id(LOG_ERROR, LOG_LOGGER, NVM_FRAMEWORK_LOAD_FAIL);
		total_nvm_len= nvm_length+NVM_HEADER_LEN;
		default_nvm_storage_addr = nvm_get_nvm_fwupd_memory_partition_address(NVM_FW_UPDATE_LOC_A);
		os_memcpy_extmem(primary_nvm_buff, default_nvm_storage_addr, total_nvm_len, NULL, 1, 1);
		ret = nvm_flash_drive_init();
		if(ret != NVM_DRV_SUCCESS)
		{
			/*
			 * load default nvm
			 */
			log_id(LOG_ERROR, LOG_LOGGER, NVM_LOCATION_A_LOAD_FAIL);
			nvm_load_defaults(primary_nvm_buff);
			ret = nvm_flash_drive_init();
			if(ret != NVM_DRV_SUCCESS)
			{
				log_id(LOG_INFO_L1, LOG_LOGGER, NVM_DEFAULT_LOAD_SUCCESS);
				/* default load fail */
				ret = ret;
			}
			else
			{
				log_id(LOG_ERROR, LOG_LOGGER, NVM_DEFAULT_LOAD_FAIL);
				/* default load pass */
				ret = ret;
			}
		}
		else
		{
			log_id(LOG_INFO_L1, LOG_LOGGER, NVM_LOCATION_A_LOAD_SUCCESS);
		}
	}
	else
	{
		log_id(LOG_INFO_L1, LOG_LOGGER, NVM_FRAMEWORK_LOAD_SUCCESS);
	}
	return 0;
}

/**
 * This API to read the data in NVM partition with the specified parameter ID
 */
int8_t nvm_parameter_read(uint8_t partition_type,uint16_t ID,uint8_t *data)
{
	uint8_t return_value=0;
	uint16_t bit_length=read_len_from_nvm_idf(ID);
	if(partition_type==NVM_DATA)
	{
		if(ID < NVM_MAX_PARM)
		{
			return_value=NVM_read(ID,bit_length,data,nvm_parm_idx_by_id,primary_nvm_buff+NVM_HEADER_LEN);
		}
		else
		{
		}
		return return_value;
	}
	else
	{
		return NVM_INVALID_PARTITION_ID;
	}
}

/**
 * This API to write the data in NVM partition with the specified parameter ID
 */
int8_t nvm_parameter_write(uint8_t partition_type,uint16_t ID,uint8_t *data)
{
	//DEBUG_CPRINT(("NVM_PARAM_WRITE_CALL ID = %d\n",ID));
	int8_t ret=-1;
	uint16_t bit_length=read_len_from_nvm_idf(ID);
	if(partition_type==NVM_DATA)
	{
		if(sys_assert_sts==0)
		{
			os_sem_take(nvm_write_sem,os_wait_forever);
		}
		nvm_dirty_flag=1;
		ret = NVM_write(ID,bit_length,data,nvm_parm_idx_by_id,primary_nvm_buff+NVM_HEADER_LEN);
		(nvm_version>255)?nvm_version=0:nvm_version++;
		ret = NVM_write(NVM_VERSION,8,&nvm_version,nvm_parm_idx_by_id,primary_nvm_buff+NVM_HEADER_LEN);

		ret = nvm_crc_calc_and_store(primary_nvm_buff,nvm_length+NVM_HEADER_LEN);
		if(sys_assert_sts==0)
		{
			os_sem_give(nvm_write_sem);
		}
	}
	return ret;
}

/**
 * This API to generate byte array for the given parameter ID
 */
void nvm_gen_byte_array(uint16_t ID)
{
	uint16_t bit_length=read_len_from_nvm_idf(ID);
	DEBUG_CPRINT(("NVM GENERATE BYTE ARRAY PARAM ID ===%d\n",ID));
	int b;
	int temp;
	int line_len=25;
	int32_t byte_offset=nvm_parm_idx_by_id[ID]/8 ;
	int32_t bytes =(bit_length/8);
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wformat"
	DEBUG_CPRINT(("NVM PARAM byte offset ===%lu\n",byte_offset));
	DEBUG_CPRINT(("NVM PARAM byte length ===%lu\n",bytes));
#pragma GCC diagnostic pop
	DEBUG_CPRINT(("{"));
	while(bytes>0)
	{
		if((bytes- line_len)>0)
		{
			temp=line_len;
		}
		else
		{
			temp=bytes;
		}
		for(b=1;b<=temp;b++)
		{
			DEBUG_CPRINT(("0x%x,",primary_nvm_buff[byte_offset]));
			byte_offset++;
		}
		bytes=bytes-line_len;
		DEBUG_CPRINT(("\n"));
	}
	DEBUG_CPRINT(("}"));
}

/**
 * API to calculate the checksum and store the NVM data in the respected flash partitions
 */
int8_t nvm_commit()
{
	int8_t ret=0;
	// Need to check dirty bit and then do write as already latest information already available in flash already.
//		if((system_error==0))// && (disable_commit ==0))
		{
			if(nvm_dirty_flag==1)
			{
#ifndef LINUX_TEMP_PORT
				if(nvm_force_commit_flag==0)
				{
					rtc_set_time_date_nvm_shutdown();
				}
#else
				rtc_set_time_date_nvm_shutdown();
#endif
				if(sys_assert_sts==0)
				{
					os_sem_take(commit_sem,os_wait_forever);
					os_sem_take(nvm_write_sem,os_wait_forever);
				}
				nvm_dirty_flag=0;
				os_memcpy(temp_nvm_buff,primary_nvm_buff,nvm_length+NVM_HEADER_LEN);
				if(sys_assert_sts==0)
				{
					os_sem_give(nvm_write_sem);
				}

#ifndef LINUX_TEMP_PORT
					DEBUG_CPRINT(("NVM FLASH COMMIT START \n"));
					ret=write_nvm_partition_to_flashmem(NVM_FLASH_PARTITION_1_ADDR,temp_nvm_buff,nvm_length+NVM_HEADER_LEN);
					exo_wdt_refresh();
					ret=write_nvm_partition_to_flashmem(NVM_FLASH_PARTITION_2_ADDR,temp_nvm_buff,nvm_length+NVM_HEADER_LEN);
					os_timer_start(nvm_commit_timer,NVM_COMMIT_PERIODICITY);
					DEBUG_CPRINT(("NVM FLASH COMMIT END \n"));
					log_id(LOG_ERROR, LOG_LOGGER, NVM_FLASH_COMMIT_END);
#endif
				}
				if(sys_assert_sts==0)
				{
					os_sem_give(commit_sem);
				}
		}
	return ret;
}

uint8_t nvm_commit_periodicity_update(uint32_t time_sec)
{
	uint8_t sts ;
	if(os_timer_start(nvm_commit_timer,time_sec)== os_success)
	{

		sts = NVM_SUCCESS;
	}
	else
	{
		sts = NVM_UNKNOWN_ERROR;
	}

	return sts;
}

static uint8_t nvm_header_check(uint8_t* nvm_buff_ptr)
{
	uint8_t header_sts = 1;
#ifndef LINUX_TEMP_PORT                        
	uint32_t length = 0;
	uint8_t checksum = 0;
	uint16_t nvm_rev =0;

	for(int i=0; i<NVM_HEADER_LEN; i++)
	{
		checksum^= nvm_buff_ptr[i];
	}
	if (checksum == 0)
	{
		if(nvm_buff_ptr[0] == NVM_HEADER_MAGIC_BYTE)
		{
			nvm_rev = (nvm_buff_ptr[1] << 8 | nvm_buff_ptr[2] );
			if(get_nvm_revision_no() == nvm_rev)
			{
				length = (nvm_buff_ptr[3] << 24  | nvm_buff_ptr[4] << 16 |  \
						nvm_buff_ptr[5] << 8   | nvm_buff_ptr[6] );
				if(length == nvm_length)
				{
					header_sts = NVM_SUCCESS;
					//NVM length error
				}
				else
				{
					header_sts = NVM_INVALID_LEN;
				}
			}
			else
			{
				header_sts = NVM_VERSION_ERROR;
				// NVM version error
			}

		}
		else
		{
			header_sts = NVM_MAGIC_BYTE_ERROR;
			// header magic byte error

		}
	}
	else
	{
		header_sts = NVM_CRC_ERROR;
		//Header checksum error
	}
#endif
	return header_sts;
}

static uint8_t nvm_crc_check(uint8_t* nvm_buff_ptr, uint16_t length)
{
	uint8_t crc_sts=NVM_CRC_ERROR;

#ifndef LINUX_TEMP_PORT
	uint32_t crc_nvm;
	uint32_t crc_nvm_calc;
	    crc_nvm = (                                 \
	    nvm_buff_ptr[length-4]      |               \
		nvm_buff_ptr[length-3]<< 8  |               \
		nvm_buff_ptr[length-2]<<16  |               \
		nvm_buff_ptr[length-1]<<24
		          );
	    crc_nvm_calc = calc_checksum_memory(nvm_buff_ptr,length - 4);
		if(crc_nvm != crc_nvm_calc)
		{
			crc_sts=NVM_CRC_ERROR;
		}
		else
		{
			crc_sts=NVM_SUCCESS;
		}
#endif
	return crc_sts;
}

static uint8_t nvm_crc_calc_and_store(uint8_t* nvm_buff_ptr, uint16_t length)
{
	uint8_t sts = NVM_UNKNOWN_ERROR;
	uint32_t crc;
#ifndef	LINUX_TEMP_PORT
		crc=calc_checksum_memory(nvm_buff_ptr,length-4); // calculate the checksum without checksum field
#endif
		sts = NVM_write(NVM_CHECKSUM,32,(uint8_t*)&crc,nvm_parm_idx_by_id,nvm_buff_ptr+NVM_HEADER_LEN);
   return sts;
}





uint8_t* nvm_get_nvm_framework_bank_address(nvm_mem_storage_id bank_id)
{
#ifndef LINUX_TEMP_PORT
	if(NVM_STORAGE_BANK1 == bank_id)
	{
		return ext_mem_flash_nvm_bank1;
	}
	else if(NVM_STORAGE_BANK2 == bank_id)
	{
		return ext_mem_flash_nvm_bank2;
	}
	else if(NVM_STORAGE_RAM == bank_id)
	{
		return primary_nvm_buff;
	}
	else
	{
		return NULL;
	}
#else
	{
		return NULL;

	}
#endif

}


uint8_t nvm_get_nvm_bin_info(uint8_t *nvm_buff_ptr, nvm_firmware_info_def *info)
{
	uint8_t xor_cal = 0;

	for(int i = 0; i < NVM_HEADER_LEN; i++)
	{
		xor_cal^= nvm_buff_ptr[i];
	}

	if(xor_cal == 0)
	{
		if(nvm_buff_ptr[0] == NVM_HEADER_MAGIC_BYTE)
		{
			info->version_number_major = nvm_buff_ptr[1];
			info->version_number_minor = nvm_buff_ptr[2];
			info->size  = (nvm_buff_ptr[3] << 24  | nvm_buff_ptr[4] << 16 |  \
					  nvm_buff_ptr[5] << 8   | nvm_buff_ptr[6] );
			if(info->size > 16384 && info->size < 32768)
			{

			}
			else
			{
				return 4;
			}

			if(nvm_crc_check(nvm_buff_ptr, info->size+8) == NVM_SUCCESS)
			{
				return 0; // crc pass
			}
			else
			{
				return 3; // crc fail
			}

		}
		else
		{
			return 2;
			// header magic byte error
		}
	}
	else
	{
		return 1;
		//Header checksum error
	}
}
